CN113363317B - A kind of negative quantum capacitance device and preparation method thereof - Google Patents

Abstract

The invention discloses a negative quantum capacitance device and a preparation method thereof. The negative quantum capacitance device includes: a substrate; the buried gate is formed in the substrate, and the upper surface of the buried gate is flush with the upper surface of the substrate; the high-K dielectric layer/graphene layer/high-K dielectric layer lamination is formed on the buried gate, wherein the graphene layer is encapsulated between two high-K dielectric layers and is positioned above the buried gate, and the length of the graphene layer is equal to that of the buried gate and is smaller than that of the high-K dielectric layer; the two-dimensional material layer is formed on the high-K dielectric layer and used as a channel; and the source electrode and the drain electrode are respectively formed on the substrate and two sides of the two-dimensional material layer, partially cover the two-dimensional material layer and are not overlapped with the buried gate. The graphene layer provides a negative quantum capacitor, so that the total capacitance in the device is amplified, the subthreshold swing amplitude can be effectively reduced, and the switching speed of the device is improved.

Description

A kind of negative quantum capacitance device and preparation method thereof

technical field

The invention relates to the technical field of semiconductor logic devices, and in particular to a negative quantum capacitor device and a preparation method thereof.

Background technique

With the miniaturization of electronic nanodevices, the increasing power consumption in complementary metal-oxide-semiconductor (CMOS) circuits has become an urgent problem to be solved; The limit is limited by the Boltzmann limit of 60mV/dec. To address this issue, a variety of novel steep subthreshold swing device technologies have been proposed, including tunneling transistors (TFETs) and negative capacitance transistors (NCFETs). However, the too small driving current of the former greatly limits the practical application, and the switching speed of NCFET based on ferroelectric materials is limited by the slow ferroelectric switching time.

The negative quantum capacitance effect based on the two-dimensional metal system can also realize the internal voltage amplification mechanism similar to NCFET, and does not depend on ferroelectric materials, is not limited by the speed of ferroelectric flipping, and realizes subthreshold swing with faster switching speed Device performance with amplitudes less than 60mV/dec.

Contents of the invention

In order to solve the above problems, the present invention discloses a negative quantum capacitor device and a preparation method thereof, so as to reduce the subthreshold swing (SS) and increase the switching speed of the device.

The negative quantum capacitor device includes: a substrate; a buried gate formed in the substrate, the upper surface of which is flat with the upper surface of the substrate; a high-K dielectric layer/graphene layer/high-K dielectric layer stack formed on the On the buried gate, wherein the graphene layer is encapsulated between two high-K dielectric layers, located above the buried gate, and its length is equivalent to the length of the buried gate, but less than the length of the high-K dielectric layer; A three-dimensional material layer is formed on the high-K dielectric layer as a channel; a source electrode and a drain electrode are respectively formed on the substrate, on both sides of the two-dimensional material layer, and partially cover the two-dimensional material layer , and has no overlap with the buried gate, wherein the graphene layer provides negative quantum capacitance, which amplifies the total internal capacitance of the device, thereby reducing the subthreshold swing.

In the negative quantum capacitance device of the present invention, preferably, the graphene layer is a monoatomic layer.

In the negative quantum capacitor device of the present invention, preferably, the high-K dielectric layer is Al ₂ O ₃ , HfO ₂ , ZrO ₂ , or HZO.

In the negative quantum capacitance device of the present invention, preferably, the two-dimensional material layer is MoS ₂ , WS ₂ .

In the negative quantum capacitance device of the present invention, preferably, the substrate is Si/SiO ₂ .

The invention also discloses a method for preparing a negative quantum capacitor device, comprising the following steps: forming a buried gate in a substrate so that its upper surface is flat with the upper surface of the substrate; forming a high-K dielectric layer/ The graphene layer/high-K dielectric layer is stacked so that it covers the buried gate, wherein the graphene layer is encapsulated between two high-K dielectric layers, located above the buried gate, and its length is equivalent to the length of the buried gate , less than the length of the high-K dielectric layer; transfer the two-dimensional material layer to the high-K dielectric layer as a channel so that it covers the high-K dielectric layer; on the substrate, the two-dimensional A source electrode and a drain electrode are formed on both sides of the material layer, the source electrode and the drain electrode partially cover the two-dimensional material layer respectively, and do not overlap with the buried gate, wherein the graphene layer provides a negative quantum capacitance, so that The total capacitance inside the device is amplified, thereby reducing the subthreshold swing.

In the preparation method of the negative quantum capacitor device of the present invention, preferably, the graphene layer is a monoatomic layer.

In the preparation method of the negative quantum capacitor device of the present invention, preferably, the high-K dielectric layer is Al ₂ O ₃ , HfO ₂ , ZrO ₂ , HZO.

In the preparation method of the negative quantum capacitance device of the present invention, preferably, the two-dimensional material layer is MoS ₂ , WS ₂ .

In the preparation method of the negative quantum capacitor device of the present invention, preferably, the high-K dielectric layer is formed at 300°C by atomic layer deposition.

When the carrier density is low enough, the electron-electron interactions in 2D materials are strong, leading to negative quantum capacitance (QC). Graphene is a two-dimensional honeycomb structure composed of carbon atoms, with inherent two-dimensional semi-metallic properties, when the Fermi energy ( _EF ) is located near the Dirac point, the density of states (DOS) and carrier density are very low , which precisely provides negative quantum capacitance (NQC). The invention encapsulates the graphene in the gate stack, obtains a smaller sub-threshold swing (SS) by enlarging the internal capacitance, and improves the switching speed of the device. It is expected to break the Boltzmann limit of the subthreshold swing of field effect transistors at room temperature, and make progress in the preparation of high-speed and low-power devices.

Description of drawings

Fig. 1 is a flow chart of a method for preparing a negative quantum capacitor device.

FIG. 2 is a schematic diagram of a device structure after forming a buried gate.

FIG. 3 is a schematic diagram of the device structure after forming a high-K dielectric layer/graphene layer/high-K dielectric layer stack.

Fig. 4 is a schematic diagram of the device structure after forming a two-dimensional material layer.

Fig. 5 is a schematic diagram of the structure of a negative quantum capacitance device.

Fig. 6 is an equivalent circuit of a negative quantum capacitance device.

detailed description

In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. It should be understood that the specific The examples are only used to explain the present invention, not to limit the present invention. The described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical" and "horizontal" are based on the orientation or positional relationship shown in the drawings, and are only for convenience The present invention is described and simplified descriptions do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed and operate in a specific orientation, and thus should not be construed as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only, and should not be understood as indicating or implying relative importance.

In addition, many specific details of the present invention, such as structures, materials, dimensions, processing techniques and techniques of devices, are described below for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. Unless otherwise specified below, each part in the device can be composed of materials known to those skilled in the art, or materials with similar functions developed in the future can be used.

Fig. 1 is a flow chart of a method for preparing a negative quantum capacitor device. As shown in Figure 1, in step S1, UV lithography is carried out on the cleaned Si100/SiO ₂ 101 substrate, wherein the thickness of the SiO ₂ layer 101 is 285 nm, and a series of gate electrodes (pads) of 160 μm×160 μm are photoetched. ). Then, the SiO ₂ layer 101 was etched by reactive ion etching (RIE) to obtain a trench with a depth of 85 nm. Wherein, the etching gas is CHF ₃ , the volume flow rate is 30 sccm, the pressure is 1.3 Pa, the RF power is 90 W, the etching rate is 20 nm/min, and the etching process lasts for 4 min15 s. Afterwards, Ti/Pt is deposited to form the metal buried gate 102, and the obtained structure is shown in FIG. 2 . Wherein, the thickness of the Ti layer is 15 nm, and the thickness of the Pt layer is 70 nm.

In step S2, a high-K dielectric layer/graphene layer/high-K dielectric layer stack is formed. Specifically, firstly, Al ₂ O ₃ with a thickness of 10 nm is deposited on the substrate as the first high-K dielectric layer 103 by atomic layer deposition (ALD) at 300° C. However, the present invention is not limited thereto, and HfO ₂ , ZrO ₂ , Hf _x Zr _(1-x) O ₂ (HZO) and the like can also be used as the high-K medium. Then, the monoatomic layer graphene layer 104 is transferred to the first high-K dielectric layer 103 by using a mechanical lift-off method, and is positioned above the range of the buried gate 102 . The length of the graphene layer 104 is equivalent to the length of the buried gate 102 and is shorter than the length of the first high-K dielectric layer 103 . Next, at 300°C, use ALD to deposit 10nm-thick Al ₂ O ₃ as the second high-K dielectric layer 105 covering the graphene layer 104, so that the graphene layer 104 is encapsulated between the two high-K dielectric layers 103,105 , the resulting structure is shown in Figure 3.

In step S3, the two-dimensional material layer 106, such as MoS ₂ , is mechanically peeled off onto the second high-K dielectric layer 105 as a channel so that it covers the second high-K dielectric layer 105, and the resulting structure is shown in FIG. 4 Show.

In step S4, the source and drain are photoetched using electron beam lithography, and then Ti/Au is deposited as source electrode 107 and drain electrode 108 by physical vapor deposition (PVD). The resulting structure is as shown in Figure 5, source electrode 107 and The drain electrodes 108 are respectively formed on the substrate, on both sides of the two-dimensional material layer 106 , partially cover the two-dimensional material layer 106 , and do not overlap with the buried gate 102 . Wherein, the thickness of the Ti layer is 15nm, and the thickness of the Au layer is 70nm.

As shown in Figure 5, the negative quantum capacitor device of the present invention includes: substrate Si100/SiO ₂ 101; buried gate 102, formed in the substrate, its upper surface is flat with the substrate upper surface; the first layer of high-K dielectric Layer 103/graphene layer 104/second layer of high-K dielectric layer 105 is stacked and formed on the buried gate 102, wherein the graphene layer 104 is encapsulated between two high-K dielectric layers 103, 105 and located above the buried gate 102, Its length is equivalent to the length of the buried gate 102, which is less than the length of the high-K dielectric layers 103 and 105; the two-dimensional material layer 106 is formed on the second high-K dielectric layer 105 as a channel; the source electrode 107 and the drain electrode 108 are respectively formed on the substrate The bottom, the two sides of the two-dimensional material layer 106 , and partially cover the two-dimensional material layer 106 , and do not overlap with the buried gate 102 .

In order to illustrate the principles and effects of the present invention more clearly, an equivalent circuit of a negative quantum capacitor device is shown in FIG. 6 . Among them, C _{High k} is the dielectric capacitance, C _Q , C _Semic. are graphene quantum capacitance and channel semiconductor capacitance respectively. V _G , V ₀ and φ _s are gate bias voltage, graphene potential and semiconductor surface potential, respectively.

Field effect transistors (FETs) can be regarded as a series of capacitors connected in series, and the total capacitance C _total is a series connection of geometric capacitance C _geom (C _geom ^-1 =2C _Highk ^-1 +C _Semic ^-1 ) and quantum capacitance C _Q .

C _total ^-1 ＝C _geom ^-1 +C _Q ^-1

Graphene is a two-dimensional honeycomb structure composed of carbon atoms, with inherent two-dimensional semi-metallic properties, when the Fermi energy ( _EF ) is located near the Dirac point, the density of states (DOS) and carrier density are very low , which precisely provides negative quantum capacitance (NQC). When C _Q is negative, the total capacitance C _total will be amplified. Smaller subthreshold swing (SS) can be achieved in the device by amplifying the internal capacitance.

It should be noted that, in the above embodiments, graphene is encapsulated in the gate stack, and the two-dimensional material MoS ₂ is used as the channel, but the present invention is not limited thereto, and other two-dimensional materials such as WS ₂ can also be selected. Various combinations are made according to its properties to obtain ideal devices and performance. In addition, the number of stacked layers and the way of combination can also be adjusted according to actual needs. In addition, because the transfer technology of two-dimensional materials has low selectivity to substrates, devices based on different substrates can be prepared according to specific needs.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention.

Claims (8)

1. A negative quantum capacitor device, characterized in that, include: Substrate; a buried gate formed in the substrate, the upper surface of which is flush with the upper surface of the substrate; A high-K dielectric layer/graphene layer/high-K dielectric layer stack is formed on the buried gate, wherein the graphene layer is encapsulated between two high-K dielectric layers, located above the buried gate, and its length is the same as the buried gate. The length of the buried gate is equivalent, less than the length of the high-K dielectric layer, and the thickness of the high-K dielectric layer is 10nm; a two-dimensional material layer formed on the high-K dielectric layer as a channel; A source electrode and a drain electrode are respectively formed on the substrate, on both sides of the two-dimensional material layer, partially cover the two-dimensional material layer, and do not overlap with the buried gate, Wherein, the graphene layer provides negative quantum capacitance, which amplifies the total capacitance inside the device, thereby reducing the subthreshold swing, and the two-dimensional material layer is MoS ₂ or WS ₂ . 2. negative quantum capacitance device according to claim 1, is characterized in that, The graphene layer is a monoatomic layer. 3. negative quantum capacitance device according to claim 1, is characterized in that, The high-K dielectric layer is Al ₂ O ₃ , HfO ₂ , ZrO ₂ or HZO. 4. negative quantum capacitance device according to claim 1, is characterized in that, The substrate is Si/SiO ₂ . 5. A method for preparing a negative quantum capacitor device, characterized in that, Include the following steps: forming a buried gate in the substrate such that its upper surface is flush with the upper surface of the substrate; A high-K dielectric layer/graphene layer/high-K dielectric layer stack is formed on the substrate so that it covers the buried gate, wherein the graphene layer is encapsulated between two high-K dielectric layers and is located on the buried gate. above the gate, the length of which is equivalent to the length of the buried gate and less than the length of the high-k dielectric layer, and the thickness of the high-k dielectric layer is 10nm; transferring a two-dimensional material layer onto the high-K dielectric layer as a channel so that it covers the high-K dielectric layer; Forming a source electrode and a drain electrode on both sides of the two-dimensional material layer on the substrate, the source electrode and the drain electrode respectively partially cover the two-dimensional material layer and do not overlap with the buried gate, Wherein, the graphene layer provides negative quantum capacitance, which amplifies the total capacitance inside the device, thereby reducing the subthreshold swing, and the two-dimensional material layer is MoS ₂ or WS ₂ . 6. negative quantum capacitance device preparation method according to claim 5, is characterized in that, The graphene layer is a monoatomic layer. 7. negative quantum capacitance device preparation method according to claim 5, is characterized in that, The high-K dielectric layer is Al ₂ O ₃ , HfO ₂ , ZrO ₂ or HZO. 8. negative quantum capacitance device preparation method according to claim 7, is characterized in that, The high-K dielectric layer is formed at 300° C. by atomic layer deposition.

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