CN113376999B - A Special Adder for High Temporal Resolution Time-to-Digital Converters - Google Patents

Abstract

The patent of the present invention proposes a design method and circuit implementation of a special adder for a time-to-digital converter (TDC) with large dynamic measurement range and high resolution performance, mainly including gray code and binary code conversion module (1), Self-calibration module (2) and internal logic module (3). The special adder proposed by the present invention is mainly used to realize the addition and merging of the integer part and the fractional part count value in the time-to-digital converter, and not only can combine the cycle integer part values and The values of the fractional parts are summed and converted into standard binary codes, and it also has a certain error correction capability in timing, which can ensure the correctness of TDC measurement to value conversion throughout the time.

Description

A Special Adder for High Temporal Resolution Time-to-Digital Converters

technical field

The technical problem to be solved by the present invention is to provide a circuit for a special adder of a time-to-digital converter (TDC) with high time resolution, which relates to the technical field of digital integrated circuits.

Background technique

The time-to-digital converter is a conversion device from analog to digital in the time domain, which has characteristics very similar to those of an analog-to-digital converter (ADC). TDC is a device mainly used to complete time measurement. It has high measurement resolution and is widely used in various application fields that need to convert time into numerical value. The application of TDC in the above fields has high requirements for its time measurement resolution, which has prompted scholars in this research field to continuously pursue the TDC circuit architecture to achieve higher time measurement resolution, which also makes the TDC The circuit structure has undergone earth-shaking changes, from the original simple delay chain type to various two-stage conversion types (such as coarse-fine TDC) proposed recently. For now, the time measurement resolution of TDC has been able to break through 1ps, and There is a move towards smaller measurement resolutions.

Although the time measurement resolution of TDC has been greatly improved in recent years, the performance of related system equipment applied to this characteristic of TDC has also been greatly improved, but this does not give more importance to TDC relative to measurement resolution. System equipment with a dynamic measuring range brings the same benefits. This is because with the improvement of TDC measurement time resolution, its corresponding dynamic measurement range has not been improved as well, and it is often exchanged at the expense of dynamic measurement range. For example, at present, for TDC with a measurement resolution of about 1 ps, its dynamic measurement range is often only a dozen nanoseconds or even a few nanoseconds, which is far from enough for TDC used in lidar ranging.

In order to realize a TDC with a large measurement dynamic range and a higher time measurement resolution that can be applied to lidar ranging, the cycle integer multiple count value and the fractional multiple count value generated by the ring oscillator (RO) in the TDC are now usually carried out. Summed and converted to standard binary values. However, because the counting results of the integer part and the fractional part represent different bases, the two counting results cannot be added directly; and due to the existence of device delay, adding a jump in the integer part and clearing the fractional part It is not completely synchronized, so that there is a serious deviation in the measured value, which affects the accuracy of time measurement.

Contents of the invention

In order to solve the above-mentioned problems, the present invention designs and implements a special adder that is applied in a TDC with a large measurement dynamic range and a relatively high time measurement resolution, and can perform addition between different base input values and has an error correction function at the same time circuit scheme. The input of the special adder used in the time-to-digital converter with high time resolution in the present invention includes the 16-bit gray code counting result A of the rough counter in the time-to-digital converter, and the 6-bit binary code counting result A of the fine counter decoder in the time-to-digital converter C, the two frequency division signal of the counting clock, the output is 24 bits representing the binary value RESULT of the measurement duration; it is characterized in that the special adder includes: Gray code and binary code conversion module 1, self-calibration module 2 and internal logic module 3;

The gray code and binary code conversion module 1 is used to convert the 16-bit gray code counting result A of the coarse counter in the time-to-digital converter into corresponding binary for subsequent operations;

The self-calibration module 2 is based on the 16-bit Gray code counting result A of the coarse counter, the 6-bit binary code C of the decoder and the frequency-divided signal of the counting clock to perform self-calibration on the conversion result B of the binary code corresponding to the 16-bit Gray code conversion. Calibration to ensure that correct results can still be given when non-ideal conditions caused by circuit delays occur, improving data accuracy and reliability;

The internal logic module 3 is used to process the 16-bit calibrated binary code result E, convert it according to a specific logic, and then add it to the 6-bit binary code C of the decoder to solve the problem corresponding to the least significant bit The problem is that the decimal number 63 cannot be expressed in binary.

The above-mentioned self-calibration module 2 includes a self-adding one module, a selector module and a selector logic judgment module; wherein: the self-adding one module input is converted to the corresponding 16-bit Gray code output by the Gray code and the binary code conversion module. The conversion result B of the binary code of the binary code is output as the 16-bit self-increment result D after it is added by one; the input of the two-choice selector module is converted into the corresponding 16-bit Gray code output by the Gray code and the binary code conversion module The conversion result B of the binary code, the 16-bit self-addition result D output by the self-addition module and the selector control signal SEL output by the selector logic judgment module; the selector control signal controls the two-to-one selector module to output 16 bits The calibrated binary code result E; the selector logic judgment module is based on the highest bit of the counting result C of the 6-bit binary code of the input decoder, the lowest bit of the counting result A of the 16-bit Gray code of the coarse counter, and the frequency-divided signal of the counting clock by two Combination logic operations are performed according to a specific relationship, and a selector control signal SEL is output.

The above-mentioned internal logic module (3) includes standard binary code conversion and common adder according to specific rules; 6-bit binary code counting result C of the decoder, 16 calibrated binary code results (E) output by the self-calibration module ; Perform standard binary code conversion according to specific rules, shift the 16-bit binary code result output by the self-calibration module by 6 bits to the left as a whole, and subtract its own value to obtain the real binary number result F, and then combine it with 6 24-bit binary value RESULT representing the measurement duration is obtained by direct addition of binary codes.

Compared with the prior art, the present invention has the following advantages:

1. It is not necessary to output the coarse and fine counting results to the external device for storage and calculation, but can be output to the register in the TDC circuit for storage after passing through the special adder, so that the external device can directly obtain the result;

2. There is no need to output the coarse and fine counting results separately, which solves the problem that the coarse and fine counting results cannot be directly merged and added due to the different base systems of the coarse and fine counting results;

3. Through the self-calibration function, the correct result can still be given when the non-ideal situation caused by the circuit delay occurs, which improves the accuracy and reliability of the data.

Description of drawings

Fig. 1 is the realization block diagram of special adder of the present invention;

Fig. 2 is the concrete block diagram of each module of special adder of the present invention;

Fig. 3 is a block diagram of the core structure of the special adder of the present invention applied to TDC.

detailed description

In order to make the technical characteristics, circuit configuration, functions and usage scenarios of the present invention intuitive and easy to understand, the following will further explain the present invention in conjunction with the diagrams. In the following expressions, unless otherwise specified, the terms "VDD", "GND", "connection "It should be understood in a broad sense.

With reference to Fig. 1 and Fig. 2, the special adder of the present invention comprises 3 inputs, is respectively the 16-bit Gray code counting result A of the rough counter in the time-to-digital converter, and the 6-bit binary code counting result A of the fine counter decoder in the time-to-digital converter The result C and the two-frequency signal of the counting clock; its output is a 24-bit binary value RESULT representing the measurement duration. According to the function, the special adder of the present invention includes a gray code and binary code conversion module 1, a self-calibration module 2 and an internal logic module 3;

The Gray code and binary code conversion module 1 has an input of the 16-bit Gray code counting result A of the coarse counter, and an output of the conversion result B of the 16-bit Gray code converted into the corresponding binary code. Due to the characteristics of only one bit of gray code jumping each time, the application in circuit design has the characteristics of reducing power consumption and improving the accuracy of data transmission. The count value is counted using Gray code. The fine count value representing the fractional part normally uses binary, so the gray code counting result of the coarse counter must first be converted to the corresponding binary for subsequent operations.

The self-calibration module is provided with 4 inputs, which are the counting result A of the 16-bit Gray code of the coarse counter, the conversion result B of the corresponding binary code converted from the 16-bit Gray code, and 6 bits of the fine counter decoder in the time-to-digital converter. The binary code counting result C and the frequency-divided signal of the counting clock; the output is the 16-bit calibrated binary code result E. Ideally, when the ring oscillator just completes one oscillation cycle, the count value of the coarse counter is increased by one, and the input of the sampling latch returns to the initial state at the same time. Due to the existence of device delay, the output of the decoder is always It will be earlier or later than the addition process of the coarse counter, which will cause serious deviations in the measured value. The self-calibration module is designed to ensure correct results in the presence of non-ideal conditions caused by circuit delays. It is characterized in that it includes a self-increasing module, a selector module for selecting one of two, and a selector logic judgment module, wherein:

The self-increment module input is the conversion result B of the 16-bit Gray code output by the Gray code and the binary code conversion module is converted into the corresponding binary code, and the output is the 16-bit self-increment result D after it is added by one;

The input of the two-to-one selector module is Gray code and the 16-bit Gray code output by the binary code conversion module is converted into the conversion result B of the corresponding binary code, and the 16-bit self-increment result D output by the self-increment module is judged by the logic of the selector The selector control signal SEL output by the module controls the two-to-one selector module to output the 16-bit calibrated binary code result E through the selector control signal;

The logic judgment module of the selector performs combinational logic operation on the counting result A of the 6-bit binary code of the input decoder and the lowest bit of the counting result A of the 16-bit Gray code of the coarse counter according to a specific relationship, and outputs The selector control signal SEL.

The internal logic module has two inputs, the 16-bit calibrated binary code result E and the 6-bit binary code C from the decoder. The least significant bit in the 16-bit Gray code corresponds to the decimal number 63, which cannot be expressed by 2n, n>=1. Therefore, it cannot be directly added or shifted and added to the 6-bit binary code, so it needs to be converted according to a specific logic and then added. It is characterized in that: perform standard binary code conversion according to specific rules, shift the 16-bit binary code result output by the self-calibration module by 6 bits to the left as a whole, and subtract its own value to obtain the real binary number result F, Then directly add the 6-bit binary code to obtain the 24-bit binary value RESULT representing the measurement duration.

Fig. 3 is a block diagram of the core structure of a special adder of the present invention applied to a TDC circuit with a large measurement dynamic range and a higher measurement time resolution, and it includes a ring oscillator RO composed of delay units represented by 63 inverters, 63 A sampling latch and its corresponding fine counter, coarse counter and special adder of the present invention. When the rising edge of the start measurement signal "Start" arrives, the RO starts to run and enables the coarse counter at the same time. Whenever the clock input of the coarse counter comes with a rising edge, the coarse counter starts to increment by one. It is worth noting that in order to ensure that the time required for the coarse counter to add one each time is approximately equal, the form of Gray code counting is used here. When the rising edge of the stop signal "Stop" arrives, on the one hand, it will latch the count value in the coarse counter and then send it to the adder; The voltage value is sampled, and a 6-bit binary code is obtained through a fine counter. The least significant bit in the 6-bit binary code determines the measurement time resolution of the TDC, which is equal to the transmission delay of two inverters, that is, LSB=2 ^τ , where τ>0 is the transmission of a single inverter delay. It can be seen that the count value in the coarse counter represents the integer number of cycles oscillated by the ring oscillator, while the 6-bit binary number output by the sampling latch and the fine counter represents the fractional count value of less than one oscillation cycle. The total count value representing the time difference between the rising edges of the "Start" and "Stop" signals shall be the count value in the coarse counter plus the output of the fine counter.

The internal logic operation flow of a special adder for a time-to-digital converter with high time resolution disclosed by the present invention is as follows:

(1) The Gray code and binary code conversion module converts the 16-bit Gray code counting result A of the TDC coarse counter into the corresponding binary B, and inputs it into the self-calibration module. The conversion method of Gray code to binary code is to reserve the highest bit of Gray code as the highest bit of binary code, and the second highest bit binary code is the XOR value of the upper bit binary code and the second highest bit Gray code. By analogy, the current binary code to be output is the XOR output of its upper binary bit and the current bit Gray code.

The conversion rule from Gray code to binary code can be summarized as the following expression:

Where n≥1, 1≤i≤n, G _n-1 G _n-2 ... G ₁ G ₀ represents the Gray code to be converted, B _n-1 B _n-2 ... B ₁ B ₀ represents the conversion to the binary code.

(2) The self-calibration module inputs the conversion result B of the binary code after the 16-bit conversion and the 16-bit self-increment result D after the self-increment into the two-to-one selector, and the selector logic judgment module is based on the input translation The highest bit of the counting result C of the 6-bit binary code of the encoder, the lowest bit of the counting result A of the 16-bit Gray code of the coarse counter, the frequency-divided signal of the counting clock is combined with logic operations according to a specific relationship, and the selector control signal SEL is generated to control the two Select the result output of a selector. Correctly determine whether to send the converted binary code without adding 1 or the converted binary code with 1 added to the next-level module circuit for processing. The selector control signal SEL is the output of the judging logic circuit, and it is also the selection control signal of the one-of-two selector. When SEL=0, the binary code obtained by directly converting the gray code is selected and output; when SEL=1, the selected output The binary code after adding "1". SEL can be represented by a logical expression as shown below:

div_2始终为1，此时选择控制信号SEL主要取决于细计数器计数结果的最高位decoder[5]。Among them, fake_binary[0] is the lowest bit of the pseudo binary code directly converted into 16bit gray code; div_2 is the frequency division signal of the counting clock, which jumps when the falling edge of the counting clock arrives; decoder[5] is the 6bit fine The highest bit signal of the counter counting result. From the characteristics of the output signal of the coarse counter (Gray code), it can be seen that before and after adding "1" to the coarse count, that is, before and after the ring oscillator completes two revolutions, fake_binary[0]

div_2 is always 1, at this time the selection control signal SEL mainly depends on the highest bit decoder[5] of the counting result of the fine counter.

(3) The internal logic module shifts the 16-bit 16-bit binary code result E output by the self-calibration module to the left by 6 bits as a whole, and subtracts its own value to obtain the real binary number result F, which is then combined with the decoder The 6-bit binary code C is directly added, and finally a 24-bit binary value RESULT representing the measurement duration is obtained.

So far, the description of the structure of the entire circuit of the present invention from the circuit modules, the operating principle of each module, and the processing of data by each module has been completed.

The above-described embodiment is only a typical example of the present invention, and the present invention is not limited to this embodiment. Obviously, various modifications, transformations and deformations can be made under the concept of the present invention, so the description and the accompanying drawings are all illustrative Without limitation, any modifications and changes made to the above embodiments according to the essence of the present invention shall belong to the protection scope of the present invention.

Claims (1)

1. A special adder for a time-to-digital converter with high time resolution, the input of the special adder includes the 16-bit Gray code counting result A of the rough counter in the time-to-digital converter, and the translation of the fine counter in the time-to-digital converter The 6-bit binary code counting result C of the coder, the two-frequency signal of the counting clock, outputs a 24-bit binary value RESULT representing the measurement duration; It is characterized in that the special adder includes: Gray code and binary code conversion module (1), self-calibration module (2) and internal logic module (3); The gray code and binary code conversion module (1) is used to convert the 16-bit gray code counting result A of the rough counter in the time-to-digital converter into corresponding binary for subsequent operations; The self-calibration module (2) is based on the 16-bit Gray code counting result A of the rough counter, the 6-bit binary code C of the decoder and the two-frequency signal pair 16 of the counting clock are the conversion result B of the binary code corresponding to the Gray code conversion Carry out self-calibration to ensure that correct results can still be given when non-ideal conditions caused by circuit delays occur, improving data accuracy and reliability; The above-mentioned self-calibration module (2) includes a self-increasing module, a selector module and a selector logic judgment module; wherein: the self-increasing module input is the 16-bit Gray code conversion of the Gray code and the binary code conversion module output It is the conversion result B of the corresponding binary code, and the output is the 16-bit self-increment result D after it is added by one; the input of the two-choice selector module is the conversion of the 16-bit Gray code output by the Gray code and the binary code conversion module is the conversion result B of the corresponding binary code, the 16-bit self-addition result D output by the self-addition module and the selector control signal SEL output by the selector logic judgment module; the output of the two-to-one selector module is controlled by the selector control signal 16-bit calibrated binary code result E; the selector control signal SEL output by the selector logic judgment module can be represented by a logical expression as shown below:

Among them, fake_binary[0] is the lowest bit of the 16-bit Gray code counting result A of the rough counter, div_2 is the frequency division signal of the counting clock by two, and decoder[5] is the highest bit of the 6-bit binary code counting result C of the decoder; The internal logic module (3) is used to process the 16-bit calibrated binary code result E, shift the 16-bit binary code result E to the left by 6 bits, and subtract its own value to obtain the true The binary number result F is directly added to the 6-bit binary code to obtain the 24-bit binary value RESULT representing the measurement duration, so as to solve the problem that the least significant bit corresponds to the decimal number 63, which cannot be expressed in binary.

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