CN113381589B - Power supply device and pulse frequency modulation method - Google Patents
Power supply device and pulse frequency modulation method Download PDFInfo
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- CN113381589B CN113381589B CN202010116302.0A CN202010116302A CN113381589B CN 113381589 B CN113381589 B CN 113381589B CN 202010116302 A CN202010116302 A CN 202010116302A CN 113381589 B CN113381589 B CN 113381589B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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Abstract
The power supply device comprises pulse frequency modulation controller circuit system and period controller circuit system. The pulse frequency modulation controller circuit system is used for adjusting the change speed of the first signal according to at least one control bit, comparing the first signal with a first reference voltage to generate a second signal, and generating a driving signal to the power conversion circuit according to the output voltage, the second reference voltage and the second signal, wherein the power conversion circuit is used for generating the output voltage according to the driving signal. The period controller circuitry is configured to detect a frequency of the driving signal based on a clock signal having a predetermined frequency to adjust at least one control bit, wherein the predetermined frequency is set based on a human ear hearing range.
Description
Technical Field
The present disclosure relates to power supply devices, and more particularly, to a power supply device with a pulse frequency modulation mechanism and a modulation method thereof.
Background
Power supply devices are commonly used in various electronic devices to provide a stable supply voltage to the internal circuitry of the electronic device. In electronic devices for audiovisual applications (e.g., cell phones, wireless headphones, wireless speakers, etc.). In practical applications, noise may be generated during the switching operation in the power supply device. As such, the user may hear these noises while using the electronic device, resulting in poor user experience.
Disclosure of Invention
In some embodiments, the power supply includes pulse frequency modulation controller circuitry and period controller circuitry. The pulse frequency modulation controller circuit system is used for adjusting the change speed of the first signal according to at least one control bit, comparing the first signal with a first reference voltage to generate a second signal, and generating a driving signal to the power conversion circuit according to the output voltage, the second reference voltage and the second signal, wherein the power conversion circuit is used for generating the output voltage according to the driving signal. The period controller circuitry is configured to detect a frequency of the driving signal based on a clock signal having a predetermined frequency to adjust the at least one control bit, wherein the predetermined frequency is set based on a human ear hearing range.
In some embodiments, the pulse frequency modulation method includes the operations of: adjusting the change speed of the first signal according to at least one control bit, and comparing the first signal with a first reference voltage to generate a second signal; generating a driving signal to a power conversion circuit according to the output voltage, the second reference voltage and the second signal, wherein the power conversion circuit is used for generating the output voltage according to the driving signal; and detecting the frequency of the driving signal according to a clock pulse signal with a preset frequency to adjust at least one control bit, wherein the preset frequency is set based on the human ear hearing frequency range.
The features, implementation and effects of the present invention are described in detail below with reference to the preferred embodiments shown in the drawings.
Drawings
FIG. 1 is a schematic diagram illustrating a power supply device according to some embodiments of the present disclosure;
FIG. 2A is a schematic diagram illustrating circuitry of the Pulse Frequency Modulation (PFM) controller of FIG. 1, according to some embodiments of the present disclosure;
FIG. 2B is a schematic diagram illustrating circuitry of the PFM controller of FIG. 1, according to some embodiments of the present disclosure;
FIG. 3 is a waveform diagram illustrating the plurality of signals of FIG. 2A (or FIG. 2B) according to some embodiments of the present disclosure;
FIG. 4 is a flowchart illustrating operation of the cycle controller circuitry of FIG. 1, according to some embodiments of the present disclosure;
FIG. 5A is a schematic waveform diagram illustrating a portion of the signal of FIG. 1 according to some embodiments of the present disclosure;
FIG. 5B is a schematic waveform diagram illustrating a portion of the signals of FIG. 1 according to some embodiments of the present disclosure; and
Fig. 6 is a flow chart illustrating a PFM method according to some embodiments of the present disclosure.
Detailed Description
All terms used herein have their ordinary meaning. The foregoing definitions of words and phrases in commonly used dictionaries, including any examples of use of words and phrases in this patent document are provided by way of example only and should not be limiting in scope and meaning. Similarly, the present disclosure is not limited to the various embodiments shown in this specification.
As used herein, "coupled" or "connected" may mean that two or more elements are in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and may also mean that two or more elements are in operation or action with each other. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuit" may be a device connected in a manner by at least one transistor and/or at least one active and passive component to process a signal.
As used herein, the term "and/or" includes any combination of one or more of the listed associated items. First, second, third, etc. words are used herein to describe and identify various components. Accordingly, a first component may also be referred to herein as a second component without departing from the intent of the present disclosure. For ease of understanding, like components in the drawings will be designated with the same reference numerals.
Fig. 1 is a schematic diagram illustrating a power supply device 100 according to some embodiments of the present disclosure. In some embodiments, the power supply device 100 may be applied to various types of electronic devices (e.g., cell phones, wireless headphones, bluetooth speakers, etc.). The power supply device 100 can prevent the frequency of the internal electronic signal from falling into the auditory frequency range of the human ear (the frequency is about 20-20 kilohertz (kHZ)), so as to prevent the noise of the electronic device from affecting the auditory perception of the user.
The power supply 100 includes power conversion circuitry 110, period controller circuitry 120, and pulse frequency modulation (pulse frequency modulation, PFM) controller circuitry 130. The power conversion circuit 110 converts the voltage V CC into an output voltage S O according to the driving signal S D. The power conversion circuit 110 includes a buffer 111, a buffer 112, a transistor TP, a transistor TN, an inductance L, and a capacitance C. The transistor TP receives the driving signal S D via the buffer 111. The transistor TN receives the driving signal S D via the buffer 112. The transistor TP is a P-type transistor, which is turned on according to the driving signal S D to charge the capacitor C through the inductor L. Thus, the output voltage S O will rise. The transistor TN is an N-type transistor, which is turned on according to the driving signal S D to discharge the capacitor C through the inductor L. Thus, the output voltage S O will drop. The above-mentioned arrangement of the power conversion circuit 110 is used as an example, and the disclosure is not limited thereto. For example, in some alternative embodiments, buffer 111 and/or buffer 112 may not be provided. In other words, the transistor TP and/or the transistor TN can directly receive the driving signal S D.
The period controller circuitry 120 detects the frequency of the driving signal S D to adjust the at least one control bit BI according to the clock signal S CLK having a predetermined frequency (e.g., F CLK in fig. 5A). In some embodiments, the preset frequency of the clock signal S CLK is set based on the human ear hearing frequency range. For example, the predetermined frequency may be set to 32kHZ, which is higher than the highest frequency of the auditory frequency range of the human ear, but the present invention is not limited thereto. As described later, the period controller circuitry 120 may adjust at least one control bit BI to avoid the frequency of the driving signal S D falling within the human ear hearing frequency range. The PFM controller circuitry 130 generates the driving signal S D according to at least one control bit BI, the reference voltage S REF1, the reference voltage S REF2, and the output voltage S O.
Fig. 2A is a schematic diagram illustrating PFM controller circuitry 130 of fig. 1, according to some embodiments of the present disclosure. In some embodiments, the PFM controller circuitry 130 adjusts the rate of change of the signal S 1 on the node N1 according to the at least one control bit BI, and compares the signal S 1 with the reference voltage S REF1 to generate the signal S 2. The PFM controller circuitry 130 further generates a driving signal S D according to the output voltage S O, the reference voltage S REF2, and the signal S 2.
For ease of illustration, FIG. 2A is illustrated with at least one control bit BI comprising 4 control bits B0-B3. It should be appreciated that the number of bits in the at least one control bit BI is not limited thereto. PFM controller circuitry 130 includes switched capacitor array circuit 210, switch SW1, current source circuit 215, switch SW2, comparator circuit 220, and inverter circuit 230. The switched capacitor array circuit 210 determines the capacitance of the node N1 according to the control bits B0-B3. For example, the switched capacitor array circuit 210 includes a plurality of capacitors CU and a plurality of switches SWU. The first ends of the capacitors CU are coupled to ground. Each of the switches SWU is coupled between the second end of a corresponding one of the capacitors CU and the node N1, and is turned on according to a corresponding one of the control bits B0-B3. The larger the number of on-switches among the plurality of switches SWU, the larger the number of capacitors CU that can be connected in parallel with each other. Thus, the higher the capacitance value of node N1. Or if the number of on switches among the plurality of switches SWU is smaller, the number of capacitors CU that can be connected in parallel with each other is smaller. Thus, the lower the capacitance value of node N1.
The above arrangement and the number of components (e.g., switch SWU and capacitor CU) of the switched capacitor array circuit 210 are only examples, and the disclosure is not limited thereto. The number of components in the switched capacitor array circuit 210 may be one or more according to practical requirements.
The current source circuit 215 provides a current signal S I. The switch SW1 is coupled between the current source 215 and the node N1, and is turned on according to the enable signal S EN to transmit the current signal S I to the node N1, so as to charge the node N1 to generate the signal S 1. If the capacitance of the node N1 is higher, the charging time is longer, so the change speed of the signal S 1 is slower. Or if the capacitance of the node N1 is lower, the charging time is shorter, so the change speed of the signal S 1 is faster.
The switch SW2 is selectively turned on according to the driving signal S D to reset the potential of the node N1. In this example, the switch SW2 may be implemented by an N-type transistor. The comparator circuit 220 compares the reference voltage S REF1 with the signal S 1 to generate a signal S 3. The inverter circuit 230 generates a signal S 2 according to the signal S 3.
The PFM controller circuitry 130 also includes a comparator circuit 240, an SR latch (latch) circuit 250, and an inverter circuit 260. The comparator circuit 240 compares the output voltage S O with the reference voltage S REF2 to generate a set signal S SET. The SR latch circuit 250 generates the enable signal S EN according to the set signal S SET and the signal S 2. In this example, the SR latch circuit 250 may include a NOR gate (NOR) circuit G1 and a NOR gate G2. The inverter circuit 260 generates the driving signal S D according to the enable signal S EN.
Fig. 2B is a schematic diagram illustrating PFM controller circuitry 130 of fig. 1, according to some embodiments of the present disclosure. In this example, the SR latch circuit 250 includes a NAND gate (NAND) circuit G3, a NAND gate circuit G4, and an inverter circuit 252, as compared to fig. 2A. In other words, in some embodiments, the SR latch circuit 250 may be implemented by a NOR circuit (i.e., fig. 2A). Alternatively, in some embodiments, the SR latch circuit 250 may also be implemented by a NAND circuit (i.e., FIG. 2B).
Fig. 3 is a waveform diagram illustrating a plurality of signals of fig. 2A (or fig. 2B) according to some embodiments of the present disclosure. For easy understanding of the operation of the power supply device 100 of fig. 1, please refer to fig. 1, fig. 2A (or fig. 2B) and fig. 3. In the period T1, the driving signal S D has a logic value of 1 (i.e., the level of the driving signal S D is high), and the enabling signal S EN has a logic value of 0 (i.e., the level of the enabling signal S EN is low). In response to this drive signal S D, switch TP is turned off and switch TN is turned on. In this way, the capacitor C is discharged via the switch TN, so that the output voltage S O decreases.
At time t 0, when the output voltage S O is lower than (or equal to) the reference voltage S REF2, the comparator circuit 240 outputs the setting signal S SET having a logic value of 1. In response to this set signal S SET and the signal S 2 having a logic value of 0, the SR latch circuit 250 outputs the enable signal S EN having a logic value of 1. In this way, the inverter circuit 260 outputs the driving signal S D having a logic value of 0. In response to this drive signal S D, switch TP is on and switch TN is off. Under this condition, the capacitor C is charged via the switch TP, so that the output voltage S O rises. When the output voltage S O is higher than the reference voltage S REF2, the comparator circuit 240 outputs a setting signal S SET having a logic value of 0. In addition, in response to the enable signal S EN having a logic value of 1, the switch SW1 is turned on, so that the node N1 is charged by the current signal S I. Thus, the level of the signal S 1 starts to rise.
At time t1, when the signal S 1 is higher than (or equal to) the reference voltage S REF1, the comparator circuit 220 outputs a signal S 3 having a logic value of 0. In response to the signal S 3 and the set signal S SET having a logic value of 0, the inverter circuit 230 outputs a signal S 2 having a logic value of 1. In response to this signal S 2 and the logic value set signal S SET, the SR latch circuit 250 outputs an enable signal S EN having a logic value of 0. In this way, the inverter circuit 260 outputs the driving signal S D having a logic value of 1. In response to this drive signal S D, switch TP is turned off and switch TN is turned on. Accordingly, the capacitor C is discharged through the switch TN, so that the output voltage S O is reduced. By analogy, based on the control of the PFM controller circuitry 130, the power conversion circuit 110 may regulate the output voltage S O according to the driving signal S D.
Through the above operation, the capacitance value of the node N1 can be changed to adjust the constant on-time (constant on-time) T COT of the driving signal S D. For example, if the capacitance of the node N1 becomes smaller, the change speed of the signal S 1 becomes faster. Under this condition, the signal S1 is higher (or equal) to the reference voltage S REF1 at time t 2, which is earlier than time t 1. Accordingly, the inverter circuit 230 outputs the signal S 2 having the logic value 1 at time t 2, thereby causing the inverter circuit 260 to output the driving signal S D having the logic value 1 more quickly. Or if the capacitance of the node N1 becomes larger, the change speed of the signal S 1 becomes slower. Under the conditions of this, the temperature of the liquid, Signal S 1 may be higher than (or equal to) reference voltage S REF1 at time t 3, which is later than time t 1. Accordingly, the inverter circuit 230 outputs the signal S 2 having the logic value 1 at time t 3, thereby causing the inverter circuit 260 to output the driving signal S D having the logic value 1 more slowly.
Fig. 4 is a flowchart illustrating operation of the cycle controller circuitry 120 of fig. 1 according to some embodiments of the present disclosure. As described above, the period controller circuitry 120 may detect the frequency of the driving signal S D according to the clock signal S CLK to adjust the at least one control bit BI. In some embodiments, as previously shown in FIG. 1, the cycle controller circuitry 120 includes a counter circuit 122 and a control logic circuit 124. The counter circuit 122 is reset according to the clock signal S CLK to count the number of pulses of the driving signal S D to generate a count value S CO. In some embodiments, the counter circuit 122 may be an up counter. The control logic 124 performs the operations of fig. 4 according to the count value S CO to adjust the at least one control bit BI. In some embodiments, control logic 124 may be implemented by one or more digital circuits configured to be implemented with a state machine that performs the operations of fig. 4. The above arrangement of the period controller circuit system 120 is used for example, and the disclosure is not limited thereto.
In operation S410, at least one control bit BI is set to a preset value. For example, the control logic 124 may include a register (not shown) storing a predetermined value of at least one control bit BI. In this operation, the control logic 124 outputs at least one control bit BI having a predetermined value through the register. Taking FIG. 2A as an example, the preset value of the control bits B0-B3 may be "0111". In response to this preset value, 3 capacitors CU in the switched capacitor array circuit 210 may be connected in parallel with each other.
In operation S420, it is determined whether the count value S CO is 0 in one period of the clock signal S CLK. If the count value S CO is 0, at least one control bit BI is adjusted to increase the rate of change of the signal S 1. If the count value S CO is not 0, at least one control bit BI is maintained as a predetermined value.
For easy understanding, please refer to fig. 5A, fig. 5A is a schematic waveform diagram illustrating a part of the signals in fig. 1 according to some embodiments of the present disclosure. In fig. 5A, the preset frequency F CLK of the clock signal S CLK is set to 32kHZ, the period of the clock signal S CLK is set to 1/F CLK, and the current IL is the current flowing through the inductor L.
In the 1 st period P1, the counter circuit 122 is triggered to count the pulse number of the driving signal S D, and the plurality of control bits B [0] to B [3] are set to a predetermined value (i.e. operation S410). If at least one pulse of the driving signal S D occurs in the 1 st period P1 (i.e., the count value S CO is at least 1). In this case, the frequency of the representative driving signal S D is higher than the frequency F CLK, so that it does not fall into the human ear hearing range. Accordingly, the control logic 124 maintains the control bits B0-B3 as a predetermined value.
Or if the pulse of the driving signal S D does not occur in the 1 st period P1 (i.e., the count value S CO is 0). In this case, the frequency of the representative drive signal S D is lower than the frequency F CLK and may fall within the human ear hearing frequency range. Accordingly, the control logic 124 adjusts the control bits B [0] B [3] (e.g., switches the control bits B [0] B [3] to "0000") so that the switched capacitor array circuit 210 provides a lower capacitance value to increase the variation speed of the signal S 1. In this way, the frequency of the driving signal S D can be increased to avoid falling into the auditory range of the human ear.
With continued reference to fig. 4, in operation S430, it is determined whether the count value S CO is greater than or equal to a preset value in the next period of the clock signal S CLK. If the count value S CO is greater than or equal to the preset value, at least one control bit BI is adjusted to reduce the change speed of the signal S 1. If the count value S CO is smaller than the preset value, the value of at least one control bit BI is maintained.
Referring to fig. 5A, if the number of pulses of the driving signal S D is smaller than the predetermined value (e.g., 16/32/48/62, etc.) in the 2 nd period P2, it represents that the power conversion circuit 110 is operated under light load. Accordingly, the control logic 124 maintains the values of the control bits B0-B3.
Or if the number of pulses of the driving signal S D is greater than or equal to the predetermined value in the 2 nd period P2, it indicates that the power conversion circuit 110 is operating under heavy load. Accordingly, the control logic 124 adjusts the plurality of control bits B [0] B [3] in the next cycle (i.e., the 3 rd cycle P3) (e.g., switches the plurality of control bits B [0] B [3] to a predetermined value). Thus, the switched capacitor array circuit 210 can provide a higher capacitance value to reduce the variation speed of the signal S1. By the above arrangement, the frequency of the driving signal S D can be prevented from being too high, so as to maintain the load current capability of the power conversion circuit 110 under heavy load.
In some embodiments, if the number of pulses of the driving signal S D is still greater than the predetermined value in the next period, it means that the power conversion circuit 110 is still operating under heavy load. Accordingly, the control logic 124 may further adjust the plurality of control bits B [0] B [3] (e.g., switch the plurality of control bits B [0] B [3] to "1111"). Thus, the switched capacitor array circuit 210 can provide a higher capacitance value to reduce the variation speed of the signal S 1. As shown in fig. 4, the above operations S420 to S430 can be understood as 3 states ST1 to ST3. In state ST1, the control bits B0-B3 have a predetermined value "0111", which corresponds to the second highest capacitance. In state ST2, the values of the control bits B0-B3 are "000", which corresponds to the lowest capacitance value. In the state ST3, the values of the control bits B0-B3 are 1111. According to the load condition and the aural frequency range, the control logic 124 can sequentially adjust the control bits B0-B3 with reference to the 3 states.
The above state numbers are only examples, and the present invention is not limited thereto. The number of states, the predetermined value, and/or the number of components of the switched capacitor array circuit 210 can be adjusted accordingly according to the actual design requirements. For example, in some embodiments, the switched capacitor array circuit 210 may include a plurality of smaller capacitors (not shown) for trimming the capacitance value provided by the switched capacitor array circuit 210 according to additional bits in the at least one control bit BI.
Fig. 5B is a waveform diagram illustrating a portion of the signals of fig. 1 according to some embodiments of the present disclosure. In comparison with FIG. 5A, in this example, if the number of pulses of the driving signal S D is greater than or equal to the predetermined value in the 2 nd period P2, the control logic circuit 124 immediately adjusts the plurality of control bits B [0] to B [3] (e.g., switches the plurality of control bits B [0] to B [3] to the predetermined value) in the current period. In this way, a large current can be provided in real time in response to the need for a high load.
Fig. 6 is a flow chart illustrating a PFM method 600 according to some embodiments of the present disclosure. In operation S610, the change speed of the signal S 1 is adjusted according to the at least one control bit BI, and the signal S 1 is compared with the reference voltage S REF1 to generate a signal S 2. In operation S620, a driving signal S D is generated to the power conversion circuit 110 according to the output voltage S O, the reference voltage S REF2 and the signal S 2. In operation S630, the frequency of the driving signal S D is detected according to the clock signal S CLK having the preset frequency F CLK to adjust the at least one control bit BI, wherein the preset frequency F CLK is set based on the human ear hearing frequency range.
The above description of the operations may refer to the above embodiments, and thus will not be repeated herein. The various operations of PFM method 600 described above are merely examples and are not limited to being performed in the order illustrated in this example. The various operations under PFM method 600 should be added, replaced, omitted, or performed in a different order as appropriate without departing from the manner and scope of operation of the various embodiments of the present disclosure. Or one or more operations under PFM method 600 may be performed concurrently or with partial concurrence.
In summary, the power supply device and the PFM method in some embodiments of the present disclosure can prevent the switching frequency from falling into the auditory range of the human ear, thereby improving the auditory feeling of the user.
Although the embodiments of the present disclosure have been described in detail, these embodiments are not intended to be limiting, and a person of ordinary skill in the art may make various changes to the technical features of the disclosure according to the disclosure or the disclosure, and all such changes may fall within the scope of protection sought herein, in other words, the scope of protection of the present disclosure shall be defined by the claims of the present disclosure.
Reference numerals illustrate:
100: power supply device
110: Power supply conversion circuit
111. 112: Buffer device
120: Periodic controller circuitry
122: Counter circuit
124: Control logic circuit
130: Pulse Frequency Modulation (PFM) controller circuitry
BI: at least one control bit
C: capacitance device
L: inductance
S CLK: clock pulse signal
S CO: count value
S D: drive signal
S O: output voltage
S REF1、SREF2: reference voltage
TN, TP: transistor with a high-voltage power supply
V CC: voltage (V)
210: Switched capacitor array circuit
215: Current source circuit
220. 240: Comparator circuit
230. 260: Inverter circuit
250: SR latch circuit
B0, B1, B2, B3: at least one control bit
CU: capacitance device
G1, G2: NOR gate circuit
N1: node
S 1、S2、S3: signal signal
S EN: enable signal
S I: current signal
S SET: setting signal
SW1, SW2, SWU: switch
252: Inverter circuit
G3, G4: NAND gate circuit
T1: time period
T 0、t1、t2、t3: time of
TCOT: constant on time
S410, S420, S430: operation of
ST1, ST2, ST3: status of
F CLK: preset frequency
P1, P2, P3: cycle time
IL: electric current
600: PFM method
S610, S620, S630: operation of
Claims (9)
1. A power supply device, comprising:
the pulse frequency modulation controller circuit system is used for adjusting the change speed of a first signal according to at least one control bit, comparing the first signal with a first reference voltage to generate a second signal, and generating a driving signal to the power supply conversion circuit according to an output voltage, the second reference voltage and the second signal, wherein the power supply conversion circuit is used for generating the output voltage according to the driving signal; and
Period controller circuitry to detect a frequency of the drive signal based on a clock signal having a preset frequency, wherein the preset frequency is set based on a human ear hearing frequency range,
Wherein the pulse frequency modulation controller circuitry comprises:
A switched capacitor array circuit for determining the capacitance of the node according to the at least one control bit,
A first switch for outputting a current signal to charge the node according to the conduction of the enable signal to generate the first signal,
A second switch selectively turned on according to the driving signal to reset the potential of the node,
A comparator circuit for comparing the first reference voltage with the first signal to generate a third signal, an
And the inverter circuit is used for generating the second signal according to the third signal.
2. The power supply of claim 1, wherein the period controller circuitry is to adjust the at least one control bit to avoid the frequency of the drive signal falling within the human ear hearing frequency range.
3. The power supply of claim 1, wherein the switched capacitor array circuit comprises:
at least one capacitor; and
At least one third switch coupled between the at least one capacitor and the node, wherein each of the at least one third switch is configured to conduct according to a corresponding control bit of the at least one control bit.
4. The power supply of claim 1, wherein the pulse frequency modulation controller circuitry comprises:
A comparator circuit for comparing the output voltage with the second reference voltage to generate a set signal;
An SR latch circuit for generating an enable signal according to the setting signal and the second signal; and
And the inverter circuit is used for generating the driving signal according to the enabling signal.
5. The power supply of claim 1, wherein the period controller circuitry is configured to count the number of pulses of the drive signal during a period of the clock signal to generate a count value, and to adjust the at least one control bit based on the count value.
6. The power supply of claim 5, wherein if the count value is 0, the period controller circuitry is configured to adjust the at least one control bit to increase the rate of change of the first signal.
7. The power supply device of claim 5, wherein the period controller circuitry is configured to adjust the at least one control bit to reduce the rate of change of the first signal during the period or a next period of the clock signal if the count value is greater than or equal to a predetermined value.
8. The power supply device of claim 1, wherein the preset frequency is higher than a highest frequency in the human ear hearing frequency range.
9. A pulse frequency modulation method performed by the power supply apparatus according to claim 1, and comprising:
Adjusting the change speed of the first signal according to at least one control bit, and comparing the first signal with a first reference voltage to generate a second signal;
generating a driving signal to a power conversion circuit according to an output voltage, a second reference voltage and the second signal, wherein the power conversion circuit is used for generating the output voltage according to the driving signal; and
Detecting a frequency of the driving signal according to a clock pulse signal having a preset frequency to adjust the at least one control bit, wherein the preset frequency is set based on a human ear hearing frequency range.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771404A (en) * | 2010-01-08 | 2010-07-07 | 北京巨数数字技术开发有限公司 | LED control chip |
| CN102104331A (en) * | 2010-12-29 | 2011-06-22 | 复旦大学 | Frequency compensating circuit suitable for switched-capacitor direct-current voltage converter |
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| CN100403206C (en) * | 2003-11-26 | 2008-07-16 | 圆创科技股份有限公司 | Pulse frequency modulation type voltage regulator capable of extending minimum OFF time |
| CN100399689C (en) * | 2004-04-27 | 2008-07-02 | 株式会社理光 | Switching regulator and method for changing output voltages thereof |
| CN100397766C (en) * | 2004-12-01 | 2008-06-25 | 崇贸科技股份有限公司 | Switching type control device |
| DE102005038231B3 (en) * | 2005-08-12 | 2007-04-12 | Infineon Technologies Ag | Method and device for switching on a voltage supply of a semiconductor circuit and corresponding semiconductor circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101771404A (en) * | 2010-01-08 | 2010-07-07 | 北京巨数数字技术开发有限公司 | LED control chip |
| CN102104331A (en) * | 2010-12-29 | 2011-06-22 | 复旦大学 | Frequency compensating circuit suitable for switched-capacitor direct-current voltage converter |
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