CN113434198B

CN113434198B - RISC-V instruction processing method, storage medium and electronic device

Info

Publication number: CN113434198B
Application number: CN202110712238.7A
Authority: CN
Inventors: 何凯帆; 张仕兵
Original assignee: Shenzhen Zhongke Lanxun Technology Co ltd
Current assignee: Shenzhen Zhongke Lanxun Technology Co ltd
Priority date: 2021-06-25
Filing date: 2021-06-25
Publication date: 2023-07-14
Anticipated expiration: 2041-06-25
Also published as: CN113434198A

Abstract

The invention relates to the technical field of RISC-V register architecture, and discloses a RISC-V instruction processing method, a storage medium and electronic equipment. The method comprises the following steps: acquiring a specified RISC-V instruction, wherein the specified RISC-V instruction comprises an operation code field and a register field, the register field is used for storing non-addressing codes but not storing addressing codes, the non-addressing codes point to corresponding non-addressing registers, and the addressing codes point to corresponding addressing registers; the non-addressed registers are operated according to the operation code of the opcode field. Because the addressing code of the addressing register does not participate in the coding of the specified RISC-V instruction, the present embodiment can save the number of bits used to express the addressing code, i.e., vacate more instruction coding space, and the saved number of bits is beneficial to express more specified RISC-V instructions, thereby improving the code density.

Description

RISC-V instruction processing method, storage medium and electronic device

Technical Field

The invention relates to the technical field of RISC-V register architecture, in particular to a RISC-V instruction processing method, a storage medium and electronic equipment.

Background

The RISC-V architecture inherits a simple design philosophy, and the RISC-V basic instruction set is only 40 or more, and together with other modularized extension instructions, a total of tens of instructions, the RISC-V instruction set can be used by enterprises without paying authorization fees.

In the RISC-V architecture, the registers of the processor fall into two main categories: the first type is a general purpose register, which is used to participate in various computing operations. The second type is an addressing register, which is used to participate in addressing. In general, the addressing register is used only in connection with addressing, and no addressing register is required to specify RISC-V instructions.

However, the prior art encodes addressing registers with general purpose registers mixed participation when encoding a specified RISC-V instruction. Because the addressing registers occupy a corresponding number of instruction bits when participating in encoding of the specified RISC-V instruction, no more RISC-V instructions can be expressed, thereby wasting instruction encoding space.

Disclosure of Invention

An object of an embodiment of the present invention is to provide a RISC-V instruction processing method, a storage medium, and an electronic device, which are used to solve the technical drawbacks of the prior art.

In a first aspect, an embodiment of the present invention provides a RISC-V instruction processing method, including:

acquiring a specified RISC-V instruction, wherein the specified RISC-V instruction comprises an operation code field and a register field, the register field is used for storing non-addressing codes but not storing addressing codes, the non-addressing codes point to corresponding non-addressing registers, and the addressing codes point to corresponding addressing registers;

and operating the non-addressing registers according to the operation codes of the operation code field.

Optionally, the non-addressed registers are general purpose registers in the RISC-V standard protocol.

Optionally, the addressing registers include a global pointer register, a thread pointer register, a stack pointer register, and a program register.

Alternatively, the number of bits of the register field is n bits, and n times 2 of the non-addressing codes may be expressed.

Alternatively, the number of bits of the opcode field is m bits, and the operation codes to the power of 2 m can be expressed.

Optionally, if the specified RISC-V instruction is an R-type instruction, the specified RISC-V instruction further includes a function field, where the number of bits of the function field is R bits, r=q-3*n-m, and Q is the number of bits of the specified RISC-V instruction.

Optionally, if the specified RISC-V instruction is an I-type instruction, the specified RISC-V instruction further includes a function field and an immediate field, a total bit number of the function field and the immediate field is I bits, i=q-2*n-m, and Q is a bit number of the specified RISC-V instruction.

Optionally, if the specified RISC-V instruction is an S-type instruction, the specified RISC-V instruction further includes a function field and an immediate field, a total bit number of the function field and the immediate field is S bits, s=q-2*n-m, and Q is a bit number of the specified RISC-V instruction.

Optionally, if the specified RISC-V instruction is a U-type instruction, the specified RISC-V instruction further includes an immediate field, a total number of bits of the immediate field is U bits, u=q-n-m, and Q is a number of bits of the specified RISC-V instruction.

Optionally, n is 4.

In a second aspect, an embodiment of the present invention provides a storage medium storing computer-executable instructions for causing an electronic device to perform the above-described RISC-V instruction processing method.

In a third aspect, an embodiment of the present invention provides an electronic device, including:

at least one processor; the method comprises the steps of,

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the RISC-V instruction processing method described above.

In the RISC-V instruction processing method provided by the embodiment of the invention, the appointed RISC-V instruction is obtained, the appointed RISC-V instruction comprises an operation code field and a register field, the register field is used for storing non-addressing codes but not storing addressing codes, the non-addressing codes point to corresponding non-addressing registers, the addressing codes point to corresponding addressing registers, and the non-addressing registers are operated according to the operation codes of the operation code field. Because the addressing code of the addressing register does not participate in the coding of the specified RISC-V instruction, the method can save the bit number used for expressing the addressing code, namely vacates more instruction coding space, and the saved bit number is beneficial to expressing more specified RISC-V instructions, thereby improving the code density.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.

FIG. 1 is a schematic representation of a prior art RISC-V register;

FIG. 2 is a schematic diagram illustrating the use of a conventional RISC-V register;

FIG. 3 is a schematic diagram of an instruction format of a conventional RISC-V;

FIG. 4 is a flow chart of a RISC-V instruction processing method according to an embodiment of the present invention;

FIG. 5 is a schematic representation of the RISC-V register provided by an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating the use of RISC-V registers according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of an instruction format of RISC-V according to an embodiment of the present invention;

fig. 8 is a schematic circuit diagram of an electronic device according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be noted that, if not in conflict, the features of the embodiments of the present invention may be combined with each other, which is within the protection scope of the present invention. In addition, while functional block division is performed in a device diagram and logical order is shown in a flowchart, in some cases, the steps shown or described may be performed in a different order than the block division in the device, or in the flowchart. Furthermore, the words "first," "second," "third," and the like as used herein do not limit the order of data and execution, but merely distinguish between identical or similar items that have substantially the same function and effect.

The RISC-V instruction set architecture is a new generation open source instruction set architecture, and is a latest, simple, clear and open source instruction set architecture. The goal of the RISC-V instruction set architecture is to allow it to work efficiently on all computer devices, from the smallest to the fastest.

Referring to fig. 1 and 2 together, the risc-V instruction set architecture includes 32 integer registers and 1 program register, each of the integer registers is named x0 to x31, where x1 to x31 are all general purpose registers, i.e., the number of general purpose registers is 31, and the general purpose registers store integer values. Register x0 is a constant 0 of the hardware wiring. The RISC-V instruction set architecture also includes 32 floating point registers, named f 0-f 31, that can be used for floating point expansion purposes.

The number of bits of the general purpose registers or floating point registers in the RISC-V instruction set architecture may be 32 bits or 64 bits, xlen=32 when the number of bits is 32 bits. Xlen=64 when the number of bits is 64 bits.

In the present embodiment, the stack pointer register x2, the global pointer register x3, the thread pointer register x4, and the program register pc shown in fig. 1 are taken as addressing registers, and then a specified number of general-purpose registers, for example, 16 specified number, are selected as non-addressing registers from among the 31 general-purpose registers shown in fig. 1.

In the RISC-V instruction set architecture, each register corresponds to a register code that is used to address the corresponding register. Since the relevant RISC-V instructions are all operated on registers, the register encoding of the registers needs to be involved in the encoding operation of the relevant RISC-V instructions in order to address the corresponding registers, and thus the RISC-V instruction format as shown in FIG. 3 is:

as shown in fig. 3, the RISC-V instruction includes an R-type instruction, an I-type instruction, an S-type instruction, and a U-type instruction, the R-type instruction being used for register and register operations, the I-type instruction being used for short immediate and memory load operations, the S-type instruction being used for memory store operations, the U-type instruction being used for long immediate operations.

In this embodiment, the addressing encoding of the addressing registers set forth above only takes part in the encoding of the addressing instructions or the encoding operations of the addition, subtraction, multiplication, shift, etc. instructions that are set up for addressing convenience.

For example, assume "DD" encodes the destination register, "BB" encodes the first source register, "SS" encodes the second source register, and "AA" and "CC" both encode the addressing register.

For add instructions add rD, rB, rS, the corresponding instruction code is: 1010 1000SSSS BBBBBB-DDDD 1111 0000 0111, in this addition instruction, the non-addressing encoding of the non-addressing registers takes part in the encoding operation.

For another example, the add instruction is add rD, rA, rS, and its corresponding instruction code is: 1010 1000SSSS 00aa-DDDD 1111 0100 0111, in this addition instruction, both the unaddressed encoding of unaddressed registers and the addressed encoding of addressed registers participate in the encoding operation.

As previously described, the non-addressing encoding of the non-addressing registers and the addressing encoding of the addressing registers may be intermixed in the encoding operations of the designated RISC-V instruction. Referring to fig. 3, fig. 3 illustrates an R-type instruction, an I-type instruction, an S-type instruction, and a U-type instruction, which are obtained by mixing non-addressing encoding and addressing encoding to participate in encoding operations of a specified RISC-V instruction in the prior art.

As shown in FIG. 3 for R-type instructions, the opcode field (opcode) has 7 bits (0-6), the destination register field (rd) has 5 bits (7-11), the first function field (function 3) has 3 bits (12-14), the first source register field (rs 1) has 5 bits (15-19), the second source register field (rs 2) has 5 bits (20-24), and the second function field (function 7) has 7 bits (25-31).

Since the R-type instruction of the related art involves the encoding operations of all of the 32 registers (31 general purpose registers and 1 program register) into the encoding operations of the target register field or the first source register field or the second source register field, each of the three register fields requires 5 bits to express the 32 register encodings, where 32=2 to the power 5.

Similarly, as shown in FIG. 3 for the type I instruction, the opcode field (opcode) has 7 bits (0-6), the destination register field (rd) has 5 bits (7-11), the first function field (funct 3) has 3 bits (12-14), the first source register field (rs 1) has 5 bits (15-19), and the immediate field (imm [11:0 ]) has 12 bits (20-31).

Similarly, prior art type I instructions also require that the encoding of the 32 registers be involved in the encoding operation of either the destination register field or the first source register field, thus requiring 5 bits for each of the two register fields.

Similarly, as shown in FIG. 3 for the S-type instruction, the opcode field (opcode) has 7 bits (0-6), the first immediate field (imm [4:0 ]) has 5 bits (7-11), the first function field (function 3) has 3 bits (12-14), the first source register field (rs 1) has 5 bits (15-19), the second source register field (rs 2) has 5 bits (20-24), and the second function field (function 7) has 7 bits (21-24). The second immediate field (imm [11:5 ]) has a number of bits of 7 bits (25-31).

Similarly, the prior art S-type instruction also requires that the 32 register codes all participate in the encoding operation of the destination register field or the first source register field, and therefore, each of the three register fields requires 5 bits to express the 32 register codes.

Similarly, as shown in FIG. 3 for U-type instructions, the opcode field (opcode) has 7 bits (0-6), the destination register field (rd) has 5 bits (7-11), and the immediate field (imm [31:12 ]) has 20 bits (12-31).

Similarly, the prior art U-type instruction also requires that the register encodings of 32 registers all participate in the encoding operation of the destination register field, and therefore the destination register field requires 5 bits to express the 32 register encodings.

However, in practice, for the specified RISC-V instruction, the addressing code of the addressing register does not participate in the encoding operation of the specified RISC-V instruction, but the prior art reserves the corresponding bit number for the addressing code of the addressing register, but cannot express more functional instructions.

In this embodiment, the addressing registers are not involved in encoding operations that specify RISC-V instructions, including logic operation instructions, DSP operation instructions, complex multiplication operation instructions, cyclic shift operation instructions, crs instructions, beq/bne instructions, jal instructions, and the like. The above-described specified RISC-V instruction does not require the address encoding of the address register to participate in the encoding operation.

For or logic instructions or rd, rs1, rs2, the corresponding instruction codes are: 0000 0000SSSS BBBB-DDDD 1111 0110 0011, in this or logic instruction, the non-addressing encoding of all non-addressing registers takes part in the encoding operation.

For another example, and logic instructions are and rd, rs1, rs2, whose corresponding instructions are encoded as: 0000 0000SSSS BBBB-DDDD 1101 0110 0011, in this or logic instruction, the non-addressing encoding of all non-addressing registers takes part in the encoding operation.

In general, for a given RISC-V instruction, the non-addressing encoding and addressing encoding mix to participate in the encoding operation of the given RISC-V instruction, but the given RISC-V instruction uses non-addressing encoding, wasting instruction encoding space.

Based on this, the embodiment of the invention provides a RISC-V instruction processing method. Referring to fig. 4, the risc-V instruction processing method S400 includes:

s41, acquiring a specified RISC-V instruction, wherein the specified RISC-V instruction comprises an operation code field and a register field, and the register field is used for storing non-addressing codes but not storing addressing codes, the non-addressing codes point to corresponding non-addressing registers, and the addressing codes point to corresponding addressing registers;

in this embodiment, the specified RISC-V instruction is an instruction that participates in the encoding operation without addressing encoding, and the specified RISC-V instruction includes, but is not limited to, the following RISC-V instructions: logic operation instructions, DSP operation instructions, complex multiplication operation instructions, cyclic shift operation instructions, crs instructions, beq/bne instructions, jal instructions.

The opcode field is used to store an opcode that defines the type or nature of operation that the RISC-V instruction needs to perform, and the opcode can be customized by the user as desired. Wherein the number of bits of the opcode field is configurable by the user.

As previously described, the register field is used to store non-addressing code but not addressing code, i.e., the addressing code does not participate in the encoding operation of the designated RISC-V instruction, which does not require the corresponding number of bits to be additionally set to store overflowed addressing code as in the prior art, such that the corresponding number of bits is vacated to express more designated RISC-V instructions.

The non-addressing encoding is a register encoding of a non-addressing register, the addressing encoding is a register encoding of an addressing register, the non-addressing register is a register that participates in an encoding operation that specifies a RISC-V instruction, the addressing register is a register that does not participate in an encoding operation that specifies a RISC-V instruction, e.g., the non-addressing encoding is a "DD" that points to a "save register," the addressing encoding is an "AA" that points to a "global pointer register.

S42, according to the operation code of the operation code field, the non-addressing register is operated.

In an embodiment, operating the non-addressed registers includes any suitable operation of storing operands of the non-addressed registers, reading operands of the non-addressed registers, calculating operands of the non-addressed registers, and the like.

Because the addressing code of the addressing register does not participate in the coding of the specified RISC-V instruction, the present embodiment can save the number of bits used to express the addressing code, i.e., vacate more instruction coding space, and the saved number of bits is beneficial to express more specified RISC-V instructions, thereby improving the code density.

In an embodiment, the non-addressed registers are general purpose registers in the RISC-V standard protocol, please refer to FIG. 5 together with FIG. 6, wherein a specified number of general purpose registers, for example 16, are selected from 32 general purpose registers in the RISC-V standard protocol as the non-addressed registers, and the non-addressed registers include a register x0 (hardware zero register), a register ra, a register a0-3, a register t0-1, and a register s0-7.

It follows that 16 general purpose registers are selected from 32 general purpose registers in the RISC-V standard protocol, and all the 16 general purpose registers can participate in encoding operations of various specified RISC-V instructions, so that, compared with the prior art, in encoding operations of specified RISC-V instructions, register encoding capable of expressing general purpose registers involved in all specified RISC-V instructions is not required to reserve corresponding bits, that is, compared with the prior art, non-addressing encoding involved in all specified RISC-V instructions is also expressed using a small number of bits.

In this embodiment, the addressing registers include a register gp (global pointer register), a register tp (thread pointer register), a register sp (stack pointer register) and a register pc (program register), and since the encoding operation for specifying the RISC-V instruction does not need to be applied to each of the addressing registers, the four registers may be individually fetched from among the 32 general-purpose registers in the RISC-V standard protocol and the four registers may be specified to be encoded without participating in the encoding operation for specifying the RISC-V instruction, but in the encoding operation for other RISC-V instructions, the four registers may be encoded with participating in the encoding operation for the addition instruction, for example, as described above.

In this embodiment, the number of bits in the register field is n, which can express n times of non-addressing codes of 2, i.e. n times of non-addressing registers of 2, as shown in fig. 6, n is 4, i.e. the number of bits in the register field can express 16 non-addressing registers in total.

As described above, referring to fig. 3, in order to express the RISC-V instruction, since the number of bits of the register field needs 32 general-purpose registers (including 4 registers of global pointer register, thread pointer register, stack pointer register and program register), each register field needs to be set with 5 bits to express the register codes of 32 general-purpose registers, but as described above, the encoding operation of the specified RISC-V instruction does not need the register codes of 4 registers of global pointer register, thread pointer register, stack pointer register and program register to participate, and the corresponding instruction function can be normally embodied.

In this embodiment, as shown in fig. 7, since only any one or more than two non-addressed registers of 16 non-addressed registers are required for specifying the expression of the RISC-V instruction, that is, only 4 bits are required for setting each register field of the RISC-V instruction, the register code of any one of the 16 non-addressed registers can be expressed.

Since the number of bits per RISC-V instruction is of fixed equal length, for example, the number of bits per RISC-V instruction is 32 or 64. As shown in FIG. 7, the number of bits specifying the RISC-V instruction is 32 bits. For a fixed-length RISC-V instruction, compared with the prior art, the embodiment can save 1 unit number in each register field, and when each RISC-V instruction needs to use e register fields according to the RISC-V standard protocol, the embodiment can save e unit numbers. The present embodiment may then use e-digits in combination with an opcode field or a function field to express a specified RISC-V instruction for more instruction functions.

For example, the R-type instruction requires 3 register fields, and this embodiment can save 3 digits. As shown in FIG. 7, the operation code field (opcode) has 8 bits (0-7), the first function field (function 4) has 4 bits (8-11), the destination register field (rd) has 4 bits (12-15), the first source register field (rs 1) has 4 bits (16-19), the second source register field (rs 2) has 4 bits (20-23), and the second function field (function 8) has 8 bits (24-31).

Therefore, as the target register field (rd), the first source register field (rs 1) and the second source register field (rs 2) can express the non-addressing codes of 16 non-addressing registers only by 4 bits, compared with the prior art, 3 digits are saved, and the 3 digits can be divided by the operation code field, the first function field and the second function field, because the instruction function of a specified RISC-V instruction can be determined by the operation code of the operation code field and/or the function code of the function field, and the digits of the expressible operation code and/or the function code are increased, the method provided by the embodiment can express more functional instructions.

For another example, if the type I instruction requires 2 register fields, the present embodiment can save 2 digits. As shown in FIG. 7, the opcode field (opcode) has 8 bits (0-7), the first function field (function 4) has 4 bits (8-11), the destination register field (rd) has 4 bits (12-15), the first source register field (rs 1) has 4 bits (16-19), and the immediate field (imm [11:0 ]) has 12 bits (20-31).

Therefore, as the target register field (rd) and the first source register field (rs 1) can express the non-addressing codes of 16 non-addressing registers only by 4 bits, compared with the prior art, 2 digits are saved, and the 2 digits can be separated by the operation code field and the first function field.

For another example, the S-type instruction requires 2 register fields, and this embodiment can save 2 digits. The operation code field (opcode) has 8 bits (0-7), the first function field (function 3) has 4 bits (8-11), the first immediate field (imm [3:0 ]) has 4 bits (12-15), the first source register field (rs 1) has 4 bits (16-19), the second source register field (rs 2) has 4 bits (20-23), and the second immediate field (imm [11:4 ]) has 8 bits (24-31).

Therefore, as the second source register field (rs 2) and the first source register field (rs 1) can express the non-addressing codes of 16 non-addressing registers only by 4 bits, compared with the prior art, 2 digits are saved, and the 2 digits can be divided by an operation code field, a function field or an immediate field.

For another example, the U-type instruction requires 1 register field, and this embodiment can save 1 digit. The operation code field (opcode) has 8 bits (0-7), the first immediate field (imm [12:15 ]) has 4 bits (8-11), the destination register field (rd) has 4 bits (12-15), and the second immediate field (imm [31:16 ]) has 16 bits (16-31).

It follows that, since the destination register field (rd) only needs 4 bits to express the non-addressing codes of 16 non-addressing registers, compared with the prior art, 1 digit is saved, and the 1 digit can be divided by the operation code field.

In general, the present embodiment may save the number of bits used to express addressing codes, i.e., freeing up more instruction encoding space, and the saved number of bits is beneficial to express more designated RISC-V instructions, thereby increasing code density.

In some embodiments, the number of bits of the opcode field is m bits, which may express 2 to the power of m, as illustrated in FIG. 7, where m is 8 bits, which may express 256 opcodes. It will be appreciated that the value of m can be user-defined.

In some embodiments, if the RISC-V instruction is designated as an R-type instruction, the RISC-V instruction is designated as a function field, the number of bits of the function field is R bits, r=q-3*n-m, Q is the number of bits of the RISC-V instruction, for example, q=32, n=4, m=8, and r=12, that is, the number of bits of the function field is 12 bits, it is understood that for the R-type instruction, the function field may be customized to be split into a plurality of function fields by a user, as shown in fig. 7, the function field includes a first function field and a second function field, the number of bits of the first function field is 4, and the number of bits of the second function field is 8.

In some embodiments, if the RISC-V instruction is designated as an I-type instruction, the RISC-V instruction is designated as further including a function field and an immediate field, the total number of bits of the function field and the immediate field is I bits, i=q-2*n-m, Q is the number of bits of the RISC-V instruction, for example, q=32, n=4, m=8, i=16, i.e., the total number of bits of the function field and the immediate field is 16 bits, it is understood that for the I-type instruction, the function field and the immediate field may be user-defined cut, for example, the number of bits of the function field is 4 bits, and the immediate field is 12 bits.

In some embodiments, if the RISC-V instruction is designated as an S-type instruction, the RISC-V instruction is designated as a function field and an immediate field, the total number of bits of the function field and the immediate field is S bits, s=q-2*n-m, Q is the number of bits of the RISC-V instruction, for example, q=32, n=4, m=8, s=16, that is, the total number of bits of the function field and the immediate field is 16 bits, and it is understood that for the S-type instruction, the function field and the immediate field may be user-defined and split, for example, the number of bits of the function field is 4 bits, the first immediate field is 4 bits, and the second immediate field is 8 bits.

In some embodiments, if the RISC-V instruction is designated as a U-type instruction, the RISC-V instruction is designated as an immediate field, the total number of bits of the immediate field is U bits, u=q-n-m, Q is the number of bits of the RISC-V instruction, e.g., q=32, n=4, m=8, u=20, i.e., the total number of bits of the immediate field is 20 bits, it being understood that for an I-type instruction, the immediate field may be user-defined split, e.g., the first immediate field is 4 bits and the second immediate field is 16 bits.

It should be noted that, in the foregoing embodiments, there is not necessarily a certain sequence between the steps, and those skilled in the art will understand that, according to the description of the embodiments of the present invention, the steps may be performed in different orders in different embodiments, that is, may be performed in parallel, may be performed interchangeably, or the like.

Referring to fig. 8, fig. 8 is a schematic circuit diagram of an electronic device according to an embodiment of the present invention, where the electronic device may be any suitable type of device or electronic product, for example, the electronic device includes a single-chip microcomputer or a desktop computer. As shown in fig. 8, the electronic device 800 includes one or more processors 81 and memory 82. In fig. 8, a processor 81 is taken as an example.

The processor 81 and the memory 82 may be connected by a bus or otherwise, for example in fig. 8.

The memory 82 is used as a storage medium for storing nonvolatile software programs, nonvolatile computer-executable programs, and modules, such as program instructions/modules corresponding to the RISC-V instruction processing method in the embodiment of the present invention. The processor 81 implements the functions of the RISC-V instruction processing method provided by the above-described method embodiment by running nonvolatile software programs, instructions, and modules stored in the memory 82.

The memory 82 may include high-speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage device. In an embodiment, the memory 82 may optionally include memory remotely located relative to the processor 81, which may be connected to the processor 81 via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The program instructions/modules are stored in the memory 82 and when executed by the one or more processors 81 perform the RISC-V instruction processing method of any of the method embodiments described above.

Embodiments of the present invention also provide a storage medium storing computer-executable instructions for execution by one or more processors, such as the one processor 81 of fig. 8, to cause the one or more processors to perform the RISC-V instruction processing method of any of the method embodiments described above.

Embodiments of the present invention also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by an electronic device, cause the electronic device to perform any of the RISC-V instruction processing methods.

The above-described embodiments of the apparatus or device are merely illustrative, in which the unit modules illustrated as separate components may or may not be physically separate, and the components shown as unit modules may or may not be physical units, may be located in one place, or may be distributed over multiple network module units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the method described in the respective embodiments or some parts of the embodiments.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; the technical features of the above embodiments or in the different embodiments may also be combined within the idea of the invention, the steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A method for processing RISC-V instructions, comprising:

acquiring a specified RISC-V instruction, wherein the specified RISC-V instruction comprises an operation code field and a register field, the register field is used for storing non-addressing codes but not storing addressing codes, the non-addressing codes point to corresponding non-addressing registers, the addressing codes point to corresponding addressing registers, and the specified RISC-V instruction is an instruction which does not need addressing codes to participate in coding operation;

2. The method of claim 1, wherein the non-addressed registers are general purpose registers in a RISC-V standard protocol.

3. The method of claim 1, wherein the addressing registers comprise global pointer registers, thread pointer registers, stack pointer registers, and program registers.

4. A method according to any one of claims 1 to 3, wherein the number of bits of the register field is n bits, the n-th power of 2 of the non-addressed codes being expressible.

5. The method of claim 4, wherein the opcode field has m bits to express 2 m-th power of the opcode.

6. The method of claim 5, wherein if the specified RISC-V instruction is an R-type instruction, the specified RISC-V instruction further includes a function field, the function field having a number of R bits, R = Q-3*n-m, Q being the number of bits of the specified RISC-V instruction.

7. The method of claim 5, wherein if the specified RISC-V instruction is an I-type instruction, the specified RISC-V instruction further includes a function field and an immediate field, the total number of bits of the function field and the immediate field being I bits, I = Q-2*n-m, Q being the number of bits of the specified RISC-V instruction.

8. The method of claim 5, wherein if the specified RISC-V instruction is an S-type instruction, the specified RISC-V instruction further comprises a function field and an immediate field, the total number of bits of the function field and the immediate field being S bits, S = Q-2*n-m, Q being the number of bits of the specified RISC-V instruction.

9. The method of claim 5, wherein if the specified RISC-V instruction is a U-type instruction, the specified RISC-V instruction further includes an immediate field having a total number of bits of U bits, U = Q-n-m, Q being the number of bits of the specified RISC-V instruction.

10. The method of claim 4, wherein n is 4.

11. A storage medium storing computer-executable instructions for causing an electronic device to perform the RISC-V instruction processing method according to any one of claims 1 to 10.

12. An electronic device, comprising:

at least one processor; the method comprises the steps of,

a memory communicatively coupled to the at least one processor; wherein,,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform a RISC-V instruction processing method according to any one of claims 1 to 10.