CN113448381B - CPLD working clock keeping method, system, storage medium and device - Google Patents

Abstract

The invention provides a CPLD working clock keeping method, a CPLD working clock keeping system, a CPLD working clock keeping storage medium and CPLD working clock keeping equipment, wherein the method comprises the following steps: responding to the starting of the CPLD, generating a logic clock signal through a delay logic module preset in the CPLD, and inputting the logic clock signal to a clock monitoring module so as to enable the logic clock signal to monitor the abnormality of a native clock signal in the CPLD based on the logic clock signal; outputting a clock monitoring signal based on a monitoring result through the clock monitoring module; the clock monitoring signal is received by a multiplexer and the logic clock signal or the native clock signal is selected based on the clock monitoring signal and output as the working clock of the CPLD. The invention monitors the abnormal condition of the original clock in the CPLD, and selects the original clock or the preset delay logic module in the CPLD according to the monitoring condition of the clock monitoring module, thereby selecting a normal clock signal to ensure that the CPLD always works normally.

Description

Method, system, storage medium and equipment for keeping CPLD working clock

technical field

The invention relates to the technical field of CPLDs, in particular to a method, system, storage medium and equipment for maintaining a CPLD working clock.

Background technique

Today's servers are getting bigger and bigger, and there are more and more chips representing various functions, such as chips commonly used in servers, such as CPU, BMC chips, etc., and these chips will have their own power requirements. timing specification. The traditional method is to use hardware to design the power sequence, which will increase the area of the circuit board, because the electronic components that control the power sequence increase; at the same time, it will also cause a lot of inconvenience, for example, if you want to adjust the power supply Timing, it is necessary to modify the parts of the circuit board to adjust the power timing. The most commonly used method today is to use CPLDs to replace the power sequence on the board. Because the CPLD itself needs the matching of the clock signal, otherwise the CPLD will not work normally, such as the control sequence of the power supply, the processing of the data register, or the design of various protocol functions, so the clock signal is the core of the entire operation of the CPLD. If there is no clock signal, the CPLD will not be able to realize the function of the sequential circuit, and may not be able to effectively produce the power sequence required by each chip, resulting in the entire server system not having the correct power sequence.

Nowadays, the clock signal source of CPLD usually has an external clock circuit, which is directly connected to the CPLD for use, or uses the clock module provided by the CPLD manufacturer. For designers, they only need to open the internal time module. Generate a clock and provide its real-time clock to the sequential circuit inside the CPLD for use, but if there is a problem with the clock inside the CPLD or the clock from the external circuit is not connected to the CPLD, the CPLD will not work properly.

Contents of the invention

In view of this, the object of the present invention is to propose a kind of CPLD work clock maintenance method, system, storage medium and equipment, in order to solve the problem that CPLD internal clock occurs in the prior art or the clock that does not connect external circuit to CPLD, will Problems that prevent CPLDs from functioning properly.

Based on above-mentioned purpose, the present invention provides a kind of CPLD work clock keeping method, comprises the following steps:

In response to the CPLD being turned on, a logic clock signal is generated by a preset delay logic module in the CPLD, and the logic clock signal is input to the clock monitoring module so that it monitors the abnormality of the original clock signal in the CPLD based on the logic clock signal;

Outputting a clock monitoring signal based on the monitoring result through the clock monitoring module;

The multiplexer receives the clock monitoring signal, selects a logic clock signal or an original clock signal based on the clock monitoring signal, and outputs it as a working clock of the CPLD.

In some embodiments, inputting the logic clock signal to the clock monitoring module to make it monitor the abnormality of the native clock signal in the CPLD based on the logic clock signal includes:

input the logic clock signal to the clock monitoring module, and respectively receive the logic clock signal and the original clock signal through the low level counter and the high level counter of the clock monitoring module;

Use a low-level counter to monitor whether the original clock signal continues to be a low-level pulse signal for a preset period of time based on the logic clock signal, and use a high-level counter to monitor whether the original clock signal continues for a preset period of time based on the logic clock signal It is a high-level pulse signal.

In some embodiments, outputting the clock monitoring signal based on the monitoring result by the clock monitoring module includes:

In response to the low-level counter detecting that the original clock signal continues to be a low-level pulse signal within a preset period of time, outputting a high-level signal through the low-level counter; or

In response to the high-level counter detecting that the original clock signal continues to be a high-level pulse signal within a preset period of time, outputting a high-level signal through the high-level counter;

The high-level signal of the low-level counter or the high-level counter is output through the clock monitoring module.

In some embodiments, receiving a clock monitoring signal through a multiplexer and selecting a logic clock signal or an original clock signal based on the clock monitoring signal and outputting it as an operating clock of the CPLD includes:

The high-level signal of the clock monitoring module is received through the multiplexer, and the logic clock signal is selected based on the high-level signal and output as the working clock of the CPLD.

In some embodiments, outputting the clock monitoring signal based on the monitoring result by the clock monitoring module includes:

In response to the low-level counter detecting that the original clock signal does not continue to be a low-level pulse signal within a preset time period and the high-level counter detecting that the original clock signal does not continue to be a high-level pulse signal within a preset time period, A low-level signal is output through the clock monitoring module.

In some embodiments, receiving a clock monitoring signal through a multiplexer and selecting a logic clock signal or an original clock signal based on the clock monitoring signal and outputting it as an operating clock of the CPLD includes:

The low-level signal is received through the multiplexer, and the original clock signal is selected based on the low-level signal and output as the working clock of the CPLD.

In some embodiments, the delay logic module includes a flip-flop, an inverter, an XOR gate, and a delay buffer.

Another aspect of the present invention also provides a kind of CPLD working clock keeping system, comprising:

The original clock signal monitoring module is configured to respond to the CPLD being turned on, generate a logic clock signal through the delay logic module preset in the CPLD, and input the logic clock signal to the clock monitoring module so that it can monitor the original clock signal in the CPLD based on the logic clock signal Abnormal clock signal;

a clock monitoring signal output module configured to output a clock monitoring signal based on a monitoring result through the clock monitoring module; and

The working clock selection module is configured to receive a clock monitoring signal through a multiplexer, select a logic clock signal or an original clock signal based on the clock monitoring signal, and output it as a working clock of the CPLD.

In yet another aspect of the present invention, a computer-readable storage medium is provided, which stores computer program instructions, and implements any one of the above-mentioned methods when the computer program instructions are executed.

In yet another aspect of the present invention, a computer device is provided, including a memory and a processor, where a computer program is stored in the memory, and when the computer program is executed by the processor, any one of the above-mentioned methods is executed.

The present invention has at least the following beneficial technical effects:

The present invention can provide a clock signal for the CPLD by setting the delay logic module, so that the CPLD does not need to use the clock provided by the external circuit, which saves the external hardware and reduces the area of the circuit board; by setting the clock monitoring module, the original clock inside the CPLD can be monitored abnormal situation; by setting the multiplexer, the original clock or the preset delay logic module in the CPLD can be selected according to the monitoring situation of the clock monitoring module, so as to select a normal clock signal so that the CPLD can always work normally.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention, and those skilled in the art can obtain other embodiments according to these drawings without any creative effort.

Fig. 1 is the schematic diagram of the CPLD working clock keeping method provided according to the embodiment of the present invention;

Fig. 2 is the schematic circuit diagram of the CPLD working clock keeping method provided according to the embodiment of the present invention;

Fig. 3 is the schematic diagram of the CPLD work clock keeping system provided according to the embodiment of the present invention;

Fig. 4 is the schematic diagram of the computer-readable storage medium that realizes the CPLD work clock keeping method provided according to the embodiment of the present invention;

FIG. 5 is a schematic diagram of a hardware structure of a computer device implementing a method for maintaining a CPLD working clock according to an embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities with the same name or different parameters. It can be seen that "first" and "second" " is only for the convenience of expression, and should not be understood as limiting the embodiment of the present invention. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, of a process, method, system, product or other steps or elements inherent in a process, method, system, product, or device comprising a series of steps or elements.

Based on the above purpose, the first aspect of the embodiments of the present invention proposes an embodiment of a method for keeping a working clock of a CPLD. What Fig. 1 shows is the schematic view of the embodiment of the CPLD working clock keeping method provided by the present invention. As shown in Figure 1, the embodiment of the present invention includes the following steps:

Step S10, in response to the opening of the CPLD, generate a logic clock signal through the delay logic module preset in the CPLD, and input the logic clock signal to the clock monitoring module so that it can monitor the abnormality of the original clock signal in the CPLD based on the logic clock signal;

Step S20, outputting a clock monitoring signal based on the monitoring result through the clock monitoring module;

Step S30, receiving the clock monitoring signal through the multiplexer, selecting a logic clock signal or an original clock signal based on the clock monitoring signal, and outputting it as a working clock of the CPLD.

CPLD (Complex Programming Logic Device) represents a complex programmable logic device. By using programming technologies such as CMOS EPROM, EEPROM, flash memory and SRAM (static random access memory), it forms a high-density, high-speed and low-power programmable logic. It is a digital integrated circuit in which users can construct logic functions according to their own needs. The basic design method is to use integrated development software platform, use schematic diagrams, hardware description languages, etc. to generate corresponding target files, and download the code to Transfer to the target chip to realize the digital system of the design.

The embodiment of the present invention can provide clock signal for CPLD by arranging delay logic module, makes CPLD need not use the clock that external circuit provides, has saved external hardware, has reduced circuit board area; By arranging clock monitoring module, can monitor CPLD internal The abnormal situation of the original clock; by setting the multiplexer, the original clock or the preset delay logic module in the CPLD can be selected according to the monitoring situation of the clock monitoring module, so as to select a normal clock signal, so that the CPLD can always work normally .

In some embodiments, inputting the logic clock signal to the clock monitoring module so that it monitors the abnormality of the native clock signal in the CPLD based on the logic clock signal includes: inputting the logic clock signal to the clock monitoring module, and passing the low voltage of the clock monitoring module The level counter and the high level counter receive the logic clock signal and the original clock signal respectively; through the low level counter, based on the logic clock signal, it is monitored whether the original clock signal continues to be a low level pulse signal within a preset period of time, and through the high level counter The flat counter monitors whether the original clock signal is a high-level pulse signal continuously within a preset time period based on the logic clock signal.

In some embodiments, outputting the clock monitoring signal based on the monitoring result through the clock monitoring module includes: in response to the low level counter monitoring that the original clock signal continues to be a low level pulse signal within a preset period of time, outputting the clock monitoring signal through the low level counter High-level signal; or in response to the high-level counter monitoring that the original clock signal continues to be a high-level pulse signal within a preset period of time, the high-level signal is output through the high-level counter; the low-level signal is output through the clock monitoring module High level signal output of counter or high level counter.

In some embodiments, receiving the clock monitoring signal through the multiplexer and selecting a logic clock signal or an original clock signal based on the clock monitoring signal and outputting it as the working clock of the CPLD includes: receiving the high power of the clock monitoring module through the multiplexer level signal, select a logic clock signal based on the high level signal and output it as the working clock of the CPLD.

In some embodiments, outputting the clock monitoring signal based on the monitoring result by the clock monitoring module includes: responding to the low-level counter monitoring that the original clock signal does not continue to be a low-level pulse signal within a preset period of time and the high-level counter monitoring When the original clock signal does not continue to be a high-level pulse signal within a preset period of time, a low-level signal is output through the clock monitoring module.

In some embodiments, receiving a clock monitoring signal through a multiplexer and selecting a logic clock signal or an original clock signal based on the clock monitoring signal and outputting it as the working clock of the CPLD includes: receiving a low-level signal through a multiplexer and based on The low-level signal selects the original clock signal and outputs it as the working clock of the CPLD.

In some embodiments, the delay logic module includes a flip-flop, an inverter, an XOR gate, and a delay buffer.

FIG. 2 shows a schematic circuit diagram of a method for maintaining a working clock of a CPLD. As shown in Figure 2, the delay logic module uses flip-flops, inverters, XOR gates, and delays signals with a delay buffer. Q in the flip-flop is the output pin, which initially transitions from low level to high level, which logically means from 0 to 1, so the initial output of Q is a high level signal. When the high level signal passes through After an inverter (that is, a NOT gate), it becomes a low-level signal and is input to the D pin of the flip-flop. The signal received by the XOR gate that has not passed through the delay buffer (assumed to be the first signal) is a high-level signal, and the high-level signal that the XOR gate needs to pass through the delay buffer has not yet been received. In the initial state, the delay buffer A low-level signal will be output to the XOR gate, so initially the XOR gate receives two different signals, and it outputs a high-level signal to trigger the flip-flop. The Q pin of the flip-flop outputs the low-level signal of the D pin, and the XOR gate receives the low-level signal as the first signal. At this time, the initial high-level signal reaches the XOR gate, so the XOR gate After receiving two different signals, it will output a high-level signal to the flip-flop, thereby triggering the flip-flop. Repeating this cycle, the delay logic module will continuously output high and low level signals. The delay buffer can set the delay time or delay frequency according to the frequency of the clock signal to be output by the delay logic module. Therefore, through the delay buffer, the XOR gate can always receive two signals of different levels (logically representing 0 and 1), thereby outputting a high-level signal (logically representing 1) to trigger the operation of the flip-flop.

As shown in Figure 2, the clock monitoring module includes a low-level counter, a high-level counter and an OR gate. Both low-level and high-level counters require clocks generated by delay logic blocks to function properly. The low-level counter and the high-level counter can respectively record the duration of the low-level pulse signal and the high-level pulse signal. If the original clock in the CPLD is normal, the low-level pulse signal and the high-level pulse signal are carried out evenly; if the low-level counter records that the low-level pulse lasts for a preset period of time, the original clock signal is abnormal; or If the high-level counter records continuous high-level pulses within the preset time period, the original clock signal is abnormal. The preset time period needs to be greater than half of the unit time of the native clock in the CPLD. For example, if a unit time of the native clock in the CPLD is 1 second, then the preset time period must be greater than 0.5 second. The OR gate receives a high-level signal output by the low-level counter or the high-level counter due to an abnormal original clock signal. Therefore, as long as a counter outputs a high-level signal due to an abnormal original clock signal, the OR gate will output a high-level signal. The signal output by the OR gate also represents the final output signal of the delay logic module.

The multiplexer can be a two-to-one multiplexer, that is, one of the two received signals is selected for output. As shown in Figure 2, when the multiplexer receives the high-level signal output by the OR gate of the clock monitoring module, that is, the original clock in the CPLD is abnormal, so the multiplexer will choose to delay the logic clock signal of the logic module and Its output; if the multiplexer receives the low-level signal output by the OR gate of the clock monitoring module, that is, the original clock in the CPLD is normal, the multiplexer will select the original clock signal of the original clock and output it.

The second aspect of the embodiment of the present invention also provides a CPLD working clock keeping system. FIG. 3 is a schematic diagram of an embodiment of the CPLD working clock keeping system provided by the present invention. A kind of CPLD operation clock keeping system comprises: original clock signal monitoring module 10, is configured to respond to CPLD to open, produces logic clock signal by delay logic module preset in CPLD, and logic clock signal is input to clock monitoring module so that It monitors the abnormality of the original clock signal in the CPLD based on the logic clock signal; the clock monitoring signal output module 20 is configured to output the clock monitoring signal based on the monitoring result through the clock monitoring module; and the working clock selection module 30 is configured to pass multiplex The controller receives the clock monitoring signal and selects the logic clock signal or the original clock signal based on the clock monitoring signal and outputs it as the working clock of the CPLD.

The CPLD work clock maintenance system of the embodiment of the present invention can provide clock signal for CPLD by setting delay logic module, makes CPLD need not use the clock that external circuit provides, has saved external hardware, has reduced circuit board area; By setting clock monitoring module , can monitor the abnormality of the original clock inside the CPLD; by setting the multiplexer, the original clock or the preset delay logic module in the CPLD can be selected according to the monitoring situation of the clock monitoring module, thereby selecting a normal clock signal, In order to make the CPLD work normally all the time.

In some embodiments, the native clock signal monitoring module 10 includes an abnormality monitoring module configured to input the logic clock signal to the clock monitoring module, and receive the logic clock signal through the low level counter and the high level counter of the clock monitoring module respectively and the original clock signal; monitor whether the original clock signal continues to be a low-level pulse signal within a preset period of time through a low-level counter based on the logic clock signal, and monitor whether the original clock signal is in the preset time period based on the logic clock signal through a high-level counter It is assumed that the pulse signal of high level continues for a period of time.

In some embodiments, the clock monitoring signal output module 20 is further configured to output a high level through the low level counter in response to the low level counter detecting that the original clock signal continues to be a low level pulse signal within a preset time period signal; or in response to the high-level counter monitoring that the original clock signal continues to be a high-level pulse signal within a preset period of time, a high-level signal is output through the high-level counter; the low-level counter or the high-level High level signal output of the level counter.

In some embodiments, the working clock selection module 30 is further configured to receive the high-level signal of the clock monitoring module through the multiplexer, select a logic clock signal based on the high-level signal, and output it as the working clock of the CPLD.

In some embodiments, the clock monitoring signal output module 20 is further configured to respond to the low-level counter detecting that the original clock signal does not continue to be a low-level pulse signal within a preset period of time and the high-level counter detecting that the original clock The signal does not continue to be a high-level pulse signal within a preset period of time, and outputs a low-level signal through the clock monitoring module.

In some embodiments, the working clock selection module 30 is further configured to receive the low-level signal through the multiplexer, select the original clock signal based on the low-level signal, and output it as the working clock of the CPLD.

In some embodiments, the delay logic module includes a flip-flop, an inverter, an XOR gate, and a delay buffer.

In the third aspect of the embodiment of the present invention, a computer-readable storage medium is also provided. FIG. 4 shows a schematic diagram of a computer-readable storage medium for implementing a method for maintaining a working clock of a CPLD according to an embodiment of the present invention. As shown in Figure 4, the computer-readable storage medium 3 stores computer program instructions 31, and when the computer program instructions 31 are executed, the method of any one of the above-mentioned embodiments is realized:

It should be understood that all the implementations, features and advantages described above for the CPLD working clock keeping method according to the present invention are equally applicable to the CPLD working clock keeping system and storage medium according to the present invention without conflicting with each other.

The fourth aspect of the embodiments of the present invention also provides a computer device, including a memory 402 and a processor 401, a computer program is stored in the memory, and when the computer program is executed by the processor, any one of the above-mentioned embodiments can be realized Methods.

As shown in FIG. 5 , it is a schematic diagram of a hardware structure of an embodiment of a computer device implementing a method for maintaining a CPLD working clock provided by the present invention. Taking the computer equipment shown in FIG. 5 as an example, the computer equipment includes a processor 401 and a memory 402 , and may further include: an input device 403 and an output device 404 . The processor 401, the memory 402, the input device 403, and the output device 404 may be connected via a bus or in other ways. In FIG. 5, connection via a bus is taken as an example. The input device 403 can receive input numbers or character information, and generate key signal input related to user setting and function control of the CPLD working clock maintenance system. The output device 404 may include a display device such as a display screen.

Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs and modules, as in the CPLD working clock keeping method corresponding to the embodiment of the present application Program instructions/modules. The memory 402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and at least one application required by a function; the data storage area may store data created by using the CPLD working clock keeping method, etc. In addition, the memory 402 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 402 may optionally include memory that is remotely located relative to the processor 401, and these remote memories may be connected to the local module through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The processor 401 executes various functional applications and data processing of the server by running non-volatile software programs, instructions and modules stored in the memory 402, that is, implements the CPLD working clock keeping method of the above method embodiment.

Finally, it should be noted that those of ordinary skill in the art can understand that all or part of the process in the above-mentioned embodiment method can be realized, and the relevant hardware can be instructed by a computer program to complete, and the program of the CPLD working clock maintenance method can be stored in a computer-readable When the program is executed, the program may include the processes of the embodiments of the above-mentioned methods. Wherein, the storage medium of the program may be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), and the like. The foregoing computer program embodiments can achieve the same or similar effects as any of the foregoing method embodiments corresponding thereto.

In addition, the above-mentioned method steps and system units can also be realized by using a controller and a computer-readable storage medium for storing a computer program for enabling the controller to realize the functions of the above-mentioned steps or units.

In addition, it should be appreciated that a computer-readable storage medium (eg, memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile memory and nonvolatile memory. By way of example and not limitation, nonvolatile memory can include read only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory memory. Volatile memory can include random access memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM is available in various forms such as Synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced SDRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). Storage devices of the disclosed aspects are intended to include, but are not limited to, these and other suitable types of memory.

Those of skill would also appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described generally in terms of their functionality. Whether such functionality is implemented as software or as hardware depends upon the particular application and design constraints imposed on the overall system. Those skilled in the art may implement the functions in various ways for each specific application, but such implementation decisions should not be interpreted as causing a departure from the scope disclosed in the embodiments of the present invention.

The various exemplary logical blocks, modules, and circuits described in connection with the disclosure herein can be implemented or performed using the following components designed to perform the functions herein: general purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these. A general-purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, eg, a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The above are the exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications can be made without departing from the scope of the disclosed embodiments of the present invention defined in the claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in an individual form, they may also be understood as a plurality unless explicitly limited to a singular number.

It should be understood that as used herein, the singular form "a" and "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items. The serial numbers of the embodiments disclosed in the above-mentioned embodiments of the present invention are only for description, and do not represent the advantages and disadvantages of the embodiments.

Those of ordinary skill in the art should understand that: the discussion of any of the above embodiments is exemplary only, and is not intended to imply that the scope (including claims) disclosed by the embodiments of the present invention is limited to these examples; under the idea of the embodiments of the present invention , the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in details for the sake of brevity. Therefore, within the spirit and principle of the embodiments of the present invention, any omissions, modifications, equivalent replacements, improvements, etc., shall be included in the protection scope of the embodiments of the present invention.

Claims (9)

1. A CPLD working clock keeping method is characterized by comprising the following steps:

responding to the starting of the CPLD, generating a logic clock signal through a delay logic module preset in the CPLD, and inputting the logic clock signal to a clock monitoring module so as to enable the logic clock signal to monitor the abnormality of a native clock signal in the CPLD based on the logic clock signal;

outputting a clock monitoring signal based on a monitoring result through the clock monitoring module;

receiving the clock monitoring signal through a multiplexer, selecting the logic clock signal or the native clock signal based on the clock monitoring signal, and outputting the logic clock signal or the native clock signal as a working clock of the CPLD;

the delay logic module comprises a flip-flop, an inverter, an exclusive-OR gate and a delay buffer;

an output pin Q in the flip-flop is initially jumped from a low level to a high level, the Q is initially output as a high level signal, and the high level signal is changed into a low level signal after passing through the inverter and is input to a pin D of the flip-flop;

the first signal which is received by the exclusive-OR gate and does not pass through the delay buffer is a high level signal, the high level signal which needs to pass through the delay buffer is not received by the exclusive-OR gate, and the delay buffer can output a low level signal to the exclusive-OR gate in an initial state, so that the exclusive-OR gate receives two different signals initially and outputs the high level signal, and the flip-flop is triggered;

the Q pin of the flip-flop outputs the low level signal of the D pin, the XOR gate receives the low level signal as a first signal, and the initial high level signal reaches the XOR gate, so that the XOR gate receives two different signals and outputs the high level signal to the flip-flop, and the flip-flop is triggered to enable the delay logic module to continuously output the high level signal and the low level signal.

2. The method of claim 1, wherein inputting the logical clock signal to a clock monitoring module to cause it to monitor for anomalies in a native clock signal within the CPLD based on the logical clock signal comprises:

inputting the logic clock signal to a clock monitoring module, and respectively receiving the logic clock signal and a native clock signal through a low level counter and a high level counter of the clock monitoring module;

monitoring, by the low level counter, whether the native clock signal continues to be a low level pulse signal for a preset time period based on the logic clock signal, and monitoring, by the high level counter, whether the native clock signal continues to be a high level pulse signal for the preset time period based on the logic clock signal.

3. The method of claim 2, wherein outputting, by the clock monitoring module, a clock monitoring signal based on the monitoring result comprises:

responding to the low-level counter monitoring that the native clock signal is continuously a low-level pulse signal in the preset time period, and outputting a high-level signal through the low-level counter; or

Responding to the fact that the high-level counter monitors that the native clock signal is continuously a high-level pulse signal in the preset time period, and outputting a high-level signal through the high-level counter;

and outputting the high level signal of the low level counter or the high level counter through the clock monitoring module.

4. The method of claim 3, wherein receiving the clock monitor signal by a multiplexer and selecting and outputting the logical clock signal or native clock signal as an operating clock of a CPLD based on the clock monitor signal comprises:

and receiving a high level signal of the clock monitoring module through a multiplexer, selecting the logic clock signal based on the high level signal and outputting the logic clock signal to serve as a working clock of the CPLD.

5. The method of claim 2, wherein outputting, by the clock monitoring module, a clock monitoring signal based on the monitoring result comprises:

outputting, by the clock monitoring module, a low level signal in response to the low level counter monitoring that the native clock signal does not continue to be a low level pulse signal within the preset time period and the high level counter monitoring that the native clock signal does not continue to be a high level pulse signal within the preset time period.

6. The method of claim 5, wherein receiving the clock monitor signal by a multiplexer and selecting and outputting the logical clock signal or native clock signal as an operating clock of a CPLD based on the clock monitor signal comprises:

the low level signal is received by a multiplexer and based on the low level signal the native clock signal is selected and output as the operating clock of the CPLD.

7. A CPLD working clock holding system is characterized by comprising:

the native clock signal monitoring module is configured to respond to the starting of the CPLD, generate a logic clock signal through a delay logic module preset in the CPLD, and input the logic clock signal to the clock monitoring module so as to enable the clock monitoring module to monitor the abnormality of the native clock signal in the CPLD based on the logic clock signal;

the clock monitoring signal output module is configured for outputting a clock monitoring signal based on a monitoring result through the clock monitoring module; and

the working clock selection module is configured to receive the clock monitoring signal through a multiplexer, select the logic clock signal or the native clock signal based on the clock monitoring signal and output the logic clock signal or the native clock signal as a working clock of the CPLD;

the delay logic module comprises a flip-flop, an inverter, an exclusive-OR gate and a delay buffer;

an output pin Q in the flip-flop is initially jumped from a low level to a high level, the Q is initially output as a high level signal, and the high level signal is changed into a low level signal after passing through the inverter and is input to a pin D of the flip-flop;

the first signal which is received by the exclusive-OR gate and does not pass through the delay buffer is a high level signal, the high level signal which needs to pass through the delay buffer is not received by the exclusive-OR gate, and the delay buffer can output a low level signal to the exclusive-OR gate in an initial state, so that the exclusive-OR gate receives two different signals initially and outputs the high level signal, and the flip-flop is triggered;

the Q pin of the flip-flop outputs the low level signal of the D pin, the XOR gate receives the low level signal as a first signal, and the initial high level signal reaches the XOR gate, so that the XOR gate receives two different signals and outputs the high level signal to the flip-flop, and the flip-flop is triggered to enable the delay logic module to continuously output the high level signal and the low level signal.

8. A computer-readable storage medium, characterized in that computer program instructions are stored which, when executed, implement the method according to any one of claims 1-6.

9. A computer device comprising a memory and a processor, characterized in that the memory has stored therein a computer program which, when executed by the processor, performs the method according to any one of claims 1-6.

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