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CN113448781B - A test method, device and equipment for a general input and output interface - Google Patents

A test method, device and equipment for a general input and output interface Download PDF

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Publication number
CN113448781B
CN113448781B CN202010211214.9A CN202010211214A CN113448781B CN 113448781 B CN113448781 B CN 113448781B CN 202010211214 A CN202010211214 A CN 202010211214A CN 113448781 B CN113448781 B CN 113448781B
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pins
group
level
gpio interface
pin
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CN113448781A (en
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李跤
何宏宇
胡磊
林江
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China Mobile Communications Group Co Ltd
China Mobile IoT Co Ltd
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China Mobile IoT Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2247—Verification or detection of system hardware configuration
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

The embodiment of the invention provides a testing method, a testing device and testing equipment of a general input/output interface, wherein the testing method comprises the following steps: sequentially numbering pins of the general purpose input/output GPIO interface; setting the odd-numbered pins as a first group of pins and the even-numbered pins as a second group of pins; wherein an odd-numbered pin is electrically connected to an even-numbered pin; and setting one group of pins in the first group of pins and the second group of pins as an input mode, and setting the other group of pins as an output mode, and if the levels of the first group of pins and the second group of pins are consistent, determining that the pins of the GPIO interface have no faults. The scheme of the invention can automatically test the connectivity of the GPIO pin.

Description

一种通用输入输出接口的测试方法、装置及设备A test method, device and equipment for a general input and output interface

技术领域technical field

本发明涉及通信技术领域，特别是指一种通用输入输出接口的测试方法、装置及设备。The invention relates to the technical field of communication, in particular to a testing method, device and equipment for a general input and output interface.

背景技术Background technique

微控制单元MCU芯片上的引脚一般分为4类：电源、时钟、控制与I/O，I/O口在使用模式上又分为General Purpose Input Output(通用输入/输出，简称GPIO)，与功能复用I/O(如SPI/I2C/UART等)。The pins on the MCU chip of the micro control unit are generally divided into four categories: power supply, clock, control and I/O.

GPIO的工作模式包括：输出模式一般包括：推挽、开漏、上拉、下拉。引脚为输出模式时，可以通过配置引脚输出的电平状态为高电平或低电平来控制连接的外围设备。输入模式一般包括：浮空、上拉、下拉、模拟。引脚为输入模式时，可以读取引脚的电平状态，即高电平或低电平。The working modes of GPIO include: output modes generally include: push-pull, open-drain, pull-up, and pull-down. When the pin is in output mode, you can control the connected peripheral device by configuring the level state of the pin output as high level or low level. Input modes generally include: floating, pull-up, pull-down, and analog. When the pin is in input mode, the level state of the pin can be read, that is, high level or low level.

MCU通过读取/写入GPIO对应的寄存器就可以判断管脚电平高低/控制管脚电平高低。The MCU can determine the level of the pin or control the level of the pin by reading/writing the register corresponding to the GPIO.

现有技术中，一般采用将GPIO管脚接入按键或者LED灯/蜂鸣器，通过人工操作按键，或者人工判断LED灯是否发光，或者人工判断蜂鸣器是否发声来判断GPIO口的好坏/连通性；又或者通过外接硬件电路来检测GPIO的物理信号来判断GPIO口的好坏/连通性(比如最简单的使用万用表来读取管脚电压)In the prior art, it is generally used to connect the GPIO pins to buttons or LED lights/buzzers, and to judge the quality/connectivity of the GPIO port by manually operating the buttons, or manually judging whether the LED light is emitting light, or manually judging whether the buzzer is sounding; or detecting the physical signal of the GPIO port through an external hardware circuit to judge the quality/connectivity of the GPIO port (such as using a multimeter to read the pin voltage in the simplest way)

现有的测试技术方案缺点：1、需要人工操作/判断；2、需要外接硬件检测电路来判断。Disadvantages of existing testing technical solutions: 1. Manual operation/judgment is required; 2. External hardware detection circuit is required for judgment.

发明内容Contents of the invention

本发明要解决的技术问题是提供一种通用输入输出接口的测试方法、装置及设备，从而可以全自动化测试和判断GPIO的好坏/连通性。The technical problem to be solved by the present invention is to provide a test method, device and equipment for a general input and output interface, so that the quality/connectivity of GPIO can be fully automatically tested and judged.

为解决上述技术问题，本发明的技术方案如下：In order to solve the problems of the technologies described above, the technical solution of the present invention is as follows:

一种通用输入输出接口的测试方法，包括：A test method for a general input and output interface, comprising:

将通用输入输出GPIO接口的管脚按顺序编号；Number the pins of the general-purpose input and output GPIO interface in sequence;

将奇数编号的管脚设为第一组管脚，偶数编号的管脚设为第二组管脚；其中，一个奇数编号的管脚与一个偶数编号的管脚电连接；The odd-numbered pins are set as the first group of pins, and the even-numbered pins are set as the second group of pins; wherein, an odd-numbered pin is electrically connected to an even-numbered pin;

将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障。A group of pins in the first group of pins and the second group of pins is set to input mode, and the other group of pins is set to output mode. If the levels of the first group of pins and the second group of pins are consistent, it is determined that there is no fault in the pins of the GPIO interface.

可选的，将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障，包括：Optionally, one group of pins in the first group of pins and the second group of pins is set to input mode, and the other group of pins is set to output mode. If the levels of the first group of pins and the second group of pins are consistent, it is determined that there is no fault in the pins of the GPIO interface, including:

将所述第一组管脚设置为输入模式，所述第二组管脚设置为输出模式，若所述第一组管脚为高电平时，所述第二组管脚的电平为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平也转为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障；或者，Setting the first group of pins to an input mode, and setting the second group of pins to an output mode, if the first group of pins is at a high level, the level of the second group of pins is at a high level, and when the first group of pins turns to a low level, the level of the second group of pins also turns to a low level, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that the tested pins of the GPIO interface do not have faults; or,

将所述第一组管脚设置为输出模式，所述第二组管脚设置为输入模式，若所述第一组管脚为高电平时，所述第二组管脚的电平也转为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障。The first group of pins is set to the output mode, and the second group of pins is set to the input mode. If the first group of pins is at a high level, the level of the second group of pins also turns to a high level, and when the first group of pins turns to a low level, the level of the second group of pins is low, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that there is no fault in the tested pins of the GPIO interface.

可选的，若所述GPIO接口的管脚的总数为偶数，确定所述GPIO接口的已测试管脚不存在故障，包括：Optionally, if the total number of pins of the GPIO interface is an even number, it is determined that there is no fault in the tested pins of the GPIO interface, including:

确定所述GPIO接口的全部管脚不存在故障。It is determined that all pins of the GPIO interface are not faulty.

可选的，若所述GPIO接口的管脚的总数为奇数，还包括：Optionally, if the total number of pins of the GPIO interface is an odd number, it also includes:

将剩余的没有测试的一个管脚与已测试过的任一管脚电连接，将两个测试的管脚中的一个设置为输入模式，另一个设置为输出模式，如果两个管脚的电平一致，则确定所述GPIO接口的全部管脚不存在故障。Electrically connect the remaining untested pin to any pin that has been tested, set one of the two tested pins to input mode, and set the other to output mode. If the levels of the two pins are consistent, it is determined that all pins of the GPIO interface do not have faults.

本发明的实施例还提供一种通用输入输出接口的测试装置，包括：Embodiments of the present invention also provide a test device for a universal input and output interface, including:

第一处理模块，用于将通用输入输出GPIO接口的管脚按顺序编号；The first processing module is used to number the pins of the general input and output GPIO interface in sequence;

第二处理模块，用于将奇数编号的管脚设为第一组管脚，偶数编号的管脚设为第二组管脚；其中，一个奇数编号的管脚与一个偶数编号的管脚电连接；The second processing module is configured to set the odd-numbered pins as the first group of pins, and the even-numbered pins as the second group of pins; wherein, an odd-numbered pin is electrically connected to an even-numbered pin;

第三处理模块，用于将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障。The third processing module is used to set a group of pins in the first group of pins and the second group of pins as an input mode, and set the other group of pins as an output mode, and if the levels of the first group of pins and the second group of pins are consistent, it is determined that there is no fault in the pins of the GPIO interface.

可选的，将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障，包括：Optionally, one group of pins in the first group of pins and the second group of pins is set to input mode, and the other group of pins is set to output mode. If the levels of the first group of pins and the second group of pins are consistent, it is determined that there is no fault in the pins of the GPIO interface, including:

将所述第一组管脚设置为输入模式，所述第二组管脚设置为输出模式，若所述第一组管脚为高电平时，所述第二组管脚的电平为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平也转为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障；或者，Setting the first group of pins to an input mode, and setting the second group of pins to an output mode, if the first group of pins is at a high level, the level of the second group of pins is at a high level, and when the first group of pins turns to a low level, the level of the second group of pins also turns to a low level, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that the tested pins of the GPIO interface do not have faults; or,

将所述第一组管脚设置为输出模式，所述第二组管脚设置为输入模式，若所述第一组管脚为高电平时，所述第二组管脚的电平也转为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障。The first group of pins is set to the output mode, and the second group of pins is set to the input mode. If the first group of pins is at a high level, the level of the second group of pins also turns to a high level, and when the first group of pins turns to a low level, the level of the second group of pins is low, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that there is no fault in the tested pins of the GPIO interface.

可选的，若所述GPIO接口的管脚的总数为偶数，确定所述GPIO接口的已测试管脚不存在故障，包括：Optionally, if the total number of pins of the GPIO interface is an even number, it is determined that there is no fault in the tested pins of the GPIO interface, including:

确定所述GPIO接口的全部管脚不存在故障。It is determined that all pins of the GPIO interface are not faulty.

可选的，若所述GPIO接口的管脚的总数为奇数，还包括：Optionally, if the total number of pins of the GPIO interface is an odd number, it also includes:

将剩余的没有测试的一个管脚与已测试过的任一管脚电连接，将两个测试的管脚中的一个设置为输入模式，另一个设置为输出模式，如果两个管脚的电平一致，则确定所述GPIO接口的全部管脚不存在故障。Electrically connect the remaining untested pin to any pin that has been tested, set one of the two tested pins to input mode, and set the other to output mode. If the levels of the two pins are consistent, it is determined that all pins of the GPIO interface do not have faults.

本发明的实施例一种通用输入输出接口的测试设备，包括：处理器、存储有计算机程序的存储器，所述计算机程序被处理器运行时，执行如上所述的方法。An embodiment of the present invention is a test device for a universal input and output interface, including: a processor, and a memory storing a computer program, and when the computer program is run by the processor, the above-mentioned method is executed.

本发明的实施例一种计算机可读存储介质，包括指令，当所述指令在计算机运行时，使得计算机执行如上所述的方法。An embodiment of the present invention is a computer-readable storage medium, including instructions, and when the instructions are run on a computer, the computer is made to execute the above-mentioned method.

本发明的上述方案至少包括以下有益效果：Above-mentioned scheme of the present invention comprises following beneficial effect at least:

本发明的上述方案，将通用输入输出GPIO接口的管脚按顺序编号；将奇数编号的管脚设为第一组管脚，偶数编号的管脚设为第二组管脚；其中，一个奇数编号的管脚与一个偶数编号的管脚电连接；将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障。从而可以全自动化测试和判断GPIO的好坏/连通性。In the above scheme of the present invention, the pins of the general-purpose input and output GPIO interface are numbered in order; the odd-numbered pins are set as the first group of pins, and the even-numbered pins are set as the second group of pins; wherein, an odd-numbered pin is electrically connected to an even-numbered pin; one group of pins in the first group of pins and the second group of pins is set as input mode, and the other group of pins is set as output mode. failure. In this way, it is possible to fully automate the test and judge the quality/connectivity of GPIO.

附图说明Description of drawings

图1是本发明的通用输入输出接口的测试方法的流程示意图；Fig. 1 is the schematic flow sheet of the testing method of general input and output interface of the present invention;

图2是本发明的通用输入输出接口的测试装置的模块示意图。FIG. 2 is a block diagram of a testing device for a universal input and output interface of the present invention.

具体实施方式Detailed ways

下面将参照附图更详细地描述本公开的示例性实施例。虽然附图中显示了本公开的示例性实施例，然而应当理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了能够更透彻地理解本公开，并且能够将本公开的范围完整的传达给本领域的技术人员。Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided for more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

如图1所示，本发明的实施例提出一种通用输入输出接口的测试方法，包括：As shown in Figure 1, the embodiment of the present invention proposes a kind of testing method of general input and output interface, comprises:

步骤11，将通用输入输出GPIO接口的管脚按顺序编号；Step 11, number the pins of the GPIO interface in sequence;

步骤12，将奇数编号的管脚设为第一组管脚，偶数编号的管脚设为第二组管脚；其中，一个奇数编号的管脚与一个偶数编号的管脚电连接；Step 12, set the odd-numbered pins as the first group of pins, and the even-numbered pins as the second group of pins; wherein, an odd-numbered pin is electrically connected to an even-numbered pin;

步骤13，将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障。Step 13, setting one group of pins in the first group of pins and the second group of pins as an input mode, and setting the other group of pins as an output mode, and if the levels of the first group of pins and the second group of pins are consistent, it is determined that there is no fault in the pins of the GPIO interface.

本发明的该实施例通过代码测试两组管脚的电平是否一致，可以全自动化测试和判断GPIO的好坏/连通性。This embodiment of the present invention tests whether the levels of the two groups of pins are consistent through the code, and can fully automatically test and judge the quality/connectivity of the GPIO.

本发明的一可选的实施例中，步骤13可以包括：In an optional embodiment of the present invention, step 13 may include:

步骤131，将所述第一组管脚设置为输入模式，所述第二组管脚设置为输出模式，若所述第一组管脚为高电平时，所述第二组管脚的电平为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平也转为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障；或者，Step 131, setting the first group of pins to an input mode, and the second group of pins to an output mode, if the first group of pins is at a high level, the level of the second group of pins is at a high level, and when the first group of pins is at a low level, the level of the second group of pins is also at a low level, and when the first group of pins is at a high level again, the level of the second group of pins is at a high level, then it is determined that there is no fault in the tested pin of the GPIO interface; or,

步骤132，将所述第一组管脚设置为输出模式，所述第二组管脚设置为输入模式，若所述第一组管脚为高电平时，所述第二组管脚的电平为高电平，并且，所述第一组管脚为转低电平时，所述第二组管脚的电平也转为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障。Step 132: Set the first group of pins to an output mode, and the second group of pins to an input mode. If the first group of pins is at a high level, the level of the second group of pins is at a high level, and when the first group of pins is at a low level, the level of the second group of pins is also at a low level, and when the first group of pins is at a high level again, the level of the second group of pins is at a high level, then it is determined that there is no fault in the tested pins of the GPIO interface.

本发明的一可选的实施例中，若所述GPIO接口的管脚的总数为偶数，确定所述GPIO接口的已测试管脚不存在故障，包括：确定所述GPIO接口的全部管脚不存在故障。In an optional embodiment of the present invention, if the total number of pins of the GPIO interface is an even number, determining that there is no fault in the tested pins of the GPIO interface includes: determining that all pins of the GPIO interface have no fault.

本发明的一可选的实施例中，若所述GPIO接口的管脚的总数为奇数，通用输入输出接口的测试方法还包括：In an optional embodiment of the present invention, if the total number of pins of the GPIO interface is an odd number, the test method of the general input and output interface also includes:

将剩余的没有测试的一个管脚与已测试过的任一管脚电连接，将两个测试的管脚中的一个设置为输入模式，另一个设置为输出模式，如果两个管脚的电平一致，则确定所述GPIO接口的全部管脚不存在故障。Electrically connect the remaining untested pin to any pin that has been tested, set one of the two tested pins to input mode, and set the other to output mode. If the levels of the two pins are consistent, it is determined that all pins of the GPIO interface do not have faults.

下面结合具体实施例说明上述方法的具体实现过程：The concrete realization process of above-mentioned method is described below in conjunction with specific embodiment:

1、将待验证的GPIO接口的管脚分成2部分：奇数组/偶数组，奇数组编号为1，3，5，7…，偶数组编号为2，4，6，8…；如果GPIO管脚总数为奇数，那么最后一个GPIO管脚编号记为2n+1。1. Divide the pins of the GPIO interface to be verified into two parts: odd group/even group, odd group numbers are 1, 3, 5, 7..., even group numbers are 2, 4, 6, 8...; if the total number of GPIO pins is an odd number, then the last GPIO pin number is recorded as 2n+1.

2、使用杜邦线将GPIO口连接起来，奇数编号和偶数编号对应相连，比如1-2，3-4，5-6…；如果GPIO管脚总数为奇数，那么2n+1管脚先空着。2. Use DuPont lines to connect the GPIO ports, and the odd numbers and even numbers are connected correspondingly, such as 1-2, 3-4, 5-6...; if the total number of GPIO pins is odd, then the 2n+1 pins are empty first.

3、测试代码中将奇数组的管脚设置为输出模式，偶数组管脚设置为输入模式。3. In the test code, set the pins of the odd group to the output mode, and the pins of the even group to the input mode.

4、测试代码中奇数组管脚设置输出高电平，代码检测偶数组管脚的电平，预期：此时偶数组管脚电平全部为高；测试代码中奇数组管脚设置输出低电平，代码检测偶数组管脚电平，预期：此时偶数组管脚电平全部为低；测试代码中奇数组管脚设置输出高电平，代码检测偶数组管脚电平，预期：此时偶数组管脚电平全部为高。4. In the test code, the odd group pins are set to output high level, and the code detects the level of the even group pins. It is expected that the levels of the even group pins are all high at this time;

5、测试代码中将偶数组的管脚设置为输出模式，奇数组管脚设置为输入模式。5. In the test code, set the pins of the even group to the output mode, and the pins of the odd group to the input mode.

6、测试代码中偶数组管脚设置输出高电平，代码检测奇数组管脚的电平，预期：此时奇数组管脚电平全部为高；测试代码中偶数组管脚设置输出低电平，代码检测奇数组管脚电平，预期：此时奇数组管脚电平全部为低；测试代码中偶数组管脚设置输出高电平，代码检测奇数组管脚电平，预期：此时奇数组管脚电平全部为高。6. In the test code, the even group pins are set to output high level, and the code detects the level of the odd group pins. It is expected that the levels of the odd group pins are all high at this time;

7、如果GPIO管脚总数为奇数，将编号为2n+1的管脚和编号2n的管脚用杜邦线连接起来，使用类似步骤3-6完成测试。7. If the total number of GPIO pins is odd, connect the pin numbered 2n+1 and the pin numbered 2n with a DuPont line, and use similar steps 3-6 to complete the test.

8、GPIO管脚连通性检测完成，如果全部符合预期，测试通过；否则失败。8. The GPIO pin connectivity test is completed. If all meet expectations, the test passes; otherwise, it fails.

本发明的上述实施例，对GPIO的管脚测试，简单可靠，通用性好，无需额外硬件检测电路。全自动化测试和判断结果，无需人工干预。方便研发时做单元测试或者生产时工厂做单板测试。In the above-mentioned embodiment of the present invention, the pin test of GPIO is simple and reliable, has good versatility, and does not require additional hardware detection circuits. Fully automated testing and judging results without manual intervention. It is convenient for unit testing during R&D or single board testing during production.

如图2所示，本发明的实施例还提供一种通用输入输出接口的测试装置20，包括：As shown in Figure 2, the embodiment of the present invention also provides a test device 20 of a universal input and output interface, including:

第一处理模块21，用于将通用输入输出GPIO接口的管脚按顺序编号；The first processing module 21 is used to number the pins of the general input and output GPIO interface in sequence;

第二处理模块22，用于将奇数编号的管脚设为第一组管脚，偶数编号的管脚设为第二组管脚；其中，一个奇数编号的管脚与一个偶数编号的管脚电连接；The second processing module 22 is configured to set the odd-numbered pins as the first group of pins, and the even-numbered pins as the second group of pins; wherein, an odd-numbered pin is electrically connected to an even-numbered pin;

第三处理模块23，用于将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障。The third processing module 23 is used to set one group of pins in the first group of pins and the second group of pins as an input mode, and another group of pins is set as an output mode. If the levels of the first group of pins and the second group of pins are consistent, it is determined that there is no fault in the pins of the GPIO interface.

可选的，将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障，包括：Optionally, one group of pins in the first group of pins and the second group of pins is set to input mode, and the other group of pins is set to output mode. If the levels of the first group of pins and the second group of pins are consistent, it is determined that there is no fault in the pins of the GPIO interface, including:

将所述第一组管脚设置为输入模式，所述第二组管脚设置为输出模式，若所述第一组管脚为高电平时，所述第二组管脚的电平为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平也转为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障；或者，Setting the first group of pins to an input mode, and setting the second group of pins to an output mode, if the first group of pins is at a high level, the level of the second group of pins is at a high level, and when the first group of pins turns to a low level, the level of the second group of pins also turns to a low level, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that the tested pins of the GPIO interface do not have faults; or,

将所述第一组管脚设置为输出模式，所述第二组管脚设置为输入模式，若所述第一组管脚为高电平时，所述第二组管脚的电平也转为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障。The first group of pins is set to the output mode, and the second group of pins is set to the input mode. If the first group of pins is at a high level, the level of the second group of pins also turns to a high level, and when the first group of pins turns to a low level, the level of the second group of pins is low, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that there is no fault in the tested pins of the GPIO interface.

可选的，若所述GPIO接口的管脚的总数为偶数，确定所述GPIO接口的已测试管脚不存在故障，包括：Optionally, if the total number of pins of the GPIO interface is an even number, it is determined that there is no fault in the tested pins of the GPIO interface, including:

确定所述GPIO接口的全部管脚不存在故障。It is determined that all pins of the GPIO interface are not faulty.

可选的，若所述GPIO接口的管脚的总数为奇数，还包括：Optionally, if the total number of pins of the GPIO interface is an odd number, it also includes:

将剩余的没有测试的一个管脚与已测试过的任一管脚电连接，将两个测试的管脚中的一个设置为输入模式，另一个设置为输出模式，如果两个管脚的电平一致，则确定所述GPIO接口的全部管脚不存在故障。Electrically connect the remaining untested pin to any pin that has been tested, set one of the two tested pins to input mode, and set the other to output mode. If the levels of the two pins are consistent, it is determined that all pins of the GPIO interface do not have faults.

需要说明的是，上述方法实施例的所有实现方式均适用于该装置的实施例中，也能达到相同的技术效果。It should be noted that all the implementation manners of the foregoing method embodiments are applicable to the device embodiments, and can also achieve the same technical effect.

本发明的实施例一种通用输入输出接口的测试设备，包括：处理器、存储有计算机程序的存储器，所述计算机程序被处理器运行时，执行如上所述的方法。上述方法实施例的所有实现方式均适用于该装置的实施例中，也能达到相同的技术效果。An embodiment of the present invention is a test device for a universal input and output interface, including: a processor, and a memory storing a computer program, and when the computer program is run by the processor, the above-mentioned method is executed. All the implementation manners of the foregoing method embodiments are applicable to the device embodiments, and can also achieve the same technical effect.

本发明的实施例一种计算机可读存储介质，包括指令，当所述指令在计算机运行时，使得计算机执行如上所述的方法。上述方法实施例的所有实现方式均适用于该装置的实施例中，也能达到相同的技术效果。An embodiment of the present invention is a computer-readable storage medium, including instructions, and when the instructions are run on a computer, the computer is made to execute the above-mentioned method. All the implementation manners of the foregoing method embodiments are applicable to the device embodiments, and can also achieve the same technical effect.

以上所述是本发明的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本发明的保护范围。The above is a preferred embodiment of the present invention, it should be pointed out that for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications should also be considered as the protection scope of the present invention.

Claims (8)

1.一种通用输入输出接口的测试方法，其特征在于，包括：1. A test method for a general-purpose input and output interface, characterized in that, comprising: 将通用输入输出GPIO接口的管脚按顺序编号；Number the pins of the general-purpose input and output GPIO interface in sequence; 将奇数编号的管脚设为第一组管脚，偶数编号的管脚设为第二组管脚；其中，一个奇数编号的管脚与一个偶数编号的管脚电连接；The odd-numbered pins are set as the first group of pins, and the even-numbered pins are set as the second group of pins; wherein, an odd-numbered pin is electrically connected to an even-numbered pin; 将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障；Setting one group of pins in the first group of pins and the second group of pins to the input mode, and setting the other group of pins to the output mode, if the levels of the first group of pins and the second group of pins are consistent, it is determined that there is no fault in the pins of the GPIO interface; 其中，将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障，包括：Wherein, one group of pins in the first group of pins and the second group of pins is set to the input mode, and the other group of pins is set to the output mode, and if the levels of the first group of pins and the second group of pins are consistent, then it is determined that there is no fault in the pins of the GPIO interface, including: 将所述第一组管脚设置为输入模式，所述第二组管脚设置为输出模式，若所述第一组管脚为高电平时，所述第二组管脚的电平为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平也转为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障；或者，Setting the first group of pins to an input mode, and setting the second group of pins to an output mode, if the first group of pins is at a high level, the level of the second group of pins is at a high level, and when the first group of pins turns to a low level, the level of the second group of pins also turns to a low level, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that the tested pins of the GPIO interface do not have faults; or, 将所述第一组管脚设置为输出模式，所述第二组管脚设置为输入模式，若所述第一组管脚为高电平时，所述第二组管脚的电平为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平也转为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障。The first group of pins is set to the output mode, and the second group of pins is set to the input mode. If the first group of pins is at a high level, the level of the second group of pins is high, and when the first group of pins is turned to a low level, the level of the second group of pins is also turned to a low level. 2.根据权利要求1所述的通用输入输出接口的测试方法，其特征在于，若所述GPIO接口的管脚的总数为偶数，确定所述GPIO接口的已测试管脚不存在故障，包括：2. the test method of general input output interface according to claim 1, is characterized in that, if the total number of the pin of described GPIO interface is an even number, it is determined that the tested pin of described GPIO interface does not have fault, comprising: 确定所述GPIO接口的全部管脚不存在故障。It is determined that all pins of the GPIO interface are not faulty. 3.根据权利要求1所述的通用输入输出接口的测试方法，其特征在于，若所述GPIO接口的管脚的总数为奇数，还包括：3. the testing method of general-purpose input and output interface according to claim 1, is characterized in that, if the total number of the pin of described GPIO interface is an odd number, also comprises: 将剩余的没有测试的一个管脚与已测试过的任一管脚电连接，将两个测试的管脚中的一个设置为输入模式，另一个设置为输出模式，如果两个管脚的电平一致，则确定所述GPIO接口的全部管脚不存在故障。Electrically connect the remaining untested pin to any pin that has been tested, set one of the two tested pins to input mode, and set the other to output mode. If the levels of the two pins are consistent, it is determined that all pins of the GPIO interface do not have faults. 4.一种通用输入输出接口的测试装置，其特征在于，包括：4. A test device for a universal input and output interface, characterized in that it comprises: 第一处理模块，用于将通用输入输出GPIO接口的管脚按顺序编号；The first processing module is used to number the pins of the general input and output GPIO interface in sequence; 第二处理模块，用于将奇数编号的管脚设为第一组管脚，偶数编号的管脚设为第二组管脚；其中，一个奇数编号的管脚与一个偶数编号的管脚电连接；The second processing module is configured to set the odd-numbered pins as the first group of pins, and the even-numbered pins as the second group of pins; wherein, an odd-numbered pin is electrically connected to an even-numbered pin; 第三处理模块，用于将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障；A third processing module, configured to set one group of pins in the first group of pins and the second group of pins as an input mode, and set the other group of pins as an output mode, and if the levels of the first group of pins and the second group of pins are consistent, then determine that there is no fault in the pins of the GPIO interface; 其中，将所述第一组管脚和所述第二组管脚中的一组管脚设置为输入模式，另一组管脚设置为输出模式，若第一组管脚和所述第二组管脚的电平一致，则确定所述GPIO接口的管脚不存在故障，包括：Wherein, one group of pins in the first group of pins and the second group of pins is set to the input mode, and the other group of pins is set to the output mode, and if the levels of the first group of pins and the second group of pins are consistent, then it is determined that there is no fault in the pins of the GPIO interface, including: 将所述第一组管脚设置为输入模式，所述第二组管脚设置为输出模式，若所述第一组管脚为高电平时，所述第二组管脚的电平为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平也转为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障；或者，Setting the first group of pins to an input mode, and setting the second group of pins to an output mode, if the first group of pins is at a high level, the level of the second group of pins is at a high level, and when the first group of pins turns to a low level, the level of the second group of pins also turns to a low level, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that the tested pins of the GPIO interface do not have faults; or, 将所述第一组管脚设置为输出模式，所述第二组管脚设置为输入模式，若所述第一组管脚为高电平时，所述第二组管脚的电平也转为高电平，并且，所述第一组管脚转为低电平时，所述第二组管脚的电平为低电平，并且所述第一组管脚再转为高电平时，所述第二组管脚的电平再转为高电平，则确定所述GPIO接口的已测试的管脚不存在故障。The first group of pins is set to the output mode, and the second group of pins is set to the input mode. If the first group of pins is at a high level, the level of the second group of pins also turns to a high level, and when the first group of pins turns to a low level, the level of the second group of pins is low, and when the first group of pins turns to a high level again, the level of the second group of pins turns to a high level again, then it is determined that there is no fault in the tested pins of the GPIO interface. 5.根据权利要求4所述的通用输入输出接口的测试装置，其特征在于，若所述GPIO接口的管脚的总数为偶数，确定所述GPIO接口的已测试管脚不存在故障，包括：5. the testing device of general input output interface according to claim 4, it is characterized in that, if the total number of the pins of described GPIO interface is an even number, determine that the tested pin of described GPIO interface does not have fault, comprising: 确定所述GPIO接口的全部管脚不存在故障。It is determined that all pins of the GPIO interface are not faulty. 6.根据权利要求4所述的通用输入输出接口的测试装置，其特征在于，若所述GPIO接口的管脚的总数为奇数，还包括：6. the testing device of general input output interface according to claim 4, is characterized in that, if the total number of the pin of described GPIO interface is an odd number, also comprises: 将剩余的没有测试的一个管脚与已测试过的任一管脚电连接，将两个测试的管脚中的一个设置为输入模式，另一个设置为输出模式，如果两个管脚的电平一致，则确定所述GPIO接口的全部管脚不存在故障。Electrically connect the remaining untested pin to any pin that has been tested, set one of the two tested pins to input mode, and set the other to output mode. If the levels of the two pins are consistent, it is determined that all pins of the GPIO interface do not have faults. 7.一种通用输入输出接口的测试设备，其特征在于，包括：处理器、存储有计算机程序的存储器，所述计算机程序被处理器运行时，执行如权利要求1至3任一项所述的方法。7. A testing device for a general input and output interface, characterized in that it comprises: a processor and a memory storing a computer program, and when the computer program is run by the processor, the method according to any one of claims 1 to 3 is executed. 8.一种计算机可读存储介质，其特征在于，包括指令，当所述指令在计算机运行时，使得计算机执行如权利要求1至3任一项所述的方法。8. A computer-readable storage medium, characterized by comprising instructions, and when the instructions are run on a computer, the computer is made to execute the method according to any one of claims 1 to 3.
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