CN113451317B - Nonvolatile memory device and method of manufacturing the same - Google Patents

Abstract

The invention provides a nonvolatile memory device and a method for manufacturing the same. The nonvolatile memory device includes a substrate, a plurality of first gate structures and a plurality of second gate structures formed on the substrate. The substrate includes a central region located in the array region and two edge regions located on opposite sides outside the central region. The first gate structure is located in the center region and the second gate structure is located in one of the edge regions. Each first gate structure has a first width and each second gate structure has a second width smaller than the first width. The first gate structures have a first spacing therebetween, and the second gate structures have a second spacing therebetween that is greater than the first spacing. The invention can improve the yield, reliability, durability and operation consistency of the memory device.

Description

Nonvolatile memory device and method of manufacturing the same

Technical Field

The present invention relates to a memory device, and more particularly, to a nonvolatile memory device and a method for manufacturing the same.

Background

With the shrinking of the manufacturing process, in the existing flash memory, the contact structure between the gate structures usually has a high aspect ratio and has a problem of high contact resistance, and even the contact structure cannot be electrically connected with the substrate, which easily causes the failure of the flash memory. In this way, the yield of the flash memory will be reduced. In addition, as the spacing between gate structures becomes smaller, the uniformity of these contact structures becomes difficult to control, making the erase capability of multiple memory cells of the flash memory non-uniform. To avoid the above problems, the pitch between gate structures is generally increased by reducing the width of each gate structure in the memory array. However, as the width of the gate structure decreases, there are problems in that the data holding capacity decreases and the operation time becomes long. Therefore, it is a urgent need for improvement in the art to reduce the contact resistance of the contact structure and improve the uniformity of the contact structure while avoiding the influence of the data storage capability and the operation time.

Disclosure of Invention

The embodiment of the invention provides a nonvolatile memory device and a manufacturing method thereof, which can improve the yield, reliability, durability and operation consistency of the memory device.

An embodiment of the invention discloses a nonvolatile memory device comprising: the substrate comprises a central area positioned in the array area and two edge areas positioned at two opposite sides outside the central area; and a plurality of memory cells constituting an array region, the memory cells including: a plurality of first gate structures formed on the substrate and located in the central region, each first gate structure having a first width and a first spacing therebetween; and a plurality of second gate structures formed on the substrate and located in one of the edge regions, each second gate structure having a second width smaller than the first width, and having a second pitch larger than the first pitch therebetween.

An embodiment of the invention discloses a method for manufacturing a nonvolatile memory device, which comprises the following steps: defining a central region of an array region on the substrate and two edge regions positioned at two opposite sides outside the central region; and forming a plurality of memory cells constituting an array region, comprising: forming a plurality of first gate structures in a central region on a substrate, wherein each first gate structure has a first width and a first interval is formed between the first gate structures; and forming a plurality of second gate structures in one of the edge regions on the substrate, wherein each of the second gate structures has a second width smaller than the first width, and a second pitch larger than the first pitch is provided between the second gate structures.

According to the non-volatile memory device and the manufacturing method provided by the embodiment of the invention, the uniformity of the size of the gate structure can be improved, and the problem that the contact resistance of a subsequently formed contact structure is overlarge due to unexpected narrowing of the spacing of the gate structure in the edge area of the array area in the manufacturing process is solved. Therefore, the operation consistency of the memory device can be obviously improved, the problem of failure of the memory device can be reduced or avoided, and the yield, reliability and durability of the memory device can be greatly improved.

Drawings

FIG. 1 is a schematic top view of a non-volatile memory device according to some embodiments of the present invention;

FIG. 2 is a schematic top view of an array region according to some embodiments of the invention;

FIGS. 3A-3D are schematic cross-sectional views of an array region at various stages of a fabrication process according to some embodiments of the invention;

FIG. 4 is a schematic top view of an array region according to further embodiments of the present invention;

FIG. 5 is a schematic cross-sectional view of an array region according to other embodiments of the present invention.

Symbol description

10: center region 134: gap filling dielectric layer

20: edge region 142: contact structure

30: intermediate region 200a: first bit line selection circuit

100: array region 200b: second bit line selection circuit

102: substrate 300: word line selection circuit

104: tunnel oxide layer D1: first direction

110a: first gate stack D2: second direction

110b: second gate stack H1: first height of

112: floating gate layer H2: second height

112a: first floating gate H3: third height

112b: second floating gate S1: first distance of

112c: third floating gate S2: second distance

114: gate dielectric layer S3: third distance

116: control gate layer T1: first thickness of

118: conductive metal layer T2: second thickness of

120a: first gate structure T3: third thickness of

120b: second gate structure W1: first width of

120c: third gate structure W2: second width of

122: cap layer 500: nonvolatile memory device

132: protective layer

Detailed Description

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments, as illustrated in the accompanying drawings. Furthermore, repeated reference characters and/or words may be used in various examples of the invention. These repeated symbols or words are for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or the appearance structures.

The terms "about" and "approximately" herein generally mean within 20%, preferably within 10%, and more preferably within 5% of a given value or range. The amounts given herein are about amounts, i.e., without specific recitation, the meaning of "about" may still be implied. In the present specification, "X is equal to or close to Y" means that the absolute value of the difference between the two is within 5.0% of the larger one.

The present invention provides a nonvolatile memory device and a method for manufacturing the same, and fig. 1 is a schematic top view of a nonvolatile memory device 500 according to some embodiments of the present invention. Fig. 2 is a schematic top view of an array region 100 according to some embodiments of the invention. In one embodiment, the non-volatile memory device is a NOR flash memory.

Referring to fig. 1 and 2, the nonvolatile memory device 500 includes a plurality of array regions 100 and peripheral circuit regions surrounding the array regions 100. Each array region 100 is composed of a plurality of memory cells and includes a central region 10 and edge regions 20 located on opposite sides of the central region 10. A plurality of first gate structures 120a parallel to each other are formed in the central region 10 and extend along the first direction D1. A plurality of second gate structures 120b parallel to each other are formed in the edge region 20 and extend along the first direction D1. Each memory cell includes a first gate structure 120a or a second gate structure 120b. In the present embodiment, the long axis of the edge region 20 extends along the first direction D1. The plurality of decoders are disposed in the peripheral circuit region. In this embodiment, the decoder includes a first bit line selection circuit 200a and a second bit line selection circuit 200b on opposite sides of the array region 100, and a word line selection circuit 300 on the other side of the array region 100. More specifically, the first bit line selection circuit 200a and the second bit line selection circuit 200b extend along the first direction D1. The word line selection circuit 300 extends along a second direction D2 perpendicular to the first direction D1. By the word line selection circuit 300, the first bit line selection circuit 200a and the second bit line selection circuit 200b adjacent to the array region 100, a specific memory cell can be selected in the array region 100 for corresponding operation. The first and second bit line selection circuits 200a and 200b and the word line selection circuit 300 may be formed by a prior art forming method, and will not be described in detail herein.

Fig. 3A-3D are schematic cross-sectional views of an array region 100 at various stages of a manufacturing process according to some embodiments of the invention. Fig. 3A to 3D are drawn along a sectional line AA' of fig. 2.

Referring to fig. 3A, a tunnel oxide layer 104 is formed on a substrate 102. The material of the substrate 102 may include silicon, gallium arsenide, gallium nitride, germanium silicide, silicon-on-insulator (silicon on insulator, SOI), or combinations thereof. In the present embodiment, the substrate 102 is a silicon substrate. In some embodiments, other structures, such as isolation structures, p-type implant regions, or n-type implant regions (not shown), may also be formed in the substrate 102. The isolation structure includes a first portion and a second portion, the first portion of the isolation structure is disposed on the second portion of the isolation structure, and a bottom surface of the first portion is higher than a top surface of the substrate 102. In some embodiments, the first portion may be a high density plasma oxide and the second portion may be spin-on glass. The tunnel oxide layer 104 may be formed by, for example, a thermal oxidation process or a deposition process.

Next, a floating gate material is formed over tunnel oxide layer 104. Wherein the floating gate material fills the tunnel oxide layer 104 between the isolation structures in a direction along the first gate structure 120a and the second gate structure 120b (not shown). The floating gate material may comprise monocrystalline silicon, polycrystalline silicon, amorphous silicon, or other suitable conductive material. In this embodiment, the floating gate material is polysilicon. The floating gate material may be formed by, for example, a furnace process, a chemical vapor deposition process, an atomic layer deposition process, or a combination thereof.

Next, a planarization process (e.g., a chemical mechanical polishing process) is performed on the floating gate material such that a top surface of the floating gate material is coplanar with a top surface of the first portion of the isolation structure to form the floating gate layer 112. In some embodiments, floating gate layer 112 is doped polysilicon and thus has better conductivity. In such embodiments, the dopant may be a p-type dopant (e.g., boron) or an n-type dopant (e.g., phosphorus). In this embodiment, after forming the floating gate layers 112, the first portions of the isolation structures may be partially removed to form recesses (not shown) between the floating gate layers 112.

Then, a gate dielectric layer 114 is conformally formed over the floating gate layer 112, and a control gate layer 116 is conformally formed over the gate dielectric layer 114. The material of the gate dielectric layer 114 may include an oxide, nitride, oxynitride, other suitable dielectric material, or a combination thereof. In the present embodiment, the gate dielectric layer 114 is a three-layer structure formed by silicon oxide/silicon nitride/silicon oxide. The gate dielectric layer 114 may be formed by a chemical vapor deposition fabrication process. The material and formation method of the control gate layer 116 may be the same as or similar to the material and formation method of the floating gate layer 112 and will not be described in detail herein.

Next, a conductive metal layer 118 is conformally formed on the control gate layer 116, and a capping material is conformally formed on the conductive metal layer 118. Thereafter, the cap layer material is patterned to form cap layer 122. The conductive metal layer 118 may be used to electrically connect the gate structure with external circuitry. The material of the conductive metal layer 118 may include tungsten, titanium, tungsten silicide, other suitable metals, or combinations thereof. In this embodiment, the conductive metal layer 118 is tungsten. The capping layer material may comprise an oxide, nitride, oxynitride, other suitable insulating material, or a combination thereof. In this embodiment, the capping layer material includes a nitride disposed on the conductive metal layer 118 and an oxide disposed on the nitride.

Referring to fig. 3B, a patterning process is performed on the floating gate layer 112, the gate dielectric layer 114, the control gate layer 116 and the conductive metal layer 118 according to the cap layer 122 to simultaneously form a plurality of first gate stacks 110a and a plurality of second gate stacks 110B on the substrate 102 in the same step. The width of the first gate stack 110a is greater than the width of the second gate stack 110b, and the space between the two first gate stacks 110a is smaller than the space between the two second gate stacks 110 b. Each first gate stack 110a includes a first floating gate 112a, a gate dielectric layer 114, a control gate layer 116, a conductive metal layer 118, and a cap layer 122, which are stacked in sequence from bottom to top. Each second gate stack 110b includes a second floating gate 112b, a gate dielectric layer 114, a control gate layer 116, a conductive metal layer 118, and a cap layer 122, which are stacked in sequence from bottom to top.

Referring to fig. 3C, a passivation layer 132 is conformally formed to cover the first gate stack 110a, the second gate stack 110b and the substrate 102 to form a plurality of first gate structures 120a and a plurality of second gate structures 120b on the substrate 102. The two first gate structures 120a have a first spacing S1 therebetween, and the two second gate structures 120b have a second spacing S2 therebetween. The second spacing S2 is greater than the first spacing S1. The first gate structure 120a has a first width W1 and the second gate structure 120b has a second width W2. The first width W1 is greater than the second width W2.

Referring to fig. 3D, a gap filling dielectric layer 134 is formed to cover the substrate 102 and fill the gap between the first gate structure 120a and the second gate structure 120b. Next, a planarization process may be performed on the gap-fill dielectric layer 134 as needed. The material of gap-fill dielectric layer 134 may include an oxide. In this embodiment, the gap-fill dielectric layer 134 is spin-on glass.

Then, an etching process is performed to the gap-fill dielectric layer 134 and the passivation layer 132 to form a contact hole exposing the substrate 102. The contact holes are located between adjacent gate structures. Next, a conductive material is filled into the contact hole, and a planarization process is performed on the conductive material to form a contact structure 142 in the gap-fill dielectric layer 134. Thereafter, other prior art manufacturing processes may be performed to complete the non-volatile memory device 500, which will not be described in detail herein. The contact structure 142 may be used to electrically connect the source or drain of the substrate 102 to subsequently formed bit lines and external circuitry. In some embodiments, the contact structure 142 includes a liner layer conformally formed on a surface of the contact hole and a conductive layer formed on the liner layer and filling the contact hole. The conductive layer comprises tungsten, aluminum, copper, other suitable metals, or combinations thereof. The liner layer may improve adhesion of the conductive layer to the substrate 102 or the gap-fill dielectric layer 134 and may prevent metal atoms from diffusing into the substrate 102 or the gap-fill dielectric layer 134. The material of the liner may include titanium, titanium nitride, tungsten nitride, tantalum or tantalum nitride, other suitable conductive materials, or combinations thereof.

In an embodiment, the height H2 of the second gate structure 120b located in the edge region 20 is higher than the height H1 of the first gate structure 120a located in the central region 10. More specifically, the thickness T2 of the floating gate layer 112b is greater than the thickness T1 of the floating gate layer 112 a.

By performing a chemical mechanical polishing process on the floating gate layer 112, dishing (dishing) of the floating gate material in the central region 10 in each array region 100 can be facilitated such that the thickness T1 of one floating gate layer 112a located in the central region 10 is less than the thickness T2 of one floating gate layer 112b located in the edge region 20. By configuring the first width W1 of the first gate structure 120a to be greater than the second width W2 of the second gate structure 120b, the size (volume) of the floating gate layer 112a can be compensated such that the size difference between the floating gate layer 112a and the floating gate layer 112b is reduced.

When an operating voltage is applied to the gate structure, electrons are injected and stored in the floating gate layer. The number of electrons that a floating gate layer can hold is proportional to its size. Furthermore, the number of electrons that can be stored by the floating gate layer decreases with time of use or environmental conditions (e.g., high temperature). If the size of the floating gate layer is smaller, the number of electrons that the floating gate layer can hold is smaller and the durability of the floating gate layer is also poorer. In addition, when the volume of the floating gate layer is large, the time required for programming and erasing is long. Therefore, by configuring the first width W1 of the first gate structure 120a to be greater than the second width W2 of the second gate structure 120b, the data storage capability of the first gate structure 120a can be compensated, and the operation speed of the second gate structure 120b can be increased, so that a plurality of memory cells of the memory device have similar data storage capability and operation speed.

In addition, since the height H2 of the second gate structure 120b located in the edge region 20 is greater than the height H1 of the first gate structure 120a located in the central region 10, the contact hole located in the edge region 20 will have a higher aspect ratio. When the contact hole has a high aspect ratio, the contact area between the contact structure 142 and the substrate 102 is easily reduced, so that the contact structure 142 in the edge region 20 has a high contact resistance. The number of electrons that can be injected (or removed) during one application of the operating voltage depends on the contact resistance of the contact structure 142. If the contact resistance of the contact structure 142 is high, the number of electrons that can be injected (or removed) during one application of the operating voltage is also low. Furthermore, the contact hole in the edge region 20 is more likely to fail to expose the substrate, thereby resulting in failure of the second gate structure 120b. By making the second spacing S2 between the second gate structures 120b greater than the first spacing S1 between the first gate structures 120a, the margin for manufacturing the contact holes in the edge region 20 can be increased, and the contact resistance of the contact structure 142 in the edge region 20 can be further compensated, so that the contact resistance of the center region 10 and the contact structure 142 in the edge region 20 are similar.

According to the method for manufacturing the nonvolatile memory device 500 of the present embodiment, the volumes of the floating gate layers in the central region 10 and the edge region 20 can be the same or similar, so that the yield, reliability and durability of the memory device can be improved without significantly increasing the complexity of the manufacturing process and the production cost.

In more detail, referring to fig. 3A, after performing a planarization process on the floating gate material, a first thickness T1 of the floating gate layer in the central region 10 and a second thickness T2 of the floating gate layer in the edge region 20 are measured, and a first width W1 and a second width W2 are determined according to the first thickness T1 and the second thickness T2, respectively. More specifically, the product of the thickness and the width of the floating gates is made equal to or similar to each other. That is, the product (T1 x W1) of the first thickness T1 and the first width W1 is equal to the product (T2 x W2) of the second thickness T2 and the second width W2. Accordingly, the floating gate layers of the center region 10 and the edge region 20 are made equal or similar in size to each other.

In some embodiments, the first width W1 plus the first spacing S1 is equal to the second width W2 plus the second spacing S2. The difference between the first width W1 and the second width W2 divided by the first width W1 (i.e., (W1-W2)/W1) is 0.5% to 25.0%. In contrast, the difference between the second spacing S2 and the first spacing S1 divided by the second spacing S2 (i.e., (S2-S1)/S2) is 0.5% to 25.0%.

Referring to fig. 1, fig. 3C, and fig. 3D, the nonvolatile memory device 500 includes a substrate 102, a plurality of first gate structures 120a, and a plurality of second gate structures 120b. The substrate 102 includes a central region 10 and two edge regions 20 located in the array region 100. The edge region 20 is located outside the central region 10. The first gate structure 120a is located in the central region 10 and the second gate structure 120b is located in the edge region 20. The first gate structure 120a has a first width W1 and a first height H1, and the second gate structure 120b has a second width W2 and a second height H2. The first width W1 is greater than the second width W2. The first height H1 is less than the second height H2. The first gate structures 120a have a first spacing S1 therebetween, the second gate structures 120b have a second spacing S2 therebetween, and the first spacing S1 is smaller than the second spacing S2.

The first gate structure 120a includes a first floating gate 112a and the second gate structure 120b includes a second floating gate 112b. The first floating gate 112a has a first thickness T1, the second floating gate 112b has a second thickness T2, and the first thickness T1 is less than the second thickness T2. In one embodiment, the ratio of the product of the first thickness T1 and the first width W1 (T1×w1) to the product of the second thickness T2 and the second width W2 (T2×w2) is 0.95-1.05, such that the volume of the first floating gate 112a is equal to or similar to the volume of the second floating gate 112b. In this way, endurance, reliability and operation uniformity of the memory device may be improved.

Fig. 4 is a schematic top view of an array region 100' according to other embodiments of the present invention. FIG. 5 is a schematic cross-sectional view of an array region 100' according to other embodiments of the present invention. Fig. 4 and 5 are similar to fig. 2 and 3A, respectively. In fig. 4 and 5, elements identical to those shown in fig. 2 and 3A are denoted by the same reference numerals. For simplicity of illustration, the same elements and the process steps for forming the same are shown in fig. 2 and 3A and will not be described in detail herein.

The array region 100' depicted in fig. 4 is similar to the array region 100 depicted in fig. 2. In the array region 100', the substrate 102 further includes two intermediate regions 30 respectively located between the central region 10 and one of the edge regions 20, and the intermediate regions 30 are symmetrical to each other with a center line passing through a center point of the central region 10. Referring to fig. 4 and fig. 5, in the present embodiment, a plurality of third gate structures 120c are formed on the substrate 102 and located in the middle region 30. In this embodiment, the floating gate layer 112, the gate dielectric layer 114, the control gate layer 116 and the conductive metal layer 118 may be patterned according to the cap layer 122 to form the first gate stacks 110a, the second gate stacks 110b and the third gate structures 120c on the substrate 102 simultaneously in the same step.

In the present embodiment, after the planarization process is performed on the floating gate layer 112, the thicknesses of the floating gate layer 112 in the central region 10, the edge region 20 and the middle region 30 are measured respectively. Referring to fig. 5, the first floating gate 112a located in the central region 10 has a first thickness T1; the second floating gate 112b at the edge region 20 has a second thickness T2; and the third floating gate 112c at the intermediate region 30 has a third thickness T3. The first gate structure 120a located in the central region 10 has a first width W1 and a first height H1; the second gate structure 120b located in the edge region 20 has a second width W2 and a second height H2; and the third gate structure 120c in the middle region 30 has a third width W3 and a third height H3. The two first gate structures 120a have a first spacing S1 therebetween; the two second gate structures 120b have a second spacing S2 therebetween; and a third spacing S3 is provided between the two third gate structures 120 c. In the present embodiment, the third thickness T3 is greater than the first thickness T1 and less than the second thickness T2. The third width W3 is smaller than the first width W1 and larger than the second width W2. The third height H3 is greater than the first height H1 and less than the second height H2. In other words, in the present embodiment, as the position of the gate structure is closer to the center of the array region, the thickness of the floating gate of the gate structure is smaller, and the width of the gate structure is larger.

In the present embodiment, the first width W1, the second width W2 and the third width W3 can be determined according to the first thickness T1, the second thickness T2 and the third thickness T3, respectively. More specifically, the product of the thickness and the width of the floating gates is made equal to or similar to each other. In one embodiment, the ratio of the product (T1 x W1) of the first thickness T1 and the first width W1 to the product (T2 x W2) of the second thickness T2 and the second width W2 is 0.95-1.05, and the ratio of the product (T1 x W1) of the first thickness T1 and the first width W1 to the product (T3 x W3) of the third thickness T3 and the third width W3 is 0.95-1.05. In this way, endurance, reliability and operation uniformity of the memory device can be significantly improved.

In some embodiments, the first width W1 plus the first spacing S1 is equal to the second width W2 plus the second spacing S2 is equal to the third width W3 plus the third spacing S3. The difference between the first width W1 and the third width W3 divided by the first width W1 (i.e., (W1-W3)/W1) is 1.0% to 24.0%.

It should be understood that the array regions 100 and 100' depicted in fig. 3C and 5 are for illustration only and are not intended to limit the present invention. The technical concepts disclosed in the embodiments of the present specification can be arbitrarily modified or combined by those skilled in the art to which the present invention pertains. For example, when the substrate 102 is viewed from the top view direction, the array region 100 may include a central region 10, two edge regions 20, and a plurality of middle regions 30, and both sides of the array region 100 are symmetrical to each other with a center line passing through a center point of the central region 10. A plurality of intermediate regions 30 may be included between the central region 10 and the edge regions 20. In other words, in other embodiments, the array region 100 may be divided into multiple regions. In such embodiments, the width of the gate structure in each region may be determined based on the thickness of the floating gate layer in that region such that the product of the thickness and width of the floating gate in those regions is equal or similar to each other.

In summary, according to the nonvolatile memory device and the manufacturing method provided by the embodiments of the invention, the floating gates of the gate structures of the array region have the same or similar dimensions, and the spacing between the gate structures in the edge region of the array region is greater than the spacing between the gate structures in the central region of the array region. Therefore, the operation consistency of the memory device can be obviously improved, and the problem of failure of the memory device can be reduced or avoided. Thus, the yield, reliability and durability of the memory device can be greatly improved. Furthermore, according to the method for manufacturing the nonvolatile memory device provided by the embodiment of the invention, the gate structures with different widths can be formed in different areas only by changing the pattern of the photomask. Therefore, such a manufacturing method can be easily integrated into an existing manufacturing process without additional replacement or modification of production equipment. Thus, the complexity of the manufacturing process and the production cost are not obviously increased.

Although the present invention has been described with respect to several preferred embodiments, it should be understood by those skilled in the art that the present invention is not limited thereto, and that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims (13)

1. A non-volatile memory device, comprising:

a substrate including a central region located in an array region and two edge regions located on opposite sides outside the central region; and

A plurality of memory cells constituting the array region, the plurality of memory cells including:

a plurality of first gate structures formed on the substrate and located in the central region, each of the first gate structures having a first width and a first pitch therebetween; and

and a plurality of second gate structures formed on the substrate and located in one of the edge regions, each of the second gate structures having a second width smaller than the first width and having a second spacing therebetween larger than the first spacing, wherein each of the first gate structures includes a first floating gate having a first thickness, each of the second gate structures includes a second floating gate having a second thickness, and the first thickness is smaller than the second thickness.

2. The non-volatile memory device of claim 1, wherein each of the first gate structures has a first height and each of the second gate structures has a second height greater than the first height.

3. The non-volatile memory device of claim 1, wherein a ratio of a product of the first thickness and the first width to a product of the second thickness and the second width is 0.95-1.05.

4. The non-volatile memory device of claim 1, wherein the first width plus the first pitch is equal to the second width plus the second pitch, and wherein a difference between the first width and the second width divided by the first width is 0.5% -25.0%.

5. The non-volatile memory device of claim 1, wherein the plurality of first gate structures are parallel to each other and extend along a first direction, the plurality of second gate structures are parallel to each other and extend along the first direction, and long axes of the plurality of edge regions extend along the first direction.

6. The non-volatile memory device of claim 2, wherein the substrate further comprises two intermediate regions, wherein each of the intermediate regions is located between the central region and one of the plurality of edge regions, and the non-volatile memory device further comprises:

and a plurality of third gate structures formed on the substrate and located in one of the plurality of intermediate regions, wherein each of the third gate structures has a third width smaller than the first width and larger than the second width, and a third pitch larger than the first pitch and smaller than the second pitch is provided between the plurality of third gate structures.

7. The non-volatile memory device of claim 6, wherein each of the third gate structures has a third height greater than the first height and less than the second height.

8. A method of manufacturing a nonvolatile memory device, comprising:

defining a central region of an array region on a substrate, and two edge regions positioned at two opposite sides outside the central region; and

Forming a plurality of memory cells constituting the array region, comprising:

forming a plurality of first gate structures in the central region on the substrate, wherein each first gate structure has a first width and a first interval is formed between the plurality of first gate structures; and

forming a plurality of second gate structures in one of the plurality of edge regions on the substrate, each of the second gate structures having a second width smaller than the first width and having a second spacing therebetween that is greater than the first spacing, and wherein forming the first gate structures and the second gate structures comprises:

forming a floating gate material on the substrate;

a planarization process is performed on the floating gate material to form a floating gate layer, wherein the floating gate layer has a first thickness in the central region and a second thickness greater than the first thickness in each of the edge regions.

9. The method of manufacturing a nonvolatile memory device of claim 8, wherein the plurality of first gate structures and the plurality of second gate structures are formed simultaneously in a same step, wherein forming the plurality of first gate structures and the plurality of second gate structures comprises:

conformally forming a gate dielectric layer over the floating gate layer;

conformally forming a control gate layer on the gate dielectric layer; and

and performing a patterning manufacturing process on the floating gate layer, the gate dielectric layer and the control gate layer to form the first gate structures and the second gate structures.

10. The method of manufacturing a nonvolatile memory device according to claim 9, further comprising:

measuring the first thickness and the second thickness after the planarization process; and

and determining the first width and the second width according to the first thickness and the second thickness respectively.

11. The method of manufacturing a nonvolatile memory device according to claim 10, wherein a ratio of a product of the first thickness and the first width to a product of the second thickness and the second width is 0.95 to 1.05.

12. The method of manufacturing a nonvolatile memory device of claim 9, wherein defining the center region and the plurality of edge regions in the substrate further comprises defining two intermediate regions in the substrate, wherein each of the intermediate regions is located between the center region and one of the plurality of edge regions, and the method of manufacturing a nonvolatile memory device further comprises:

forming a plurality of third gate structures on the substrate and in one of the plurality of intermediate regions, wherein the plurality of first gate structures and the plurality of third gate structures are formed simultaneously in a same step, wherein each of the third gate structures has a third width smaller than the first width and larger than the second width, and the plurality of third gate structures have a third pitch therebetween that is larger than the first pitch and smaller than the second pitch,

wherein, after the planarization process, the floating gate layer has a third thickness in each of the intermediate regions that is greater than the first thickness and less than the second thickness.

13. The method of manufacturing a nonvolatile memory device according to claim 12, further comprising:

measuring the first thickness, the second thickness and the third thickness respectively after the planarization manufacturing process; and

and determining the first width, the second width and the third width according to the first thickness, the second thickness and the third thickness respectively, wherein the ratio of the product of the first thickness and the first width to the product of the second thickness and the second width is 0.95-1.05, and the ratio of the product of the first thickness and the first width to the product of the third thickness and the third width is 0.95-1.05.