CN113466649B - A method for judging failure causes of SiC MOSFETs in surge current testing - Google Patents

Abstract

The invention discloses a method for judging the failure cause of a SiC MOSFET in a surge current test. In high-power converters such as motor drivers and grid-connected systems, the SiC power MOSFET and its body diode may be impacted by large surge currents. It is necessary to study the inrush current capability and inrush current reliability of SiC power MOSFETs and determine the cause of their failure. The judgment of the failure cause of SiC MOSFET in the surge current test is mainly based on the failure observation after the device is unsealed, and there is a lack of judgment methods related to electrical performance. The invention proposes a judgment method related to electrical performance for the possible failure reasons of SiC MOSFET in the positive gate bias surge current test, which can judge the SiC MOSFET according to the change law of the surge voltage waveform in the surge current test. The failure cause of the device is verified by comparing the maximum inrush current capability, which avoids the decapsulation and observation of the device, reduces the workload, is conducive to understanding the failure process of the device, and supplements the reliability research of SiC MOSFET.

Description

A method for judging failure causes of SiC MOSFETs in surge current testing

technical field

The invention belongs to the field of SiC power semiconductor devices, and particularly relates to a method for judging the failure cause of a SiC MOSFET in a surge current test.

Background technique

Compared with the semiconductor Si material, the wide band gap semiconductor SiC has a larger forbidden band width (3 times that of Si), higher thermal conductivity (3 times that of Si), high critical breakdown field strength (10 times that of Si), Higher electron saturation velocity (2 times that of Si) and other more excellent material properties, its temperature resistance, radiation resistance, heat dissipation, pressure resistance are stronger, and the applicable frequency is higher, which is widely used in high power density and high conversion efficiency. in the power electronic system. In power electronic applications, if the parasitic anti-parasitic PIN body diode inside the SiC MOSFET is directly used instead of adding an additional anti-parallel SiC SBD, the chip cost and the size of the power assembly module can be greatly reduced, and the EMI characteristics of the system can be improved.

In high-power converters such as motor drives and grid-connected systems, SiC power MOSFETs and their body diodes may be impacted by large inrush currents. It is necessary to study the inrush current capability and inrush current reliability of SiC power MOSFETs and judge their Reason for failure.

The possible failure causes of SiC MOSFETs in the surge current test can be summarized as gate oxide failure and package failure caused by aluminum melting. However, the current research on the failure causes of SiC MOSFETs in surge current testing mainly focuses on package failure. There are few reports on the failure of the gate oxide layer of SiC MOSFET in the surge current test. The judgment of the failure cause is mainly based on the failure observation after the device is unsealed, and there is a lack of judgment methods related to electrical performance.

SUMMARY OF THE INVENTION

The invention proposes a judgment method related to electrical performance for the possible failure causes of the SiC MOSFET in the positive gate bias surge current test. The invention can judge the failure cause of the SiC MOSFET according to the change law of the surge voltage waveform in the surge current test, and can verify the failure cause of the device by comparing the maximum surge current capability, avoiding the unpacking and observation of the device and reducing the workload. , which is beneficial to understand the failure process of the device and complements the reliability research of SiC MOSFETs.

To achieve the above object, the present invention provides the following technical solutions:

1. The gate voltage _VGS is set to a fixed value within 15 to 20V, and a surge current is applied to the SiC MOSFET from the source to the drain, and the corresponding surge voltage waveform is recorded. Gradually increase the peak value of the surge current for testing, and record the surge voltage waveform during each test until the device fails. The peak surge current when the device fails is defined as the maximum surge current capability of the device, and the maximum surge current capability of the device is recorded.

2. Analyze the change of the surge voltage waveform during the positive gate bias surge current test. If the surge voltage waveform has obvious peak voltage before the device fails, and the position of the peak voltage gradually turns to the upper left as the surge test progresses If the side moves, it is judged that the package fails due to the melting of aluminum;

3. Analyze the surge voltage waveform changes during the positive gate bias surge current test. If there is no peak voltage in the surge voltage waveform before the device fails, it is judged that the device fails due to gate oxide breakdown.

4. The gate voltage _VGS is set to a fixed value within -5 to -1V, and the surge current test is performed on the same type of SiC MOSFET until the device fails, and the maximum surge current capability of the device is recorded.

5. Compare the maximum surge current capability of the device in the positive gate bias surge current test and the negative gate bias surge current test to verify the judgment of the failure cause of the device. According to existing research, SiC MOSFETs experience package failure due to aluminum melting during negative gate bias testing. If the maximum surge current capability of the device in the positive gate bias surge current test is similar to that in the negative gate bias surge current test (not more than 10%), it is verified that the device in the positive gate bias surge current test is due to melting of aluminum. The package failure occurs; if the maximum surge current capability of the device in the positive gate bias surge current test is significantly smaller than that in the negative gate bias surge current test (more than 10%), it is verified that the positive gate bias surge current test The device fails prematurely due to gate oxide breakdown.

The advantages of the present invention are that: the present invention can judge the failure cause of the SiC MOSFET according to the change rule of the surge voltage waveform in the surge current test, avoid the decapsulation and observation of the device, reduce the workload, and help to understand the device The failure process complements the reliability studies of SiC MOSFETs.

Description of drawings

Figure 1 is a schematic diagram of the surge current test circuit.

Figure 2 is a schematic diagram of inrush current.

Figure 3 shows the change of the surge voltage waveform of the Class A device in the positive gate bias surge current test.

Figure 4 shows the surge voltage waveform change of the B-type device in the positive gate bias surge current test.

Detailed ways

The present invention is a method for judging the failure cause of a SiC MOSFET in a surge current test. The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Embodiments include the following steps:

1) FIG. 1 is a schematic diagram of the surge current test circuit used in the present invention. The circuit is based on the LC oscillation method. The LC resonance circuit composed of capacitors and inductors in FIG. 1 can generate surge current. The surge current generated by the above circuit is shown in Figure 2, which is a positive half-cycle sinusoidal current pulse with a pulse width of 10ms. The peak value of the surge current pulse can be adjusted by the DC voltage V _DC .

2) In this example, SiC MOSFET commercial devices from two manufacturers are selected, which are numbered as A-type devices and B-type devices respectively. The gate voltage _VGS was set to 20V, and a surge current was applied to the SiC MOSFET from the source to the drain, and the corresponding surge voltage waveform was recorded. Gradually increase the peak surge current for testing until the device fails,

3) Record the surge voltage waveform during each test. The maximum surge current capability of class A devices in the forward gate bias surge current test is 85A, and the maximum surge current capability of class B devices in the forward gate bias surge current test is 64A.

4) Figure 3 shows the change of the surge voltage waveform of the Class A device in the positive gate bias surge current test. Before the device fails, the surge voltage waveform has obvious peak voltage, and the position of the peak voltage follows the surge test. Gradually moving to the upper left, the surge voltage waveform is less symmetrical. This peak voltage corresponds to the turn-on voltage of the body diode when the gate is biased forward. When the surge voltage value exceeds the turn-on voltage of the body diode, the body diode is also turned on on the basis of the reverse channel conduction, and the final device occurs due to the melting of aluminum. Figure 4 shows the surge voltage waveform change of the B-type device in the positive gate bias surge current test. Before the device fails, there is no peak voltage, and the surge voltage waveform is symmetrical. The reverse channel of the device is turned on, the body diode is never turned on, and eventually the device fails due to gate oxide breakdown.

5) The gate voltage V _GS is set to -5V, and the surge current test is performed on the A and B devices respectively until the device fails, and the maximum surge current capability of the device is recorded. The maximum surge current capability of class A devices in the negative gate bias surge current test is 86A, and the maximum surge current capability of class B devices in the positive gate bias surge current test is 100A. The maximum surge current capability of Class A devices in the positive gate bias surge current test is similar to that in the negative gate bias surge current test (no more than 10%), which verifies that the Class A devices in the positive gate bias surge current test The package failure also occurs due to melting of aluminum; the maximum surge current capability of class B devices in the positive gate bias surge current test is significantly smaller than that in the negative gate bias surge current test (more than 10%), verifying that the class B devices Early failure due to gate oxide breakdown in positive gate bias surge current testing.

The above preferred examples are only used to illustrate the technical solutions of the invention and not limit it. Although the present invention has been described in detail through the above preferred examples, those skilled in the art should understand that various changes in form and details can be made. Such changes can be made without departing from the scope of the invention as defined by the claims.

To sum up, the present invention can judge the failure cause of the SiC MOSFET according to the change rule of the surge voltage waveform in the surge current test, and can verify the failure cause of the device by comparing the maximum surge current capability, avoiding the unpacking and observation of the device. The workload is reduced, it is beneficial to understand the failure process of the device, and it supplements the reliability research of SiC MOSFET.

Claims (2)

1. A method for judging failure reasons of a SiC MOSFET in surge current test is characterized in that the failure reasons of a device are judged according to a surge voltage waveform, and the method comprises the following steps:

1) Gate voltage V _GS Applying surge current to the SiC MOSFET from a source electrode to a drain electrode, recording corresponding surge voltage waveform, gradually increasing the surge current peak value for testing, recording the surge voltage waveform in each testing process until the device fails, defining the surge current peak value when the device fails as the maximum surge current capacity of the device, and recording the maximum surge current capacity of the device;

2) Analyzing the change of a surge voltage waveform in the positive gate bias surge current testing process, and judging that the device is subjected to packaging failure due to aluminum melting if the surge voltage waveform has obvious peak voltage before the device fails and the position of the peak voltage gradually moves to the upper left along with the surge test;

3) Analyzing the change of a surge voltage waveform in the positive gate bias surge current testing process, and judging that the device fails due to gate oxide breakdown if the surge voltage waveform does not have peak voltage before the device fails;

4) Gate voltage V _GS Setting the voltage to a certain fixed value within-5 to-1V, carrying out surge current test on SiC MOSFETs of the same type until the device fails, recording the maximum surge current capability of the device, and carrying out surge current test on the SiC MOSFETs of the same type until the device failsVerifying the judgment of the failure reason of the device according to the maximum surge current capability of the device in the positive gate bias surge current test and the negative gate bias surge current test;

5) If the maximum surge current capability of the device in the positive gate bias surge current test is close to that in the negative gate bias surge current test and is not more than 10 percent compared with the situation in the negative gate bias surge current test, the SiC MOSFET verifies that the device in the positive gate bias surge current test has packaging failure due to aluminum melting; if the maximum surge current capability of the device in the positive gate bias surge current test is obviously smaller than that in the negative gate bias surge current test and exceeds 10 percent, the device in the positive gate bias surge current test fails in advance due to gate oxide breakdown.

2. The method for judging the failure reason of the SiC MOSFET in the surge current test as claimed in claim 1, wherein the gate voltage V in the step 1) _GS Set at 15-20V.

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