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CN113496960A - Package and packaging method - Google Patents

Package and packaging method Download PDF

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Publication number
CN113496960A
CN113496960A CN202010250034.1A CN202010250034A CN113496960A CN 113496960 A CN113496960 A CN 113496960A CN 202010250034 A CN202010250034 A CN 202010250034A CN 113496960 A CN113496960 A CN 113496960A
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China
Prior art keywords
chip
lead frame
metal layer
layer
patterned
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Pending
Application number
CN202010250034.1A
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Chinese (zh)
Inventor
阳小芮
董美丹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
DIODES TECHNOLOGY (CHENGDU) CO LTD
Shanghai KaiHong Technology Co Ltd
Diodes Shanghai Co Ltd
Original Assignee
DIODES TECHNOLOGY (CHENGDU) CO LTD
Shanghai KaiHong Technology Co Ltd
Diodes Shanghai Co Ltd
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Priority to CN202010250034.1A priority Critical patent/CN113496960A/en
Publication of CN113496960A publication Critical patent/CN113496960A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H01L23/49527—Additional leads the additional leads being a multilayer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

一种封装体及封装方法，通过在封装过程中直接形成图案化导电层，以解决小尺寸导电层因模具设计的限制或导电层自身机械结构的限制而无法制作的问题，从而彻底目前因导电层过小而无法使用导电层设计的问题，大大简化了因导电层过小而只能使用密排焊线的封装体的作业能效。

Figure 202010250034

A package body and a packaging method, by directly forming a patterned conductive layer in the packaging process, to solve the problem that the small-sized conductive layer cannot be fabricated due to the limitation of mold design or the limitation of the mechanical structure of the conductive layer itself, thereby completely eliminating the current problem of conductive layers. The problem that the layer is too small to use the conductive layer design greatly simplifies the operating energy efficiency of the package that can only use densely packed wires because the conductive layer is too small.

Figure 202010250034

Description

Package and packaging method
Technical Field
The present invention relates to the field of semiconductor packaging, and more particularly, to a package and a packaging method.
Background
The packaged product is usually formed by mounting a chip on a lead frame and encapsulating the chip with a molding compound.
Currently, in view of cost, efficiency, electrical parameters, heat dissipation, high frequency parameters, etc., there is a package body that replaces the traditional wire bonding process with a conductive sheet (or conductive layer), especially a copper sheet welding process. Copper sheets are typically formed and cut using a copper sheet die and then attached to the chip and lead frame using additional processes. However, as the functions of the chip are improved, the design of the copper sheets becomes more and more complex, so that the design size of the copper sheets and the space between the copper sheets become smaller and smaller.
However, due to the design and manufacturing limitations of the mold, some small-sized copper sheets or designs with small copper sheet pitches are difficult to manufacture due to the limitations of the mechanical structure, and thus the copper sheets cannot be manufactured.
Therefore, the existing process technology causes that some packages have to use large-area densely-arranged bonding wires to replace the copper sheets because the formation of the copper sheets can not be realized actually, thereby not only reducing the operation energy efficiency, but also influencing the product performance.
Therefore, there is a need to provide a new packaging method and a package obtained by applying the new packaging method to overcome the above-mentioned drawbacks.
Disclosure of Invention
The invention aims to provide a packaging body and a packaging method, wherein a patterned conductive layer is directly formed in the packaging process, so that the problem that a small-size conductive layer cannot be manufactured due to the limitation of mold design or the limitation of the mechanical structure of the conductive layer is solved, the problem that the design of the conductive layer cannot be used due to the fact that the conductive layer is too small at present is solved, and the operation energy efficiency of the packaging body which only can use closely-arranged bonding wires due to the fact that the conductive layer is too small is greatly simplified.
In order to achieve the above object, according to an aspect of the present invention, a package is provided, which includes a lead frame and a chip, wherein the lead frame includes a base island and a pin, the chip is disposed on the base island of the lead frame, and a bonding pad of the chip is electrically connected to the pin of the lead frame through a metal sheet.
In an embodiment of the invention, the metal sheet is electrically connected to the bonding pad of the chip through solder paste.
In an embodiment of the present invention, the metal sheet is attached to a surface of the chip away from the base island.
In an embodiment of the invention, the metal sheet is made of copper.
According to another aspect of the present invention, there is provided a packaging method including: providing a lead frame, and mounting a chip on the lead frame; packaging the chip for the first time; a step of forming a patterned metal layer;
and, a second encapsulation step; in the step of forming the patterned metal layer, a metal sheet is formed to electrically connect the bonding pad of the chip and the lead of the lead frame.
In an embodiment of the present invention, in the step of performing the first packaging on the chip, the chip and the lead frame are packaged by a molding compound, and at least the bonding pad of the chip and the lead of the lead frame are exposed.
As can be understood by those skilled in the art, in an embodiment of the present invention, in the step of performing the first packaging on the chip, a plastic package mold is used, so that when the chip and the lead frame are packaged by the plastic package material, the bonding pad of the chip and the lead of the lead frame are exposed; or, in the step of packaging the chip for the first time, a plastic package mold is used, so that when the chip and the lead frame are packaged by the plastic package material, the surface (including the bonding pad) of the chip, which is far away from the base island, and the pins of the lead frame are fully exposed.
In an embodiment of the present invention, in the step of forming the patterned metal layer, a metal layer is first formed, so that the metal layer covers the chip and the lead area of the lead frame; and then, forming a patterned masking layer on the metal layer, and etching to obtain the patterned metal layer.
It will be appreciated by those skilled in the art that, in one embodiment of the present invention, the data may be obtained by: and forming a masking layer on the metal layer, and carrying out exposure and development to form the patterned masking layer on the metal layer.
Alternatively, in an embodiment of the present invention, in the step of forming the patterned metal layer, a patterned masking layer is first formed, such that the patterned masking layer covers the chip and the lead area of the lead frame; and then, forming a metal layer to fill the patterned masking layer, and removing the patterned masking layer to obtain the patterned metal layer. It will be appreciated by those skilled in the art that in this step, the patterned masking layer exposes at least the bonding pads of the chip and the leads of the lead frame.
In an embodiment of the invention, the material of the patterned masking layer is a photosensitive dry film or a photoresist material. It will be understood by those skilled in the art that the photosensitive dry film and the photoresist are commercially available as is conventional in the art.
In an embodiment of the present invention, before the step of forming the patterned metal layer, the packaging method further includes: a step of forming a solder paste such that the solder paste covers the exposed pads of the chip and the leads of the lead frame.
In a preferred embodiment of the present invention, a packaging method is provided, which comprises the following steps:
s10: providing a lead frame, and mounting a chip on the lead frame;
s20: packaging for the first time, namely, exposing a bonding pad of the chip and a pin of the lead frame when the chip and the lead frame are packaged by using a plastic package mold;
s30: forming a solder paste so that the solder paste covers the pads of the chip and the leads of the lead frame exposed in step S20;
s41: forming a metal layer covering the chip and the lead frame in the area, i.e., the metal layer covers and contacts the surface of the molding compound formed in the step S20 and the surface of the solder paste formed in the step S30; that is, in this step, the metal layer covers the region where the base island of the lead frame is located and the region where the pin is located;
s42: forming a patterned masking layer on the surface of the metal layer formed in step S41;
s43: etching to obtain a patterned metal layer, wherein the patterned metal layer is electrically connected with the bonding pad of the core and the pin of the lead frame through the solder paste;
s50: and packaging for the second time to package the lead frame, the chip and the patterned metal layer, and cutting and molding to obtain a packaging body.
In a preferred embodiment of the present invention, a packaging method is provided, which comprises the following steps:
s10: providing a lead frame, and mounting a chip on the lead frame;
s20: packaging for the first time, namely, exposing a bonding pad of the chip and a pin of the lead frame by using a plastic package mold when the chip and the lead frame are packaged by using a plastic package material;
s31: vacuum pasting a photosensitive dry film, so that the photosensitive dry film covers the chip and the lead area of the lead frame, that is, the photosensitive dry film covers and contacts the surface of the molding compound formed in the step S20 and the bonding pad of the chip exposed in the step S20;
s32: obtaining a patterned masking layer after exposure and development, so that the patterned masking layer at least exposes the bonding pad of the chip and the pin of the lead frame;
s40: forming a metal layer, filling the patterned masking layer with the metal layer, and removing the patterned masking layer to obtain the patterned metal layer, so that the patterned metal layer is electrically connected with the bonding pad of the core and the pins of the lead frame;
s50: and packaging for the second time to package the lead frame, the chip and the patterned metal layer, and cutting and molding to obtain a packaging body.
In a preferred embodiment of the present invention, a packaging method is provided, which comprises the following steps:
s10: providing a lead frame, and mounting a chip on the lead frame;
s20: packaging for the first time, namely, fully exposing the surface (including a bonding pad) of the chip departing from the base island and pins of the lead frame when the chip and the lead frame are packaged by using a plastic package mold;
s31: forming a metal layer, wherein the metal layer covers the chip and the lead area of the lead frame, namely, the metal layer covers and contacts the surface of the molding compound formed in the step S20, and the exposed surface (including the bonding pad) of the chip, which is far away from the base island, and the lead of the lead frame;
s32: forming a patterned masking layer on the surface of the metal layer formed in step S31;
s33: etching to obtain a patterned metal layer, wherein the patterned metal layer is attached to the surface of the chip, which is far away from the base island, and is electrically connected with the pins of the lead frame;
s40: and packaging for the second time to package the lead frame, the chip and the patterned metal layer, and cutting and molding to obtain a packaging body.
In the invention, the patterned conducting layer is directly formed in the packaging process, so that the forming step of an additional independent conducting layer is avoided, and the problem that the small-size conducting layer cannot be manufactured due to the limitation of the design of a mold or the limitation of the mechanical structure of the conducting layer is solved. The packaging body and the packaging method can solve the technical problem that the design of the conductive layer cannot be used due to the fact that the conductive layer is too small at present, and greatly simplify the operation energy efficiency of the packaging body which only can use closely-arranged bonding wires due to the fact that the conductive layer is too small.
Drawings
FIG. 1 is a flow diagram of a packaging method according to an embodiment of the invention; fig. 2A to 2H are schematic structural views of the package body corresponding to fig. 1;
FIG. 3 is a flow chart of a packaging method according to another embodiment of the invention; fig. 4A to 4E are schematic structural views of the package body corresponding to fig. 3;
FIG. 5 is a flow chart of a packaging method according to another embodiment of the invention; fig. 6A to 6G are schematic structural views of the package corresponding to fig. 5;
FIGS. 7A and 7B are schematic views of a part of the step structure of a packaging method according to another embodiment of the invention
Detailed Description
Hereinafter, the technique of the present invention will be described in detail with reference to specific embodiments. It should be understood that the following detailed description is only for the purpose of assisting those skilled in the art in understanding the present invention, and is not intended to limit the present invention.
Example one
In the present embodiment, a method for packaging a package and a package obtained by using the method are provided.
The packaging method in this embodiment is described in detail below with reference to fig. 1 and fig. 2A to 2H. In this embodiment, the packaging method includes the following steps:
step S10: as shown in fig. 1 and 2A, a lead frame 1 is provided, and a chip 2 is mounted on the lead frame 1. As shown in fig. 2A, the lead frame 1 includes a base island 11 and a lead 12. It will be understood by those skilled in the art that the lead frame 1 may include a plurality of frame units defined by a package line W, each of which includes the base island 11 and the leads 12. In fig. 2A, only one frame unit defined by the package line W is schematically shown. In this step, as shown in fig. 2A, the chip 2 is mounted on the lead frame 1, particularly on the base island 11 of the lead frame 1. It will be appreciated by those skilled in the art that the chip 2 may be mounted on the lead frame 1 in any manner known in the art, such as, but not limited to, by soldering or adhesive material to the lead frame 1. As shown in fig. 2A, the chip 2 includes a plurality of bonding pads 21, and the bonding pads 21 are electrically connected to the leads 12 of the lead frame 1 through a subsequently formed conductive layer.
Step S20: as shown in fig. 1 and 2B, a first packaging is further performed, and a plastic mold is used to expose the bonding pads 21 of the chip 2 and the leads 12 of the lead frame 1 when the chip 2 and the lead frame 1 are packaged by the plastic mold 3. It will be understood by those skilled in the art that the molding compound 3 may expose the bonding pads 21 of the chip 2 and portions of the chip 2, as well as portions of the leads 12 of the lead frame 1.
Step S30: as shown in fig. 1 and 2C, a solder paste layer 4 is further formed such that the solder paste layer 4 covers the pad 21 of the chip 2 and the portion of the lead 12 of the lead frame 1 exposed in the above step S20;
step S41: as shown in fig. 1 and 2D, a metal layer 5A is further formed, and the metal layer 5A covers the chip 2 and the lead 12 of the lead frame 1, that is, the metal layer 5A covers and contacts the surface of the molding compound 3 formed in the step S20 and the surface of the solder paste layer 4 formed in the step S30. That is, in this step, the metal layer 5A covers the region where the base island 11 and the lead 12 of the lead frame 1 are located, as shown in fig. 2D. It will be understood by those skilled in the art that, in this step, the coverage area of the metal layer 5A is not particularly limited, and at least covers the area where the conductive layer is finally formed. In order to simplify the manufacturing process, in the present embodiment, as shown in fig. 2D, the metal layer 5A covers substantially the entire area of the frame unit defined by the package line W.
Step S42: a patterned masking layer 6 is further formed on the surface of the metal layer 5A formed in the above step S41. As will be understood by those skilled in the art, in this step, as shown in fig. 2E, a masking layer 6A may be first formed on the metal layer 5A, the coverage of the masking layer 6A is the same as that of the metal layer 5A, and the material of the masking layer 6A is a photosensitive dry film or a photoresist material. The masking layer 6A is then patterned by exposure and development steps known in the art to form a patterned masking layer 6 as shown in fig. 2F on the metal layer 5A.
Step S43: after further etching and removing the patterned masking layer 6, the metal layer 5A shown in fig. 2D is patterned to finally obtain a patterned metal layer (i.e. the conductive layer 5), as shown in fig. 2G. Therefore, as shown in fig. 2A and 2G, the step obtains the conductive layers 5 electrically connected to the bonding pads (bonding pads 21 in fig. 2A) of the core 2 and the leads 12 of the lead frame 1 through the solder paste layers 4, respectively, and each bonding pad 21 is directly electrically connected to the corresponding lead 12 of the lead frame 1 through one conductive layer 5. The formed conductive layer 5 is a clip copper sheet which is used in the same traditional packaging body in the field and has heat dissipation performance and replaces wire bonding. It can be seen that, in the packaging method of the present embodiment, there is no need to form a clip copper sheet with an external shape structure as shown in fig. 2G in advance and mount the clip copper sheet in the package, but the clip copper sheet is directly formed in the packaging step of the package through an etching process. This allows the conductive layer 5 to be formed in the desired shape and size without being mechanically and dimensionally constrained by the clip copper sheet forming process. It will be appreciated by those skilled in the art that etching may be performed in this step in an etching method known in the art.
Step S50: and finally, performing secondary packaging to package the lead frame 1, the chip 2 and the conductive layer 5, and cutting and forming to obtain a packaging body. As shown in fig. 2H, in this step, the lead frame 1, the chip 2 and the conductive layer 5 are encapsulated by a molding compound 3, and a package 100 is obtained after cutting and molding.
As shown in fig. 2H, the package 100 manufactured by the packaging method according to the embodiment has a lead frame 1 and a chip 2, the lead frame 1 includes a base island 11 and a lead 12, and the chip 2 is disposed on the base island 11 of the lead frame 1. The chip 2 has a plurality of bonding pads 21 as shown in fig. 2A, each bonding pad 21 corresponds to one lead 12 of the lead frame 1, and each bonding pad 21 of the chip 2 is electrically connected to the corresponding lead 12 of the lead frame 1 through the solder paste layer 4 by one conductive layer 5 as shown in fig. 2H. That is, as shown in fig. 2H, a solder paste layer 4 is disposed between the conductive layer 5 and the corresponding pad 21 shown in fig. 2A, so as to achieve electrical connection.
Example two
In the embodiment, a packaging method of the package and a package obtained by using the packaging method are also provided. Unlike the first embodiment, the step of forming the solder paste layer described in the first embodiment is not included in the packaging method of the present embodiment.
The packaging method in this embodiment is described in detail below with reference to fig. 3 and 4A to 4E. In this embodiment, the packaging method includes the following steps:
step S10: as shown in fig. 3 and fig. 2A, a lead frame 1 is provided, and a chip 2 is mounted on the lead frame 1, as in the first embodiment. As shown in fig. 2A, the lead frame 1 includes a base island 11 and a lead 12. It will be understood by those skilled in the art that the lead frame 1 may include a plurality of frame units defined by a package line W, each of which includes the base island 11 and the leads 12. In fig. 2A, only one frame unit defined by the package line W is schematically shown. In this step, as shown in fig. 2A, the chip 2 is mounted on the lead frame 1, particularly on the base island 11 of the lead frame 1. It will be appreciated by those skilled in the art that the chip 2 may be mounted on the lead frame 1 in any manner known in the art, such as, but not limited to, by soldering or adhesive material to the lead frame 1. As shown in fig. 2A, the chip 2 includes a plurality of bonding pads 21, and the bonding pads 21 are electrically connected to the leads 12 of the lead frame 1 through a subsequently formed conductive layer.
Step S20: as shown in fig. 3 and fig. 2B, as in the first embodiment, a first packaging is further performed, and a plastic mold is used to expose the bonding pads 21 of the chip 2 and the leads 12 of the lead frame 1 when the chip 2 and the lead frame 1 are packaged by the plastic mold 3. It will be understood by those skilled in the art that the molding compound 3 may expose the bonding pads 21 of the chip 2 and portions of the chip 2, as well as portions of the leads 12 of the lead frame 1.
Step S41: as shown in fig. 3 and 4A, a metal layer 5A is further formed, where the metal layer 5A covers the chip 2 and the lead 12 of the lead frame 1, and contacts the pad 21 of the chip 2 and the lead 12 of the lead frame 1 exposed in step S20. That is, the metal layer 5A covers and contacts the surface of the molding compound 3 formed in the above step S20, and all exposed portions in the above step S20. That is, in this step, the metal layer 5A covers the region where the base island 11 and the lead 12 of the lead frame 1 are located, as shown in fig. 2D. It will be understood by those skilled in the art that, in this step, the coverage area of the metal layer 5A is not particularly limited, and at least covers the area where the conductive layer is finally formed. In order to simplify the manufacturing process, in the present embodiment, as shown in fig. 4A, the metal layer 5A covers substantially the entire area of the frame unit defined by the package line W.
Step S42: as in the first embodiment, a patterned masking layer 6 is further formed on the surface of the metal layer 5A formed in step S41. As will be understood by those skilled in the art, in this step, as shown in fig. 4B, a masking layer 6A may be first formed on the metal layer 5A, the coverage of the masking layer 6A is the same as that of the metal layer 5A, and the material of the masking layer 6A is a photosensitive dry film or a photoresist material. The masking layer 6A is then patterned by exposure and development steps known in the art to form a patterned masking layer 6 as shown in fig. 4C on the metal layer 5A.
Step S43: as in the first embodiment, after further etching and removing the patterned masking layer 6, the metal layer 5A shown in fig. 4C is patterned to finally obtain a patterned metal layer (i.e., the conductive layer 5), as shown in fig. 4D. Therefore, as shown in fig. 2A and 4D, the step obtains the conductive layers 5 directly electrically connected to the bonding pads (bonding pads 21 in fig. 2A) of the core 2 and the leads 12 of the lead frame 1, respectively, and each bonding pad 21 is directly electrically connected to the corresponding lead 12 of the lead frame 1 through one conductive layer 5.
Step S50: and finally, performing secondary packaging to package the lead frame 1, the chip 2 and the conductive layer 5, and cutting and forming to obtain a packaging body. As shown in fig. 4E, in this step, the lead frame 1, the chip 2 and the conductive layer 5 are encapsulated by a molding compound 3, and a package 200 is obtained after cutting and molding.
As shown in fig. 4E, the package 200 manufactured by the packaging method according to the embodiment has a lead frame 1 and a chip 2, the lead frame 1 includes a base island 11 and a lead 12, and the chip 2 is disposed on the base island 11 of the lead frame 1. The chip 2 has a plurality of bonding pads 21 as shown in fig. 2A, each bonding pad 21 corresponds to one lead 12 of the lead frame 1. Unlike the first embodiment, in the package 200 of the present embodiment, each pad 21 of the chip 2 is in direct contact with the corresponding lead 12 of the lead frame 1 through the conductive layer 5. That is, as shown in fig. 4E, each conductive layer 5 is in direct contact with the corresponding pad 21 shown in fig. 2A facing the surface of the pad 21; and, each conductive layer 5 faces the surface of the corresponding pin 12 and is in direct contact with the pin 12.
EXAMPLE III
In the embodiment, a packaging method of the package and a package obtained by using the packaging method are also provided. Different from the first embodiment or the second embodiment, in the packaging method of the present embodiment, a manner of obtaining the conductive layer is different.
Further, as shown in fig. 6A to 6F, in the present embodiment, a surface of the lead 12 of the lead frame 1 for contacting the conductive layer 5 (i.e., an upper surface of the lead 12 in fig. 6A to 6F) is higher than a surface of the base island 11 for contacting the chip 2 (i.e., an upper surface of the base island 11 in fig. 6A to 6F).
The packaging method in this embodiment is described in detail below with reference to fig. 5 and 6A to 6F. In this embodiment, the packaging method includes the following steps:
step S10: as shown in fig. 5 and 6A, a lead frame 1 is provided, and a chip 2 is mounted on the lead frame 1. As shown in fig. 6A, the lead frame 1 includes a base island 11 and a lead 12. It will be understood by those skilled in the art that the lead frame 1 may include a plurality of frame units defined by a package line W, each of which includes the base island 11 and the leads 12. In fig. 6A, only one frame unit defined by the packaging line W is schematically shown. In this step, as shown in fig. 6A, the chip 2 is mounted on the lead frame 1, particularly on the base island 11 of the lead frame 1. It will be appreciated by those skilled in the art that the chip 2 may be mounted on the lead frame 1 in any manner known in the art, such as, but not limited to, by soldering or adhesive material to the lead frame 1. As shown in fig. 6A, the chip 2 includes a plurality of bonding pads 21, and the bonding pads 21 are electrically connected to the leads 12 of the lead frame 1 through a subsequently formed conductive layer.
Step S20: as shown in fig. 5 and 6B, a first packaging is further performed, and a plastic mold is used to expose the bonding pads 21 of the chip 2 and the leads 12 of the lead frame 1 when the chip 2 and the lead frame 1 are packaged by the plastic mold 3. It will be understood by those skilled in the art that the molding compound 3 may expose the bonding pads 21 of the chip 2 and portions of the chip 2, as well as portions of the leads 12 of the lead frame 1. Alternatively, as shown in fig. 6B, the molding compound 3 exposes the chip 2.
Step S31: as shown in fig. 5 and 6C, a photosensitive dry film 6A is further attached in vacuum, so that the photosensitive dry film 6A covers the chip 2 and the region where the lead 12 of the lead frame 1 is located, that is, the photosensitive dry film 6A covers and contacts the surface of the molding compound 3 formed in step S20, and the chip 2 and the region where the lead 12 of the lead mine 1 is located, which are exposed in step S20. In order to simplify the manufacturing process, in the present embodiment, as shown in fig. 6C, the photosensitive dry film 6A covers substantially the entire area of the frame unit defined by the packaging line W.
Step S32: as shown in fig. 5 and 6D, a patterned masking layer 6 is obtained after exposure and development, so that the patterned masking layer 6 exposes at least the bonding pad 21 of the chip 2 and the lead 12 of the lead frame 1. It will be appreciated by those skilled in the art that the exposed portion of patterned masking layer 6 is the portion where conductive layer 5 is ultimately formed, as shown in fig. 6D.
Step S40: as shown in fig. 5 and fig. 6E, a metal layer 5A is further formed, and the metal layer 5A fills the patterned masking layer 6. After removing the patterned masking layer 6 by a method conventional in the art, a patterned metal layer as shown in fig. 6F, i.e. the conductive layer 5, can be obtained. Therefore, as shown in fig. 6A and 6F, the step obtains the conductive layers 5 respectively and directly electrically connected to the bonding pads (bonding pads 21 in fig. 6A) of the core 2 and the leads 12 of the lead frame 1, and each bonding pad 21 is directly contacted with the corresponding lead 12 of the lead frame 1 through one conductive layer 5. The formed conductive layer 5 is a clip copper sheet which is used in the same traditional packaging body in the field and has heat dissipation performance and replaces wire bonding. It can be seen that, in the packaging method of the present embodiment, there is no need to form a clip copper sheet with an external shape structure as shown in fig. 6F in advance and mount the clip copper sheet in the package, but the clip copper sheet is directly formed in the packaging step of the package through an etching process. This allows the conductive layer 5 to be formed in the desired shape and size without being mechanically and dimensionally constrained by the clip copper sheet forming process.
Step S50: as shown in fig. 5 and 6G, a second packaging is further performed to package the lead frame 1, the chip 2 and the conductive layer 5, and a package 300 is obtained after cutting and molding. As shown in fig. 6G, in this step, the lead frame 1, the chip 2 and the conductive layer 5 are encapsulated by a molding compound 3, and a package 300 is obtained after cutting and molding.
As shown in fig. 6G, the package 300 manufactured by the packaging method according to the embodiment has a lead frame 1 and a chip 2, the lead frame 1 includes a base island 11 and a lead 12, and the chip 2 is disposed on the base island 11 of the lead frame 1. The chip 2 has a plurality of bonding pads 21 as shown in fig. 6A, each bonding pad 21 corresponding to one lead 12 of the lead frame 1. Each pad 21 of the chip 2 is in direct contact with a corresponding lead 12 of the lead frame 1 through the conductive layer 5. That is, as shown in fig. 6F, each conductive layer 5 is in direct contact with the corresponding pad 21 shown in fig. 6A facing the surface of the pad 21; and, each conductive layer 5 faces the surface of the corresponding pin 12 and is in direct contact with the pin 12.
Example four
In the embodiment, a packaging method of the package and a package obtained by using the packaging method are also provided. Unlike the third embodiment, in the packaging method of the present embodiment, in the step S32 of forming a patterned masking layer 6, as shown in fig. 7A, the patterned masking layer 6 exposes only the bonding pad 21 of the chip 2 and the lead 12 of the lead frame 1. So that when the conductive layer 5 is finally formed, as shown in fig. 7B, a projection 51 is formed on the surface of the conductive layer 5 facing the corresponding pad 21 shown in fig. 7A so that the projection 51 is in direct contact with the pad 21.
In this embodiment, except for the step S32, the packaging method is the same as that of the third embodiment.
The present invention has been described in relation to the above embodiments, which are only exemplary of the implementation of the present invention. It must be noted that the disclosed embodiments do not limit the scope of the invention. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the invention.

Claims (11)

1.一种封装体，包括引线框架和芯片，其中，所述引线框架包括基岛和引脚，所述芯片设置于所述引线框架的所述基岛上，其特征在于，所述芯片包含复数个焊盘，每一焊盘对应一个所述引线框架的引脚，所述芯片的每一焊盘通过一个导电层与对应的所述引线框架的引脚直接电性连接。1. A package body, comprising a lead frame and a chip, wherein the lead frame comprises a base island and a pin, the chip is arranged on the base island of the lead frame, wherein the chip comprises A plurality of bonding pads, each bonding pad corresponds to a pin of the lead frame, and each bonding pad of the chip is directly and electrically connected to the corresponding pin of the lead frame through a conductive layer. 2.如权利要求1所述的封装体，其特征在于，每一导电层面朝对应的所述焊盘的表面与所述焊盘直接接触；并且，每一导电层面朝对应的所述引脚的表面与所述引脚直接接触。2 . The package according to claim 1 , wherein a surface of each conductive layer facing the corresponding pad is in direct contact with the pad; and each conductive layer faces the corresponding pin surface is in direct contact with the pins. 3.如权利要求1所述的封装体，其特征在于，每一导电层面朝对应的所述焊盘的表面上设置至少一个凸起，使得所述凸起与所述焊盘直接接触。3 . The package of claim 1 , wherein at least one protrusion is provided on the surface of each conductive layer facing the corresponding pad, so that the protrusion is in direct contact with the pad. 4 . 4.如权利要求1所述的封装体，其特征在于，所述导电层与对应的所述焊盘之间设置一锡膏层。4 . The package of claim 1 , wherein a solder paste layer is disposed between the conductive layer and the corresponding pad. 5 . 5.如权利要求1所述的封装体，其特征在于，所述引脚接触所述导电层的表面高于所述所述基岛接触所述芯片的表面。5 . The package according to claim 1 , wherein a surface of the pin contacting the conductive layer is higher than a surface of the base island contacting the chip. 6 . 6.一种封装方法，其特征在于，所述封装方法包括：6. An encapsulation method, characterized in that the encapsulation method comprises: 提供一引线框架，并在所述引线框架上贴装一芯片的步骤；providing a lead frame and mounting a chip on the lead frame; 所述芯片进行第一次封装的步骤；the step of first encapsulating the chip; 形成一图案化金属层的步骤；以及，the step of forming a patterned metal layer; and, 第二次封装的步骤；其中，the second encapsulation step; wherein, 所述芯片包含复数个焊盘，每一焊盘对应一个所述引线框架的引脚；并且，The chip includes a plurality of pads, and each pad corresponds to a pin of the lead frame; and, 在所述形成一图案化金属层的步骤中，获得的所述图案化金属层包含复数个导电层，每一所述导电层用于将一个焊盘与对应的一个引脚直接电性连接。In the step of forming a patterned metal layer, the obtained patterned metal layer includes a plurality of conductive layers, and each of the conductive layers is used to directly electrically connect a pad and a corresponding pin. 7.如权利要求5所述的封装方法，其特征在于，在所述芯片进行第一次封装的步骤中，以塑封料封装所述芯片及所述引线框架，并至少暴露所述芯片的焊盘以及所述引线框架的引脚的部分。7 . The packaging method according to claim 5 , wherein, in the step of packaging the chip for the first time, the chip and the lead frame are packaged with a plastic sealing compound, and at least the solder joints of the chip are exposed. 8 . part of the pad and the pins of the lead frame. 8.如权利要求6所述的封装方法，其特征在于，在所述形成一图案化金属层的步骤中，首先形成一金属层，使得所述金属层覆盖所述芯片及所述引线框架的引脚所在区域；然后，在所述金属层上形成一图案化掩蔽层，刻蚀后获得所述图案化金属层。8 . The packaging method according to claim 6 , wherein in the step of forming a patterned metal layer, a metal layer is first formed, so that the metal layer covers the chip and the lead frame. 9 . the area where the pins are located; then, a patterned masking layer is formed on the metal layer, and the patterned metal layer is obtained after etching. 9.如权利要求6所述的封装方法，其特征在于，在所述形成一图案化金属层的步骤中，首先形成一图案化掩蔽层，使得所述图案化掩蔽层覆盖所述芯片及所述引线框架的引脚所在区域；然后，形成一金属层以填充所述图案化掩蔽层，去除图案化掩蔽层后获得所述图案化金属层。9 . The packaging method according to claim 6 , wherein, in the step of forming a patterned metal layer, a patterned masking layer is firstly formed, so that the patterned masking layer covers the chip and the surrounding area. 10 . Then, a metal layer is formed to fill the patterned masking layer, and the patterned metal layer is obtained after removing the patterned masking layer. 10.如权利要求6或权利要求7所述的封装方法，其特征在于，所述图案化掩蔽层的材料为感光干膜或光阻材料。10 . The packaging method according to claim 6 or claim 7 , wherein the material of the patterned masking layer is a photosensitive dry film or a photoresist material. 11 . 11.如权利要求5所述的封装方法，其特征在于，所述封装方法在所述形成图案化金属层的步骤之前，还包括：形成锡膏的步骤，使得所述锡膏覆盖被暴露的所述芯片的焊盘以及所述引线框架的引脚。11 . The packaging method according to claim 5 , wherein, before the step of forming the patterned metal layer, the packaging method further comprises: the step of forming a solder paste, so that the solder paste covers the exposed 11 . The pads of the chip and the pins of the lead frame.
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CN101073151A (en) * 2004-12-20 2007-11-14 半导体元件工业有限责任公司 Semiconductor package structure with enhanced heat dissipation
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