CN113506802B - A direct bandgap GeSn CMOS device and its preparation method - Google Patents

Abstract

The invention discloses a direct band gap GeSn CMOS device, which comprises: the semiconductor device comprises a substrate layer, a Ge virtual substrate, a first P-type Ge layer, an isolation region, an N well, a second P-type Ge layer, an intrinsic Ge isolation layer, a channel layer, a first intrinsic ternary alloy heterogeneous cap layer, a PMOS gate, a PMOS source drain region, an N-type Ge layer, a second intrinsic ternary alloy heterogeneous cap layer, an NMOS gate, an NMOS source drain region, a dielectric layer, a source drain electrode and a passivation layer; the material of the first intrinsic ternary alloy heterogeneous cap layer is Si _xGe_{1‑x‑ y}Sn_y; wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07; the material of the second intrinsic ternary alloy heterogeneous cap layer is Si _xGe_1‑x‑ySn_y; wherein, the range of x is 0.1-0.15, and the range of y is 0.08-0.1; the channel layer is an intrinsic DR-Ge _1‑zSn_z layer; wherein z ranges from 0.12 to 0.18. According to the invention, the DR-GeSn CMOS structure formed by the single-side high barrier quantum confinement NMOS and the quantum well PMOS can be beneficial to starting the channel of the NMOS device, the materials of all layers of the whole device are the same, and the NMOS and PMOS structures have better process compatibility. The invention also provides a preparation method of the direct band gap GeSn CMOS device.

Description

A direct bandgap GeSn CMOS device and its preparation method

Technical Field

The invention belongs to the technical field of semiconductor integrated circuits, and in particular relates to a direct bandgap GeSn CMOS device and a preparation method thereof.

Background technique

The development of microelectronics technology has always followed Moore's Law, but as the feature size of Si MOS devices continues to shrink, it is becoming increasingly difficult to continue Moore's Law. In this context, a series of new technologies have emerged, such as strain technology, fin gate FinFet, SOI and other technologies. However, at present, even with the assistance of these new technologies, the feature size of Si MOS devices has almost reached its limit (the channel is only a few nanometers), and integrated circuits are gradually approaching their physical and process limits. Therefore, replacing Si materials and developing and adopting new MOS channel materials compatible with Si processes have become an important technical approach to continue Moore's Law.

The carrier mobility of Ge semiconductors and modified Ge semiconductors (including strain-induced modified strained Ge and Sn alloy-modified direct bandgap GeSn) is significantly higher than that of Si semiconductors (wherein, the electron mobility of direct bandgap GeSn is about 4 times that of Si semiconductors, and the hole mobility of the former is about twice that of the latter), and they can be epitaxially prepared on Si substrates and are compatible with Si processes, making them ideal MOS channel materials. Replacing Si materials with them and applying them as channel materials for MOS devices is expected to continue Moore's Law and break the physical limits of Si processes.

However, at present, whether Ge semiconductor or direct bandgap GeSn (i.e., DR-GeSn) is used to make the channel material of the enhanced surface channel nMOS device, due to the poor interface characteristics between the gate dielectric and the P-type Ge-based semiconductor, the Fermi pinning effect caused by the interface state causes the Ge-based enhanced surface channel nMOS channel to be unable to turn on and work in the inversion state. The emergence of this situation makes it impossible to consider a compatible structure with the Ge-based PMOS, and form a complementary Ge-based CMOS device, which greatly limits the performance of the Ge-based CMOS device.

Summary of the invention

In order to solve the above problems existing in the prior art, the present invention provides a direct bandgap GeSn CMOS device and a method for preparing the same. The technical problem to be solved by the present invention is achieved by the following technical solutions:

A first aspect of an embodiment of the present invention provides a direct bandgap GeSn CMOS device, comprising: a substrate layer, a Ge virtual substrate, a first P-type Ge layer, an isolation region, an N well, a second P-type Ge layer, an intrinsic Ge isolation layer, a channel layer, a first intrinsic ternary alloy heterogeneous cap layer, a PMOS gate, a PMOS source and drain region, an N-type Ge layer, a second intrinsic ternary alloy heterogeneous cap layer, an NMOS gate, an NMOS source and drain region, a dielectric layer, a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode, an NMOS drain electrode, and a passivation layer;

The substrate layer, the Ge virtual substrate and the first P-type Ge layer are arranged in sequence from bottom to top;

The N-type Ge layer and the second P-type Ge layer are both located on the upper layer of the first P-type Ge layer;

The N-well is located in the first P-type Ge layer and below the second P-type Ge layer;

The intrinsic Ge isolation layer is located on the upper layer of the N-type Ge layer and the second P-type Ge layer;

The channel layer is located on the upper layer of the intrinsic Ge isolation layer;

The first intrinsic ternary alloy heterogeneous cap layer and the second intrinsic ternary alloy heterogeneous cap layer are both located on the upper layer of the channel layer;

The isolation region extends upward from the first P-type Ge layer through the intrinsic Ge isolation layer and the channel layer to above the first intrinsic ternary alloy heterogeneous cap layer and the second intrinsic ternary alloy heterogeneous cap layer;

The N well, the second P-type Ge layer and the first intrinsic ternary alloy heterogeneous cap layer are located on one side of the isolation region;

The N-type Ge layer and the second intrinsic ternary alloy heterogeneous cap layer are located on the other side of the isolation region;

The PMOS source and drain regions are located within the first intrinsic ternary alloy heterogeneous cap layer, the channel layer and the intrinsic Ge isolation layer;

The NMOS source and drain regions are located within the second intrinsic ternary alloy heterogeneous cap layer, the channel layer and the intrinsic Ge isolation layer;

The PMOS gate is located on the upper layer of the first intrinsic ternary alloy heterogeneous cap layer;

The NMOS gate is located on the upper layer of the second intrinsic ternary alloy heterogeneous cap layer;

The PMOS gate and the NMOS gate are covered with a dielectric layer;

The PMOS source electrode and the PMOS drain electrode are located on the dielectric layer and on one side of the isolation region, and are respectively located on both sides of the PMOS gate;

The NMOS source electrode and the NMOS drain electrode are located on the dielectric layer and on the other side of the isolation region, and on both sides of the NMOS gate;

The dielectric layer, the PMOS source electrode, the PMOS drain electrode, the NMOS source electrode, and the NMOS drain electrode are covered with the passivation layer;

The material of the first intrinsic ternary alloy heterogeneous cap layer is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.05 to 0.07;

The material of the second intrinsic ternary alloy heterogeneous cap layer is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.08 to 0.1;

The channel layer is an intrinsic DR-Ge _1-z Sn _z layer, wherein the range of z is 0.12-0.18.

A second aspect of an embodiment of the present invention provides a method for preparing a direct bandgap GeSn CMOS device, comprising the following steps:

Step 101, substrate selection: select single crystal Si as the substrate layer;

Step 102: Prepare a Ge virtual substrate by using a laser recrystallization method;

Step 103, depositing a first P-type Ge layer on the surface of the Ge virtual substrate;

Step 104, applying photoresist on the surface of the first P-type Ge layer, exposing the photoresist in one area, and implanting P ions in the exposed area by an ion implantation process to form an N well;

Step 105, removing the remaining photoresist, and forming an N-type Ge layer and a second P-type Ge layer on the surface;

Step 106, depositing an intrinsic Ge isolation layer on the surface of the N-type Ge layer and the second P-type Ge layer;

Step 107 , growing intrinsic DR-Ge _1-z Sn _z with a thickness of 15-20 nm on the intrinsic Ge isolation layer to form a channel layer, wherein the range of z is 0.12-0.18;

Step 108, making an isolation region, a first intrinsic ternary alloy heterogeneous cap layer and a second intrinsic ternary alloy heterogeneous cap layer of the device prepared in step 107; wherein the material of the first intrinsic ternary alloy heterogeneous cap layer is Si _x Ge _1-xy Sn _y ; wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07;

The material of the second intrinsic ternary alloy heterogeneous cap layer is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.08 to 0.1;

Step 109, manufacturing a PMOS gate on the first intrinsic ternary alloy heterogeneous cap layer, and manufacturing an NMOS gate on the second intrinsic ternary alloy heterogeneous cap layer;

Step 110, fabricating a PMOS source-drain region and an NMOS source-drain region on the device fabricated in step 109;

Step 111, depositing a dielectric layer on the surface of the device prepared in step 110;

Step 112, manufacturing a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode and an NMOS drain electrode on the dielectric layer;

Step 113, depositing a passivation layer on the surface of the device manufactured in step 112.

Beneficial effects of the present invention:

1. The presence of the intrinsic ternary alloy heterogeneous cap layer of the present invention avoids direct contact between the gate region and the channel layer, thereby eliminating the Fermi pinning effect in the channel region caused by the interface state, which is beneficial to the opening of the channel of the nMOS device; on the other hand, under the field induction effect of the gate voltage and the unilateral high potential barrier blocking effect formed by the conduction band deviation of the intrinsic ternary alloy heterogeneous cap layer and the channel layer deep ΔEC, the electrons originating from the N-type Ge layer will be confined in the channel region, accumulated and then form an open channel, so as to realize a Ge-based enhancement mode nMOS device.

2. When the nMOS channel layer of the device of the present invention transports electrons, the channel electron mobility is further improved due to the absence of surface roughness scattering (the channel layer is not in direct contact with the gate dielectric) and ionized impurity scattering (the immovable charges of ionized impurities are in the N-type Ge layer), and the device performance is correspondingly enhanced; the intrinsic ternary alloy heterogeneous cap layer is a ternary alloy with a high Ge component, and the Fermi pinning effect makes it impossible for this layer to form a parasitic channel, which is beneficial to subsequent circuit applications; the entire device is implemented on a Si substrate, is compatible with Si technology, and is beneficial to integration and cost control.

3. The pMOS part is a three-layer quantum well structure with a wide-narrow-wide-deep ΔE _V valence band bias and double heterojunction. When the device is working, the quantum well structure allows holes to be transported only in the quantum well channel, and there is no surface roughness scattering (no direct contact with the gate dielectric) and ionized impurity scattering (the immovable charge of the ionized impurities is in the second P-type Ge layer). The high hole mobility of the channel ensures the excellent performance of the PMOS.

4. The two layers immediately below the channel layer are the intrinsic Ge isolation layer, the second P-type Ge layer, and the N-type Ge layer. The materials of each layer of the entire device are the same, only the doping of some areas and the ternary alloy composition of the intrinsic ternary alloy heterogeneous cap layer are different. The Ge-based NMOS and Ge-based PMOS structures and processes are more compatible.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

1 to 37 are diagrams of a manufacturing process of a direct bandgap GeSn CMOS device provided by an embodiment of the present invention.

Detailed ways

The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Embodiment 1

Please refer to Figure 37. The first aspect of an embodiment of the present invention provides a direct bandgap GeSn CMOS device, including: a substrate layer 1, a Ge virtual substrate 4, a first P-type Ge layer 5, an isolation region 17, an N well 7, a second P-type Ge layer 11, an intrinsic Ge isolation layer 12, a channel layer 13, a first intrinsic ternary alloy heterogeneous cap layer 16, a PMOS gate, a PMOS source and drain region 25, an N-type Ge layer 8, a second intrinsic ternary alloy heterogeneous cap layer 20, an NMOS gate, an NMOS source and drain region 27, a dielectric layer 28, a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode, an NMOS drain electrode and a passivation layer 30.

The substrate layer 1 , the Ge dummy substrate 4 and the first P-type Ge layer 5 are arranged in sequence from bottom to top. The N-type Ge layer 8 and the second P-type Ge layer 11 are both located on the upper layer of the first P-type Ge layer 5 .

The N-well 7 is located in the first P-type Ge layer 5 and below the second P-type Ge layer 11 .

The intrinsic Ge isolation layer 12 is located on the upper layer of the N-type Ge layer 8 and the second P-type Ge layer 11 .

The channel layer 13 is located on the intrinsic Ge isolation layer 12 .

The first intrinsic ternary alloy heterogeneous cap layer 16 and the second intrinsic ternary alloy heterogeneous cap layer 20 are both located on the upper layer of the channel layer 13 .

The isolation region 17 extends upward from the first P-type Ge layer 5 through the intrinsic Ge isolation layer 12 and the channel layer 13 to above the first intrinsic ternary alloy heterogeneous cap layer 16 and the second intrinsic ternary alloy heterogeneous cap layer 20. The N-well 7, the second P-type Ge layer 11 and the first intrinsic ternary alloy heterogeneous cap layer 16 are located on one side of the isolation region 17. The N-type Ge layer 8 and the second intrinsic ternary alloy heterogeneous cap layer 20 are located on the other side of the isolation region 17.

The PMOS source and drain regions 25 are located in the first intrinsic ternary alloy heterogeneous cap layer 16, the channel layer 13 and the intrinsic Ge isolation layer 12. The NMOS source and drain regions 27 are located in the second intrinsic ternary alloy heterogeneous cap layer 20, the channel layer 13 and the intrinsic Ge isolation layer 12.

The PMOS gate is located on the upper layer of the first intrinsic ternary alloy heterogeneous cap layer 16. The NMOS gate is located on the upper layer of the second intrinsic ternary alloy heterogeneous cap layer 20. A dielectric layer 28 covers the PMOS gate and the NMOS gate.

The PMOS source electrode and the PMOS drain electrode are located on the dielectric layer 28 and on one side of the isolation region 17, and are located on both sides of the PMOS gate. The NMOS source electrode and the NMOS drain electrode are located on the dielectric layer 28 and on the other side of the isolation region 17, and are located on both sides of the NMOS gate. The dielectric layer 28, the PMOS source electrode, the PMOS drain electrode, the NMOS source electrode, and the NMOS drain electrode are covered with a passivation layer 30.

The channel layer 13 is an intrinsic DR-Ge _1-z Sn _z layer, wherein the range of z is 0.12-0.18.

The material of the first intrinsic ternary alloy heterogeneous cap layer 16 is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.05 to 0.07. In this embodiment, the first intrinsic ternary alloy heterogeneous cap layer 16 has a bandgap width greater than the bandgap width of DR-GeSn, and forms a deep _ΔEV valence band bias heterojunction with the channel layer 13. The PMOS part is a wide-bandwidth-narrow-wide-deep _ΔEV valence band bias double heterojunction three-layer quantum well structure. When the device is working, the quantum well structure allows holes to be transported only in the quantum well channel, and there is no surface roughness scattering (not in direct contact with the gate dielectric) and ionized impurity scattering (ionized impurity immovable charges are in the second P-type Ge layer 11), and the high hole mobility of the channel ensures the excellent performance of the PMOS.

The material of the second intrinsic ternary alloy heterogeneous cap layer 20 is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.08 to 0.1. In this embodiment, the bandgap width of the second intrinsic ternary alloy heterogeneous cap layer 20 is greater than the bandgap width of DR-GeSn, and forms a deep _ΔEC conduction band offset heterojunction with the channel layer 13. When the NMOS device is operated by applying a gate voltage, the presence of the intrinsic ternary alloy heterogeneous cap layer avoids direct contact between the gate region and the channel layer 13, thereby eliminating the Fermi pinning effect in the channel region caused by the interface state, which is beneficial to the opening of the channel of the nMOS device; on the other hand, under the field induction effect of the gate voltage and the unilateral high potential barrier blocking effect formed by the deep ΔEC conduction band offset of the intrinsic ternary alloy heterogeneous cap layer and the channel layer 13, the electrons from the N-type Ge layer 8 will be confined to the channel region, accumulated to form an open channel, so as to realize a Ge-based enhancement type nMOS device.

In addition, when electrons in the channel layer 13 are transported, the mobility of channel electrons is further improved due to the absence of surface roughness scattering (the channel layer 13 is not in direct contact with the gate dielectric) and ionized impurity scattering (the immovable charges of ionized impurities are in the N-type Ge layer 8), and the device performance is correspondingly enhanced; the intrinsic ternary alloy heterogeneous cap layer is a ternary alloy with a high Ge component, and the Fermi pinning effect makes it impossible for this layer to form a parasitic channel, which is beneficial to subsequent circuit applications; the entire device is implemented on a Si substrate, which is compatible with Si technology, and is beneficial to integration and cost control.

In this embodiment, the materials of each layer of the entire CMOS device are the same, and only the doping and ternary alloy components of some regions are different. The Ge-based NMOS and Ge-based PMOS structures have good process compatibility. The DR-GeSn CMOS structure composed of a single-sided high-barrier quantum confined NMOS and a quantum well PMOS has high channel carrier mobility and excellent performance indicators such as device driving capability.

Further, the doping concentration of the first P-type Ge layer 5 is 1×10 ¹⁶ ～1×10 ¹⁷ cm ^-3 ; the doping concentration of the second P-type Ge layer 11 is 1×10 ¹⁶ ～1×10 ¹⁹ cm ^-3 ; and the doping concentration of the N-type Ge layer 8 is 1×10 ¹⁶ ～1×10 ¹⁹ cm ^-3 .

Furthermore, the thickness of the channel layer 13 is 15-20 nm.

Furthermore, the thickness of the first intrinsic ternary alloy heterogeneous cap layer 16 is 5-10 nm; the thickness of the second intrinsic ternary alloy heterogeneous cap layer 20 is 5-10 nm.

Furthermore, the substrate layer 1 is made of single crystal Si. The entire device is implemented on a Si substrate, which is compatible with Si technology and is conducive to integration and cost control.

Embodiment 2

A second aspect of an embodiment of the present invention provides a method for preparing a direct bandgap GeSn CMOS device, comprising the following steps:

Step 101 , substrate selection: single crystal Si is selected as the substrate layer 1 , as shown in FIG1 .

Step 102: Prepare Ge virtual substrate 4 by laser recrystallization. The specific steps of step 102 include:

Step 1021 , clean the substrate layer 1 using the RCA method, and then clean it with 10% hydrofluoric acid to remove the Si surface oxide layer.

Step 1022, using the magnetron sputtering method, at a temperature of 400°C to 500°C, an intrinsic Ge target material with a purity of 99.999% is sputtered and deposited on the substrate layer 1 at a process pressure of 1.5×10-3mb and a deposition rate of 5nm/min, with a deposition thickness of 300 to 400nm, to form a Ge epitaxial layer film 2, as shown in Figure 2.

Step 1023 , depositing a first silicon dioxide protection layer 3 : depositing a first silicon dioxide protection layer 3 with a thickness of 100 nm on the Ge epitaxial film 2 by using a CVD process, as shown in FIG. 3 .

Step 1024, heating the material prepared in step 1023 to 600°C to 650°C, and then continuously laser scanning, wherein the laser wavelength is 808nm, the laser power density is 2.1kW/cm2, the laser spot size is 10mm×1mm, the laser moving speed is 20mm/s, and then the material is allowed to cool naturally. Continuous laser irradiation causes the Ge epitaxial layer film 2 to melt and recrystallize after cooling, so that the dislocation density of the epitaxial layer is greatly reduced.

Among them, laser recrystallization of high Ge epitaxial layer film requires precise control of laser physical parameters (laser power, scanning speed, etc.), the initial temperature of the Ge epitaxial layer film 2 and the thickness of the epitaxial layer. For the setting of laser power, the laser energy is required to make the temperature of the Ge epitaxial layer film 2 at least reach the melting point, and as high as possible without exceeding the ablation point. Such a heat treatment process can significantly improve the crystal quality of the Ge epitaxial layer. At the same time, it is also necessary to focus on the initial temperature parameters of the Ge epitaxy. Preheating the Ge epitaxy before laser recrystallization can significantly reduce the threshold laser power required for laser recrystallization. There is a thermal mismatch between the Si substrate and the Ge epitaxial layer film 2. System preheating can also effectively prevent material cracking caused by a sharp increase in temperature during laser irradiation.

Step 1025 , naturally cool the material prepared in step 1024 , and etch the first silicon dioxide protective layer 3 using a dry etching process to obtain a Ge virtual substrate 4 , as shown in FIG. 4 .

Step 103 , depositing a first P-type Ge layer 5 with a thickness of 700-750 nm on the surface of the Ge dummy substrate 4 by molecular beam epitaxy at a temperature of 500-600° C., with a doping concentration of 1×10 ¹⁶ -1×10 ¹⁷ cm ⁻³ , as shown in FIG5 .

Step 104 , applying photoresist 6 on the surface of the first P-type Ge layer 5 , exposing the photoresist in one area and implanting P ions into the exposed area by an ion implantation process to form an N well 7 , as shown in FIG. 6 .

Step 105, remove the remaining photoresist 6, and form an N-type Ge layer 8 and a second P-type Ge layer 11 on the surface. The specific steps of step 105 include:

Step 1051 , removing the remaining photoresist 6 , as shown in FIG. 7 .

Step 1052 , depositing an N-type Ge layer 8 with a thickness of 5 to 10 nm and a doping concentration of 1×10 ¹⁶ to 1×10 ¹⁹ cm ⁻³ on the surface of the device manufactured in step 1501 by using a molecular beam epitaxy (MBE) process, as shown in FIG. 8 .

Step 1053 , depositing a first SiO ₂ layer 9 with a thickness of 20 nm on the surface of the N-type Ge layer 8 , as shown in FIG. 9 .

Step 1054 : depositing a first Si ₃ N ₄ layer 10 with a thickness of 20-30 nm on the first SiO ₂ layer 9 , as shown in FIG. 10 .

Step 1055 , etching and removing the first SiO ₂ layer 9 and the first Si ₃ N ₄ layer 10 at the corresponding position above the N well 7 , as shown in FIG. 11 .

Step 1056 , perform ion compensation on the unmasked N-type Ge layer 8 above the N-well 7 to form a second P-type Ge layer 11 , with a doping concentration of 1×10 ¹⁶ to 1×10 ¹⁹ cm ⁻³ , as shown in FIG. 12 .

Step 1057 : remove the first SiO ₂ layer 9 and the first Si ₃ N ₄ layer 10 on the N-type Ge layer 8 by wet etching, as shown in FIG. 13 .

Step 106 , depositing an intrinsic Ge isolation layer 12 with a thickness of 15 to 20 nm on the surface of the N-type Ge layer 8 and the second P-type Ge layer 11 at a temperature of 500° C. to 600° C. by using a molecular beam epitaxy process, as shown in FIG. 14 .

Step 107 , growing intrinsic DR-Ge _1-z Sn _z with a thickness of 15-20 nm on the intrinsic Ge isolation layer 12 by molecular beam epitaxy at 500° C.-600° C. to form a channel layer 13 , wherein z ranges from 0.12 to 0.18, as shown in FIG. 15 .

Step 108, the device prepared in step 107 is made into an isolation region 17, a first intrinsic ternary alloy heterogeneous cap layer 16 and a second intrinsic ternary alloy heterogeneous cap layer 20; wherein the material of the first intrinsic ternary alloy heterogeneous cap layer 16 is Si _x Ge _{1-x- y} Sn _y ; wherein the range of x is 0.1-0.15, and the range of y is 0.05-0.07.

The material of the second intrinsic ternary alloy heterogeneous cap layer 20 is Si _x Ge _1-xy Sn _y , wherein x is in the range of 0.1 to 0.15, and y is in the range of 0.08 to 0.1. The specific steps of step 108 include:

Step 1081 , using a dry etching process, an isolation groove with a depth of 100 to 150 nm is etched on the device prepared in step 107 , as shown in FIG. 16 .

Step 1082: Deposit a second SiO ₂ material 14 on the device surface at a temperature of 680° C. to 730° C. using a CVD process to fill the isolation trench, as shown in FIG. 17 .

Step 1083: Deposit a second Si ₃ N ₄ layer 15 with a thickness of 20-30 nm on the surface of the second SiO ₂ material 14 by using a CVD process, as shown in FIG. 18 .

Step 1084 , the second SiO ₂ material 14 and the second Si ₃ N ₄ layer 15 on the surface of the channel layer 13 above the N well 7 are removed by etching, as shown in FIG. 19 .

Step 1085 , using a molecular beam epitaxy process to deposit 5-10 nm thick intrinsic Si _x Ge _1-xy Sn _y on the surface of the channel layer 13 to form a first intrinsic ternary alloy heterogeneous cap layer 16 , wherein x ranges from 0.1 to 0.15, and y ranges from 0.05 to 0.07, as shown in FIG. 20 .

Step 1086 , etching away the remaining second Si ₃ N ₄ layer 15 and part of the second SiO ₂ material 14 on the device surface to form an isolation region 17 , as shown in FIG. 21 .

Step 1087 , using the CVD process to continue depositing a third SiO ₂ material 18 and a third Si ₃ N ₄ layer 19 with a thickness of 20 to 30 nm on the surface of the device manufactured in step 1086 , as shown in FIG. 22 .

Step 1088 , the third SiO ₂ material 18 and the third Si ₃ N ₄ layer 19 on the surface of the channel layer 13 on the other side of the isolation region 17 are removed by etching, as shown in FIG. 23 .

Step 1089: Deposit intrinsic Si _x Ge _1-xy Sn _y with a thickness of 5 to 10 nm on the surface of the channel layer 13 using a molecular beam epitaxy process to form a second intrinsic ternary alloy heterogeneous cap layer 20, wherein x ranges from 0.1 to 0.15, and y ranges from 0.08 to 0.10, as shown in FIG24. Then, the remaining third SiO ₂ material 18 and the third Si ₃ N ₄ layer 19 are etched away, as shown in FIG25.

Step 109: fabricate a PMOS gate on the first intrinsic ternary alloy heterogeneous cap layer 16, and fabricate an NMOS gate on the second intrinsic ternary alloy heterogeneous cap layer 20. The specific steps of step 109 include:

Step 1091 , depositing a HfO ₂ layer 21 with a thickness of 5 to 10 nm by atomic layer deposition, as shown in FIG. 26 .

Step 1092: Deposit a TaN layer 22 with a thickness of 70 nm on the surface of the HfO ₂ layer 21 by using a CVD process at a temperature of 750-850° C., as shown in FIG. 27 .

Step 1093, partially etch the TaN layer 22 and the _HfO2 layer 21 using a selective etching process to form a PMOS gate on the first intrinsic ternary alloy heterogeneous cap layer 16, and form an NMOS gate on the second intrinsic ternary alloy heterogeneous cap layer 20, as shown in Figure 28.

Step 110: fabricate a PMOS source/drain region 25 and an NMOS source/drain region 27 on the device fabricated in step 109. The specific steps of step 110 include:

Step 1101: deposit a fourth SiO ₂ material 23 on the surface of the device prepared in step 109 by using a CVD process, and etch out the area other than the NMOS gate and the PMOS gate by using a selective etching process, as shown in FIG. 29 .

Step 1102, using photoresist 24 to cover the NMOS region on the other side of the isolation region 17, using ion implantation process, _BF2 + implantation is performed on the PMOS active region in the N well 7 to form a PMOS source and drain region 25, as shown in FIG30. Then the photoresist 24 is removed.

Step 1103, use photoresist 26 to cover the PMOS region on one side of the isolation region 17, and use ion implantation technology to implant As ions into the NMOS active region to form NMOS source and drain regions 27, as shown in FIG31. Then remove the photoresist 26.

Step 1104: remove the fourth SiO ₂ material 23 on the surface of the NMOS gate and the PMOS gate, as shown in FIG. 32 .

Step 111 , using a CVD process to deposit BPSG with a thickness of 30 to 50 nm on the surface of the device prepared in step 110 to form a dielectric layer 28 , as shown in FIG. 33 .

Step 112: fabricate a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode and an NMOS drain electrode on the dielectric layer 28. Specifically, nitric acid and hydrofluoric acid are used to etch BPSG to form NMOS source and drain contact holes and PMOS source and drain contact holes, as shown in FIG. 34 .

Then, a 20 nm thick metal tungsten 29 is deposited on the device surface by electron beam evaporation to form source and drain contacts, as shown in FIG35. Afterwards, the metal tungsten 29 in the designated area is etched by selective etching, and planarized by CMP, as shown in FIG36.

Step 113, depositing on the surface of the device manufactured in step 112. Using the CVD process, a SiN material with a thickness of 20 to 30 nm is deposited on the entire substrate surface for passivation of the dielectric to form a passivation layer 30, and finally a direct bandgap GeSn CMOS device is formed, as shown in FIG37 .

The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims (9)

1. A direct bandgap GeSn CMOS device, characterized in that it comprises: a substrate layer (1), a Ge virtual substrate (4), a first P-type Ge layer (5), an isolation region (17), an N well (7), a second P-type Ge layer (11), an intrinsic Ge isolation layer (12), a channel layer (13), a first intrinsic ternary alloy heterogeneous cap layer (16), a PMOS gate, a PMOS source and drain region (25), an N-type Ge layer (8), a second intrinsic ternary alloy heterogeneous cap layer (20), an NMOS gate, an NMOS source and drain region (27), a dielectric layer (28), a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode, an NMOS drain electrode and a passivation layer (30); The substrate layer (1), the Ge dummy substrate (4) and the first P-type Ge layer (5) are arranged in sequence from bottom to top; The N-type Ge layer (8) and the second P-type Ge layer (11) are both located on the upper layer of the first P-type Ge layer (5); The N well (7) is located in the first P-type Ge layer (5) and below the second P-type Ge layer (11); The intrinsic Ge isolation layer (12) is located on the upper layer of the N-type Ge layer (8) and the second P-type Ge layer (11); The channel layer (13) is located on the upper layer of the intrinsic Ge isolation layer (12); The first intrinsic ternary alloy heterogeneous cap layer (16) and the second intrinsic ternary alloy heterogeneous cap layer (20) are both located on the upper layer of the channel layer (13); The isolation region (17) extends upward from the first P-type Ge layer (5) through the intrinsic Ge isolation layer (12) and the channel layer (13) to above the first intrinsic ternary alloy heterogeneous cap layer (16) and the second intrinsic ternary alloy heterogeneous cap layer (20); The N well (7), the second P-type Ge layer (11) and the first intrinsic ternary alloy heterogeneous cap layer (16) are located on one side of the isolation region (17); The N-type Ge layer (8) and the second intrinsic ternary alloy heterogeneous cap layer (20) are located on the other side of the isolation region (17); The PMOS source and drain regions (25) are located within the first intrinsic ternary alloy heterogeneous cap layer (16), the channel layer (13) and the intrinsic Ge isolation layer (12); The NMOS source and drain region (27) is located within the second intrinsic ternary alloy heterogeneous cap layer (20), the channel layer (13) and the intrinsic Ge isolation layer (12); The PMOS gate is located on the upper layer of the first intrinsic ternary alloy heterogeneous cap layer (16); The NMOS gate is located on the upper layer of the second intrinsic ternary alloy heterogeneous cap layer (20); The PMOS gate and the NMOS gate are covered with a dielectric layer (28); The PMOS source electrode and the PMOS drain electrode are located on the dielectric layer (28) and on one side of the isolation region (17), and are respectively located on both sides of the PMOS gate; The NMOS source electrode and the NMOS drain electrode are located on the dielectric layer (28) and on the other side of the isolation region (17), and on both sides of the NMOS gate; The dielectric layer (28), the PMOS source electrode, the PMOS drain electrode, the NMOS source electrode, and the NMOS drain electrode are covered with the passivation layer (30); The material of the first intrinsic ternary alloy heterogeneous cap layer (16) is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.05 to 0.07; The material of the second intrinsic ternary alloy heterogeneous cap layer (20) is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.08 to 0.1; The channel layer (13) is an intrinsic DR-Ge _1-z Sn _z layer, wherein the range of z is 0.12 to 0.18. 2. A direct bandgap GeSn CMOS device according to claim 1, characterized in that the doping concentration of the first P-type Ge layer (5) is 1×10 ¹⁶ ～1×10 ¹⁷ cm ^-3 ; the doping concentration of the second P-type Ge layer (11) is 1×10 ¹⁶ ～1×10 ¹⁹ cm ^-3 ; and the doping concentration of the N-type Ge layer (8) is 1×10 ¹⁶ ～1×10 ¹⁹ cm ^-3 . 3. A direct bandgap GeSn CMOS device according to claim 1, characterized in that the thickness of the channel layer (13) is 15-20 nm. 4. A direct bandgap GeSn CMOS device according to claim 1, characterized in that the thickness of the first intrinsic ternary alloy heterogeneous cap layer (16) is 5-10 nm; the thickness of the second intrinsic ternary alloy heterogeneous cap layer (20) is 5-10 nm. 5. A direct bandgap GeSn CMOS device according to claim 1, characterized in that the substrate layer (1) is made of single crystal Si. 6. A method for preparing a direct bandgap GeSn CMOS device, characterized in that it comprises the following steps: Step 101, substrate selection: single crystal Si is selected as the substrate layer (1); Step 102: Prepare a Ge virtual substrate (4) by using a laser recrystallization method; Step 103, depositing a first P-type Ge layer (5) on the surface of the Ge virtual substrate (4); Step 104, applying photoresist on the surface of the first P-type Ge layer (5), exposing the photoresist in one area, and implanting P ions in the exposed area by an ion implantation process to form an N well (7); Step 105, removing the remaining photoresist, and forming an N-type Ge layer (8) and a second P-type Ge layer (11) on the surface; Step 106, depositing an intrinsic Ge isolation layer (12) on the surface of the N-type Ge layer (8) and the second P-type Ge layer (11); Step 107, growing intrinsic DR-Ge _1-z Sn _z with a thickness of 15 to 20 nm on the intrinsic Ge isolation layer (12) to form a channel layer (13), wherein the range of z is 0.12 to 0.18; Step 108, manufacturing an isolation region (17), a first intrinsic ternary alloy heterogeneous cap layer (16) and a second intrinsic ternary alloy heterogeneous cap layer (20) in the device prepared in step 107; wherein the material of the first intrinsic ternary alloy heterogeneous cap layer (16) is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.05 to 0.07; the isolation region (17) extends upward from the first P-type Ge layer (5) through the intrinsic Ge isolation layer (12) and the channel layer (13) to above the first intrinsic ternary alloy heterogeneous cap layer (16) and the second intrinsic ternary alloy heterogeneous cap layer (20); the first intrinsic ternary alloy heterogeneous cap layer (16) is located on one side of the isolation region (17); The material of the second intrinsic ternary alloy heterogeneous cap layer (20) is Si _x Ge _1-xy Sn _y ; wherein the range of x is 0.1 to 0.15, and the range of y is 0.08 to 0.1; Step 109, manufacturing a PMOS gate on the first intrinsic ternary alloy heterogeneous cap layer (16), and manufacturing an NMOS gate on the second intrinsic ternary alloy heterogeneous cap layer (20); Step 110, fabricating a PMOS source-drain region (25) and an NMOS source-drain region (27) on the device fabricated in step 109; Step 111, depositing a dielectric layer (28) on the surface of the device prepared in step 110; Step 112, manufacturing a PMOS source electrode, a PMOS drain electrode, an NMOS source electrode and an NMOS drain electrode on the dielectric layer (28); Step 113, depositing a passivation layer (30) on the surface of the device manufactured in step 112. 7. The method for preparing a direct bandgap GeSn CMOS device according to claim 6, wherein the specific steps of step 105 include: Step 1051, removing the remaining photoresist; Step 1052, depositing an N-type Ge layer (8) with a thickness of 5 to 10 nm on the surface of the device manufactured in step 1501, with a doping concentration of 1×10 ¹⁶ to 1×10 ¹⁹ cm ^-3 ; Step 1053, depositing a first _SiO2 layer (9) with a thickness of 20 nm on the surface of the N-type Ge layer (8); Step 1054, depositing a first Si ₃ N ₄ layer (10) with a thickness of 20-30 nm on the first SiO ₂ layer (9); Step 1055, etching and removing the first _SiO2 layer (9) and the first _Si3N4 layer ( ₁₀ ) at corresponding positions above the N well (7); Step 1056, performing ion compensation on the N-type Ge layer (8) above the N-well (7) to form a second P-type Ge layer (11), with a doping concentration of 1×10 ¹⁶ to 1×10 ¹⁹ cm ^-3 ; Step 1057: Use a wet etching method to remove the first SiO ₂ layer (9) and the first Si ₃ N ₄ layer (10) on the N-type Ge layer (8). 8. The method for preparing a direct bandgap GeSn CMOS device according to claim 6, wherein the specific steps of step 108 include: Step 1081, using a dry etching process, etching an isolation groove with a depth of 100 to 150 nm on the device prepared in step 107; Step 1082, depositing a second _SiO2 material (14) on the device surface to fill the isolation groove; Step 1083, depositing a second Si ₃ N ₄ layer (15) with a thickness of 20 to 30 nm on the surface of the second SiO ₂ material (14); Step 1084, etching and removing the second SiO ₂ material (14) and the second Si ₃ N ₄ layer (15) on the surface of the channel layer (13) above the N well (7); Step 1085, depositing intrinsic Si _x Ge _1-xy Sn _y with a thickness of 5 to 10 nm on the surface of the channel layer (13) to form a first intrinsic ternary alloy heterogeneous cap layer (16), wherein the range of x is 0.1 to 0.15, and the range of y is 0.05 to 0.07; Step 1086, etching away the remaining second Si ₃ N ₄ layer (15) and part of the second SiO ₂ material (14) on the surface of the device to form an isolation region (17); Step 1087, depositing 20-30 nm of a third SiO ₂ material (18) and a third Si ₃ N ₄ layer (19) on the surface of the device manufactured in step 1086; Step 1088, etching and removing the third SiO ₂ material (18) and the third Si ₃ N ₄ layer (19) on the surface of the channel layer (13) on the other side of the isolation region (17); Step 1089, depositing intrinsic Si _x Ge _1-xy Sn _y with a thickness of 5-10 nm on the surface of the channel layer (13) to form a second intrinsic ternary alloy heterogeneous cap layer (20), wherein the range of x is 0.1-0.15, and the range of y is 0.08-0.10; and then etching away the remaining third SiO ₂ material (18) and the third Si ₃ N ₄ layer (19). 9. The method for preparing a direct bandgap GeSn CMOS device according to claim 6, wherein the specific steps of step 110 include: Step 1101, depositing a fourth _SiO2 material (23) on the surface of the device prepared in step 109, and etching out the area other than the NMOS gate and the PMOS gate; Step 1102: Cover the NMOS region on the other side of the isolation region (17) with photoresist, and use an ion implantation process to implant _BF2 + into the PMOS active region in the N well (7) to form a PMOS source and drain region (25); Step 1103, using photoresist to cover the PMOS region on one side of the isolation region (17), and using an ion implantation process to implant As ions into the NMOS active region to form an NMOS source and drain region (27); Step 1104, removing the fourth _SiO2 material (23) on the surface of the NMOS gate and the PMOS gate.