CN113517334A - A kind of power MOSFET device with high-K dielectric trench and preparation method thereof - Google Patents

Abstract

The invention discloses a power MOSFET device with a high-K dielectric groove and a preparation method thereof, wherein the device sequentially comprises the following components from bottom to top: the device comprises a first metal layer, an N + substrate, an N-epitaxial layer and a main body structure layer; the N-epitaxial layer is internally provided with a plurality of groove well structures, the groove well structures extend downwards from the upper surface of the N-epitaxial layer, and the depth of the groove well structures is smaller than the thickness of the N-epitaxial layer; a high-K dielectric groove is arranged between two adjacent groove well structures, and the depth of the high-K dielectric groove is the same as the thickness of the N-epitaxial layer; the upper surface of the high-K dielectric groove region is provided with a groove gate, the groove gate is positioned between two adjacent main body structure layers, and a second metal layer is arranged on the groove gate; and a device source electrode is formed on the main body structure layer. The power MOSFET device provided by the invention combines the trench gate, the high-K dielectric trench and the trench well, obtains the maximum breakdown voltage, reduces the on-resistance to the maximum extent and improves the device performance.

Description

A kind of power MOSFET device with high-K dielectric trench and preparation method thereof

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a power MOSFET device with a high-K dielectric trench and a preparation method thereof.

Background technique

With the continuous development of semiconductor technology, higher requirements are put forward for power devices in electronic power systems. Power Metal-Oxide-Semiconductor Field-Effect Transistor (Power MOSFET), also known as power field effect transistor, is a field effect transistor that uses gate voltage to control drain current. It is characterized by simple driving circuit, small driving power, fast switching speed and high operating frequency; however, its current capacity is small and its withstand voltage is low, so it is only used for low-power power electronic devices and cannot be widely used in high-voltage fields.

In recent years, people have been devoted to improving the relationship between the on-resistance Ron and the breakdown voltage VB of the field effect transistor, trying to obtain the smallest on-resistance while having a high breakdown voltage. In 1991, Professor Chen Xingbi from the University of Electronic Science and Technology of China independently proposed the composite buffer layer (CB) structure, and proposed that the structure has the relationship of Ron∝VB ^1.32 , which successfully broke the "silicon limit" of the traditional pressure-resistant layer. The CB structure is also known as a super junction (Superjunction, SJ) withstand voltage layer. A MOSFET using a superjunction withstand voltage layer is called a superjunction MOSFET (SJ-MOSFET). Under the same breakdown voltage, the on-resistance of SJ-MOSFET can be an order of magnitude lower than that of conventional power MOSFETs.

However, based on the development of electronic power technology, the existing performance methods such as low on-resistance and high breakdown voltage of superjunction MOSFET devices still cannot be used in all scenarios; To a certain extent, its application scope is limited.

SUMMARY OF THE INVENTION

In order to solve the above problems existing in the prior art, the present invention provides a power MOSFET device with a high-K dielectric trench and a preparation method thereof. The technical problem to be solved by the present invention is realized by the following technical solutions:

A power MOSFET device with a high-K dielectric trench, including from bottom to top: a first metal layer, an N+ substrate, an N- epitaxial layer and a main structure layer; wherein,

The N-epitaxial layer is provided with a plurality of trench well structures, the trench well structures extend downward from the upper surface of the N-epitaxial layer, and the depth thereof is smaller than the thickness of the N-epitaxial layer;

A high-K dielectric trench is arranged between two adjacent trench well structures, and the depth of the high-K dielectric trench is the same as the thickness of the N- epitaxial layer; the trench well structure, the The high-K dielectric trench and the N-epitaxial layer therebetween together form a three-dimensional superjunction structure;

A trench gate is provided on the upper surface of the high-K dielectric trench region, the trench gate is located between two adjacent main body structure layers, and a second metal layer is formed thereon;

A device source electrode is formed on the main body structure layer.

In an embodiment of the present invention, the doping concentration of the trench well structure gradually decreases from bottom to top.

In an embodiment of the present invention, the trench well structure includes a first trench well and a second trench well; wherein the second trench well starts from the upper surface of the N- epitaxial layer, and extending inside the N-epitaxial layer;

The first trench well is located below the second trench well and has a certain distance from the N- epitaxial layer to form a depletion region.

In an embodiment of the present invention, the width of the first trench well is smaller than the width of the second trench well.

In one embodiment of the present invention, the depth of the first trench well is smaller than the depth of the second trench well.

In an embodiment of the present invention, the ion doping concentration of the first trench well is greater than the ion doping concentration of the second trench well.

In an embodiment of the present invention, the body structure layer includes a P+ substrate, an N+ doped region and a P+ doped region, the P+ substrate is located on the N- epitaxial layer, the N+ doped region and The P+ doped regions are all located on the P+ substrate, and the P+ doped regions are located between two N+ doped regions.

In an embodiment of the present invention, the ion doping concentration of the P+ substrate is greater than the ion doping concentration of the second trench well, and is smaller than the ion implantation concentration of the P+ doping region.

In one embodiment of the present invention, the high-K dielectric trench region is formed by implanting high-K dielectric ions, and the high-K dielectric ions include nitride or gold oxide.

Another embodiment of the present invention also provides a method for fabricating a power MOSFET device with a high-K dielectric trench, comprising the following steps:

Selecting the first metal layer as the drain electrode of the device, and growing an N+ substrate on it;

epitaxially growing an N- epitaxial layer on the N+ substrate for many times, and performing etching and ion implantation after each growth to form a trench well structure;

performing ion implantation on the N-epitaxial layer in the middle of the trench well to form a high-K dielectric trench region;

Perform multiple ion implantation on the surface of the sample to form a main structure layer;

A trench gate structure and a source electrode are fabricated to complete the device fabrication.

Beneficial effects of the present invention:

1. In the present invention, a trench well structure is arranged in the epitaxial layer of the device to form a depletion region between the trench well and the epitaxial layer, thereby increasing the area of the depletion region of the device and improving the breakdown voltage. A high-K dielectric trench structure is also arranged between the structures, which changes the electric field distribution in the drift region, reduces the lateral component of the electric field, and makes the vertical electric field distribution uniform, which further improves the breakdown voltage;

2. The present invention uses high-K dielectric ion implantation technology to form a K dielectric trench structure, which replaces part of the N-drift region, increases the equivalent dielectric constant of the drift region, optimizes the electric field, and improves the charge balance problem; At the same time, for high-K dielectrics, the higher the dielectric constant, the stronger the MIS capacitance effect, so that the device has higher impurity concentration and smaller on-resistance;

3. In the present invention, the ion implantation concentration of the trench well structure is set to a non-uniform mode that gradually decreases from bottom to top, and the relationship between breakdown voltage and on-resistance is compromised under the condition that the depletion region is kept to a maximum;

4. The power MOSFET device with the high-K dielectric trench provided by the present invention combines the trench gate, the high-K dielectric trench and the trench well to obtain the maximum breakdown voltage while reducing the maximum breakdown voltage to the greatest extent. On-resistance improves device performance.

The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

Description of drawings

1 is a schematic structural diagram of a power MOSFET device with a high-K dielectric trench provided by an embodiment of the present invention;

Fig. 2a is the equipotential surface of the existing common channel;

2b is an equipotential surface of a high-K dielectric trench provided by an embodiment of the present invention;

3 is a flowchart of a method for preparing a power MOSFET device with a high-K dielectric trench provided by an embodiment of the present invention;

4a-4j are schematic diagrams of a preparation process of a power MOSFET device with a high-K dielectric trench provided by an embodiment of the present invention;

Description of reference numbers:

1-first metal layer; 2-N+ epitaxial region; 3-N- epitaxial region; 4-first trench well; 5-second trench well; 6-high-K dielectric trench; 7-P+ implantation region ; 8-trench gate; 9-N+ implantation region; 10-P+ implantation region; 11-third metal layer; 12-silicon dioxide layer; 13-second metal layer.

Detailed ways

The present invention will be described in further detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

Example 1

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a power MOSFET device with a high-K dielectric trench provided by an embodiment of the present invention. From bottom to top, it includes: a first metal layer 1, an N+ substrate 2, an N- Epitaxial layer 3 and main structure layer; wherein,

A plurality of trench well structures are arranged in the N-epitaxial layer 3, and the trench well structures extend downward from the upper surface of the N-epitaxial layer 3, and the depth thereof is smaller than the thickness of the N-epitaxial layer 3;

A high-K dielectric trench 6 is arranged between two adjacent trench well structures, and the depth of the high-K dielectric trench 6 is the same as the thickness of the N- epitaxial layer 3; the trench well structure, the high-K dielectric trench The groove 6 and the N-epitaxial layer 3 between the two together form a three-dimensional superjunction structure;

A trench gate 8 is provided on the upper surface of the high-K dielectric trench region 6, and the trench gate 8 is located between two adjacent main body structure layers, and has a second metal layer 11 thereon;

A device source electrode 13 is formed on the body structure layer.

Specifically, the first metal layer 1 is the drain of the MOSFET device and is located on the backside of the N+ substrate region 2 . The second metal layer 13 is used to provide a gate voltage for the trench gate 8 .

This embodiment adopts the trench gate structure, which shortens the channel length compared with the planar gate structure, and the high-K dielectric trench under the trench can adjust the carrier distribution and reduce the on-resistance.

Further, the trench well structure may include a plurality of vertically distributed trench wells, the doping concentration of which is gradually decreased from bottom to top. In this embodiment, the ion implantation concentration of the trench well structure is set to a non-uniform mode that gradually decreases from bottom to top, and the relationship between the breakdown voltage and the on-resistance is compromised under the condition of keeping the maximum depletion region.

For example, in the present embodiment, the trench well structure may include a first trench well 4 and a second trench well 5; wherein, the second trench well 5 starts from the upper surface of the N- epitaxial layer 3 and extends toward the N - the internal extension of the epitaxial layer 3;

The first trench well 4 is located under the second trench well 5 and has a certain distance from the N- epitaxial layer 3 to form a depletion region.

The width and depth of the first trench well 4 are both smaller than those of the second trench well 5 , and the ion doping concentration of the first trench well 4 is greater than that of the second trench well 5 .

In this embodiment, the first trench well and the second trench well use deep trench filling technology, that is, in the deep trench filling method, a plurality of first trenches can be formed by epitaxy or chemical vapor deposition a trench well and a plurality of second trench wells.

Furthermore, in this embodiment, the high-K dielectric trench region 6 is formed by implanting high-K dielectric ions, wherein the high-K dielectric ions include nitrides or gold oxides, such as Si ₃ N ₄ , Al ₂ O ₃ , _TiO2 , etc.

Specifically, in this embodiment, a high-K dielectric trench structure is formed by using a high-K dielectric ion implantation technology, which replaces part of the N-drift region, so that the equivalent dielectric constant of the drift region is increased, the electric field is optimized, and the charge is improved. At the same time, for high-K dielectrics, the higher the dielectric constant, the stronger the MIS capacitive effect, resulting in a higher impurity concentration and smaller on-resistance for the device.

2a-2b, FIG. 2a is an equipotential surface of an existing common channel, and FIG. 2b is an equipotential surface of a high-K dielectric trench provided by an embodiment of the present invention; The K material trench changes the electric field distribution in the drift region, making it more uniform and compact. Due to the modulation of the HK species on the E field, the lateral component of the electric field is very small and the vertical electric field distribution is very uniform, thus obtaining a high breakdown voltage.

Multiple experiments have shown that the extended high-K material trench brings a larger MIS capacitance in the drift region, thereby enhancing the auxiliary depletion, thus reducing the on-resistance and the sensitivity to charge balance. Compared with a MOSFET device without a dielectric trench, its breakdown voltage increased by 12 percent and on-resistance decreased by 50 percent.

In this embodiment, a trench well structure is arranged in the epitaxial layer of the device to form a depletion region between the trench well and the epitaxial layer, thereby increasing the area of the depletion region of the device and improving the breakdown voltage. At the same time, in the trench well structure There is also a high-K dielectric trench structure between them, which changes the electric field distribution in the drift region, reduces the lateral component of the electric field, and makes the vertical electric field distribution uniform, which further improves the breakdown voltage.

In this embodiment, the main structure layer includes a P+ substrate 7 , an N+ doped region 9 and a P+ doped region 10 , the P+ substrate 7 is located on the N− epitaxial layer 3 , the N+ doped region 9 and the P+ doped region 10 Both are located on the P+ substrate 7 , and the P+ doped region 10 is located between the two N+ doped regions 9 .

The ion doping concentration of the P+ substrate 7 is greater than the ion doping concentration of the second trench well 5 , and is smaller than the ion implantation concentration of the P+ doping region 10 .

Further, a third metal layer 11 is provided on the P+ doped region 10 and part of the N+ doped region 9 to serve as the source electrode of the device, and the silicon dioxide layer 12 is passed between the third metal layer 11 and the second metal layer 13 separated.

The power MOSFET device with the high-K dielectric trench provided by the present invention combines the trench gate, the high-K dielectric trench and the trench well, so as to obtain the maximum breakdown voltage and reduce the conduction to the greatest extent. resistance, improving device performance.

Embodiment 2

On the basis of the above-mentioned first embodiment, this embodiment provides a method for fabricating a power MOSFET device with a high-K dielectric trench. Please refer to FIG. 3. FIG. 3 is a flowchart of a method for preparing a power MOSFET device with a high-K dielectric trench provided by an embodiment of the present invention, which specifically includes the following steps:

S1: Select the first metal layer as the device drain, and grow an N+ substrate on it;

S2: epitaxially grow the N- epitaxial layer on the N+ substrate for many times, and perform etching and ion implantation after each growth to form a trench well structure;

S3: perform ion implantation on the N-epitaxial layer in the middle of the trench well to form a high-K dielectric trench region;

S4: perform multiple ion implantation on the surface of the sample to form a main structure layer;

The main structure layer includes a P+ substrate, an N+ doped region and a P+ doped region, the P+ substrate is located on the upper part of the N- epitaxial layer, the N+ doped region and the P+ doped region are both located on the P+ substrate, and the P+ doped region The region is located between the two N+ doped regions.

S5: fabricating a trench gate structure and a source electrode to complete device fabrication.

In this embodiment, in the process of preparing a power MOSFET device with a high-K dielectric trench, multiple epitaxy techniques and ion implantation techniques are used, which reduces the difficulty of the process.

The preparation process of the present invention will be described in detail below with reference to the accompanying drawings. Please refer to FIGS. 4a-4j. FIGS. 4a-4j are schematic diagrams of a preparation process of a power MOSFET device with a high-K dielectric trench provided by an embodiment of the present invention, which specifically includes:

Step 1: Select a first metal, such as copper, etc., as the first metal layer 1, and grow an N+ substrate 2 thereon, as shown in FIG. 4a.

Specifically, since the conduction channel of the trench power MOSFET is from the source on the surface of the silicon wafer to the drain on the back, in order to reduce conduction, the doping concentration of the silicon substrate must be increased as much as possible. The red phosphorus-doped silicon substrate generally has a doping concentration of 1×10 ¹³ cm ^-3 to 1×10 ¹³ cm ^-3 .

Step 2: A part of polysilicon 3 is firstly epitaxially grown on the N+ substrate 2, as shown in FIG. 4b.

Step 3: Perform trench etching on the epitaxial layer formed by the above-mentioned part of the polysilicon 3. After mask projection and exposure, dry etching is used to form a first trench on the epitaxial single crystal silicon, as shown in FIG. 4c.

Step 4: Perform P+ ion implantation into the first trench by using the deep trench filling technology to form the first trench well 4, as shown in FIG. 4d.

Specifically, the doping concentration of the first trench well is 1×10 ¹⁵ cm ^-3 to 1×10 ¹⁷ cm ^-3 .

Step 5: Continue to epitaxy the N-material in the N-epitaxial layer 3, and the thickness of the epitaxial layer this time is greater than the thickness of the first epitaxial layer, as shown in FIG. 4e.

Step 6: Perform trench etching on the above epitaxial layer, after mask projection and exposure, dry etching is used to form a second trench on the epitaxial single crystal silicon, as shown in FIG. 4f.

Step 7: Implanting P+ ions into the second trench by using the deep trench filling technique. At this time, the ion concentration is lower than the ion concentration in the first trench well, and the second trench well 5 is formed, as shown in FIG. 4g.

Specifically, the doping concentration of the second trench well is 1×10 ¹⁴ cm ⁻³ to 1×10 ¹⁶ cm ⁻³ , which is about an order of magnitude lower than the ion concentration of the first trench.

Step 8: A high-K dielectric trench is formed by ion implantation of a high-K dielectric material, and the high-K dielectric material is shown in FIG. 4h.

Specifically, a material with a relative dielectric constant of 100-2000 is usually selected here, such as TiO ₂ . The higher the relative permittivity of a material, the more it can strengthen the electric field in its drift region.

Step 9: Continue to use ion implantation to form P+ substrate 7, N+ doped region 9 and P+ doped region 10 on the N- epitaxial layer 3 in sequence, so as to form the main layer structure during the formation, as shown in FIG. 4i.

Step 10: Fabricate the trench gate 8, and cover the entire surface of the device with metal and silicon dioxide to form the gate and source of the device, as shown in FIG. 4j.

So far, the fabrication of power metal-oxide-semiconductor field-effect transistor devices with extended high-K dielectric trenches and three-dimensional superjunctions is completed.

It should be noted that, in this embodiment, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply these entities or operations. There is no such actual relationship or sequence between operations.

The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be considered that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deductions or substitutions can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

1. A power MOSFET device with a high-K dielectric trench, characterized in that, from bottom to top, it comprises: a first metal layer (1), an N+ substrate (2), an N- epitaxial layer (3) and main structure layer; of which, A plurality of trench well structures are arranged in the N-epitaxial layer (3), the trench well structures extend downward from the upper surface of the N-epitaxial layer (3), and the depth thereof is smaller than that of the N-epitaxial layer thickness of layer (3); A high-K dielectric trench (6) is provided between two adjacent trench well structures, and the depth of the high-K dielectric trench (6) is the same as the thickness of the N-epitaxial layer (3); The trench well structure, the high-K dielectric trench (6) and the N-epitaxial layer (3) therebetween together form a three-dimensional superjunction structure; A trench gate (8) is provided on the upper surface of the high-K dielectric trench region (6), the trench gate (8) is located between two adjacent main body structure layers, and a second metal is formed thereon layer(13); A device source electrode (13) is formed on the main body structure layer. 2 . The power MOSFET device according to claim 1 , wherein the doping concentration of the trench well structure gradually decreases from bottom to top. 3 . 3. The power MOSFET device according to claim 1, wherein the trench well structure comprises a first trench well (4) and a second trench well (5); wherein the second trench A well (5) starts from the upper surface of the N-epitaxial layer (3) and extends toward the interior of the N-epitaxial layer (3); The first trench well (4) is located below the second trench well (5) and has a certain distance from the N- epitaxial layer (3) to form a depletion region. 4. The power MOSFET device according to claim 3, wherein the width of the first trench well (4) is smaller than the width of the second trench well (5). 5. The power MOSFET device according to claim 3, characterized in that the depth of the first trench well (4) is smaller than the depth of the second trench well (5). 6. The power MOSFET device according to claim 3, wherein the ion doping concentration of the first trench well (4) is greater than the ion doping concentration of the second trench well (5). 7. The power MOSFET device according to claim 3, characterized in that, the main structure layer comprises a P+ substrate (7), an N+ doped region (9) and a P+ doped region (10), the P+ substrate The bottom (7) is located on the N- epitaxial layer (3), the N+ doped region (9) and the P+ doped region (10) are both located on the P+ substrate (7), and the A P+ doped region (10) is located between the two N+ doped regions (9). 8. The power MOSFET device according to claim 6, characterized in that, the ion doping concentration of the P+ substrate (7) is greater than the ion doping concentration of the second trench well (5), and is less than the ion doping concentration of the second trench well (5) The ion implantation concentration of the P+ doped region (10). 9. The power MOSFET device according to claim 1, wherein the high-K dielectric trench region (6) is formed by implanting high-K dielectric ions, the high-K dielectric ions comprising nitride or gold oxide. 10. A preparation method of a power MOSFET device with a high-K dielectric trench, characterized in that, comprising the following steps: Selecting the first metal layer as the drain electrode of the device, and growing an N+ substrate on it; epitaxially growing an N- epitaxial layer on the N+ substrate for many times, and performing etching and ion implantation after each growth to form a trench well structure; performing ion implantation on the N-epitaxial layer in the middle of the trench well to form a high-K dielectric trench region; Perform multiple ion implantation on the surface of the sample to form a main structure layer; A trench gate structure and a source electrode are fabricated to complete the device fabrication.

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