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CN113541718A - Four-channel multi-function chip - Google Patents

Four-channel multi-function chip Download PDF

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CN113541718A
CN113541718A CN202110662635.8A CN202110662635A CN113541718A CN 113541718 A CN113541718 A CN 113541718A CN 202110662635 A CN202110662635 A CN 202110662635A CN 113541718 A CN113541718 A CN 113541718A
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serial
phemt
terminal
phase shifter
pin
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CN113541718B (en
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刘会东
崔璐
赵子润
刘永强
马瑞
魏洪涛
吴洪江
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CETC 13 Research Institute
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
    • H04B1/40—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/02—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas
    • H04B7/04—Diversity systems; Multi-antenna system, i.e. transmission or reception using multiple antennas using two or more spaced independent antennas

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Abstract

本发明适用于微波单片集成电路技术领域，提供了一种四通道多功能芯片，包括：多功能芯片的输入端、多功能芯片的四个输出端、多功能芯片的供电端、多功能芯片的接地端、放大器、栅端供电端、漏端供电端、一分四功分器、四个移相器、三个串转并驱动器、数据锁存端、数据输入端、时钟端和片选端；第一移相器、第二移相器、第三移相器和第四移相器中的至少之一包括移相功能模块，移相功能模块至少包括衰减电路。本发明通过在移相器中设置衰减电路，对输出信号进行衰减，有效改善与移相器连接的输出端口的电压驻波比，从而提高四通道多功能芯片的性能。

Figure 202110662635

The invention is applicable to the technical field of microwave monolithic integrated circuits, and provides a four-channel multi-function chip, comprising: an input end of the multi-function chip, four output ends of the multi-function chip, a power supply end of the multi-function chip, and a multi-function chip The ground terminal, amplifier, gate-side power supply terminal, drain-side power supply terminal, one-to-four power divider, four phase shifters, three serial-to-parallel drivers, data latch terminal, data input terminal, clock terminal and chip select terminal; at least one of the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter includes a phase shifting function module, and the phase shifting function module at least includes an attenuation circuit. The invention effectively improves the voltage standing wave ratio of the output port connected with the phase shifter by setting an attenuation circuit in the phase shifter to attenuate the output signal, thereby improving the performance of the four-channel multifunctional chip.

Figure 202110662635

Description

Four-channel multifunctional chip
Technical Field
The invention belongs to the field of microwave monolithic integrated circuits, and particularly relates to a four-channel multifunctional chip.
Background
In a microwave millimeter wave phased array antenna system, a TR (transmitter and receiver) component is a basic module unit of a phased array antenna, plays the functions of amplitude control and phase control, and mainly comprises an amplitude limiter, an amplifier and a multifunctional chip, wherein the multifunctional chip is the core component of the TR component. For TR components of different functions, the multifunction chip requires different functions, and thus the performance index of the multifunction chip may also be different.
The voltage standing wave ratio is an important index for measuring the performance of the multifunctional chip. The voltage standing wave ratio represents the reflection degree of the signals of the input and output ports, and can also represent the mismatching degree of the ports. In the prior art, an input port of a multifunctional chip of a TR module is connected to an output port of a low noise amplifier chip, and an output port of the multifunctional chip is connected to an input port of a power amplifier chip, so as to perform signal transmission between the chips.
However, when each chip performs signal transmission, energy loss of the input port and the output port of the multifunctional chip is relatively serious, that is, the voltage standing wave ratio of the input port and the output port is poor.
Disclosure of Invention
In view of this, embodiments of the present invention provide a four-channel multifunctional chip to solve the problem of a difference in voltage standing wave ratio between an input port and an output port of the four-channel multifunctional chip in the prior art.
A first aspect of an embodiment of the present invention provides a four-channel multifunctional chip, including:
the circuit comprises an input end of a multifunctional chip, four output ends of the multifunctional chip, a power supply end of the multifunctional chip, a grounding end of the multifunctional chip, an amplifier, a grid end power supply end, a drain end power supply end, a one-to-four power divider, four phase shifters, three serial-parallel drivers, a data latch end, a data input end, a clock end and a chip selection end, wherein the input end of the multifunctional chip is connected with the four output ends of the multifunctional chip;
the four output ends of the multifunctional chip comprise a first output end of the multifunctional chip, a second output end of the multifunctional chip, a third output end of the multifunctional chip and a fourth output end of the multifunctional chip;
the four phase shifters comprise a first phase shifter, a second phase shifter, a third phase shifter and a fourth phase shifter;
the three serial-to-parallel drivers comprise a first serial-to-parallel driver, a second serial-to-parallel driver and a third serial-to-parallel driver;
the amplifier is respectively connected with the input end, the grid end power supply end, the drain end power supply end and the one-to-four power divider of the multifunctional chip;
the four-in-one power divider is respectively connected with a first phase shifter, a second phase shifter, a third phase shifter and a fourth phase shifter, the first phase shifter is connected with a first output end of the multifunctional chip, the second phase shifter is connected with a second output end of the multifunctional chip, the third phase shifter is connected with a third output end of the multifunctional chip, and the fourth phase shifter is connected with a fourth output end of the multifunctional chip;
the first serial-parallel driver is respectively connected with the second serial-parallel driver, the third serial-parallel driver, the power supply end of the multifunctional chip, the grounding end, the data latch end, the data input end, the clock end and the chip selection end of the multifunctional chip, and the second serial-parallel driver is connected with the third serial-parallel driver;
the third serial-parallel driver is connected with the first phase shifter and the second phase shifter, and the second serial-parallel driver is connected with the third phase shifter and the fourth phase shifter;
at least one of the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter includes a phase shift functional module including at least an attenuation circuit.
Compared with the prior art, the embodiment of the invention has the following beneficial effects:
the four-channel multifunctional chip of the embodiment of the invention comprises: the circuit comprises an input end of a multifunctional chip, four output ends of the multifunctional chip, a power supply end of the multifunctional chip, a grounding end of the multifunctional chip, an amplifier, a grid end power supply end, a drain end power supply end, a one-to-four power divider, four phase shifters, three serial-parallel drivers, a data latch end, a data input end, a clock end and a chip selection end, wherein the input end of the multifunctional chip is connected with the four output ends of the multifunctional chip; at least one of the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter includes a phase shift functional module including at least an attenuation circuit. The phase shifter is provided with the attenuation circuit to attenuate the output signal, so that the voltage standing wave ratio of the output port connected with the phase shifter is effectively improved, and the performance of the four-channel multifunctional chip is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic structural diagram of a four-channel multifunctional chip according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a four-channel multifunctional chip according to another embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of an RFin-RFout1 phase shift functional module in a quad-channel multi-function chip according to an embodiment of the present invention;
FIG. 4 is a circuit layout of an RFin-RFout1 phase shift functional module in a quad-channel multi-function chip according to an embodiment of the present invention;
FIG. 5 is a schematic voltage standing wave ratio test curve of the first output port RFout1 of a four-channel multifunctional chip according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of an impedance Smith chart test curve of the first output port RFout1 of the four-channel multifunctional chip according to the embodiment of the invention;
FIG. 7 is a schematic circuit diagram of an improved RFin-RFout1 phase shift functional module in a quad-channel multi-function chip according to an embodiment of the present invention;
FIG. 8 is a circuit layout of an improved RFin-RFout1 phase shift functional module in a four-channel multi-function chip according to an embodiment of the present invention;
FIG. 9 is a schematic voltage standing wave ratio test curve of the first output port RFout1 of the improved quad-channel multifunctional chip according to the embodiment of the present invention;
fig. 10 is a schematic diagram of an impedance smith chart test curve of the first output port RFout1 of the improved four-channel multifunctional chip according to the embodiment of the invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical scheme of the invention, the performance index of the multi-channel multifunctional chip is explained below.
The important performance indexes of the multi-channel multifunctional chip are as follows:
1. the working frequency is as follows: generally, the frequency band is an operating frequency band, such as 14 GHz-18 GHz, 19 GHz-23 GHz, 29 GHz-31 GHz, etc.
2. Gain: the amplification capability of the chip to the signal can be expressed as output power to input power, i.e. gin ═ Pout/Pin.
3. Input-output voltage standing wave ratio: the degree of reflection of the input/output port signal may be expressed by the degree of port mismatch, i.e., VSWR (1+ | Γ |)/(1- | Γ |), where Γ is the voltage reflection coefficient of the port.
4. Phase shift digit, phase shift step and phase shift range: the phase-shifting digit is 6, the phase-shifting step is 5.625 degrees, the total number of 63 phase-shifting states is 63, and the phase-shifting range is 5.625-354.375 degrees.
5. Relative phase shift quantity: the relative phase shift amount of each phase-shifted state is PSi ═ phase (S21 for the corresponding phase-shifted state) -phase (S21 for the reference state) |.
6. Phase shift precision: the phase-shifting precision of each phase-shifted state is delta phi i-PSi-the nominal value of the corresponding phase-shifted state
7. Phase-shift root mean square error:
Figure BDA0003115694770000041
wherein n is 63.
8. Amplitude consistency among channels:
gain Gi ═ dB in the reference state of each channel (S21 in the reference state) i, i ═ 1,2,3, …, n;
the amplitude consistency among the channels refers to the gain consistency among different channels of the same tested chip under the same frequency in a reference state, namely, Δ Am is max (G1, G2, G3, …, Gn) -min (G1, G2, G3, …, Gn).
9. Phase consistency among channels:
phase PHi ═ phase (S21 for reference state) i |, i ═ 1,2,3, …, n for each channel reference state;
the phase consistency among the channels refers to the phase consistency among different channels of the same tested chip under the same frequency, and Δ φ n is max (PH1, PH2, PH 3, …, PH n) -min (PH1, PH2, PH 3, …, PH n).
Note 1: dB () is a function that converts the magnitude-phase form of the S parameter to decibel representation.
Note 2: phase () is a function that converts the amplitude-phase form of the S-parameter to a phase representation.
Note 3: and 2 and 1 in the S parameters correspond to an output port and an input port of the tested chip during testing.
Note 4: the reference state refers to a state in which no phase shift is performed.
In the TR component, an input port of a multifunctional chip is connected with an output port of a low-noise amplifier chip in most cases, and an output port of the multifunctional chip is connected with an input port of a power amplifier chip; in order to reduce the loss of energy transfer between the chips as much as possible, the port butted between the chips is required to have a good voltage standing wave ratio. The invention provides an optimization method which can improve the voltage standing wave ratio of a multifunctional chip. In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic circuit diagram of a four-channel multifunctional chip according to an embodiment of the present invention. As shown in fig. 1, a four-channel multifunction chip of this embodiment includes:
an input end RFin of the multifunctional chip, four output ends RFout1-RFout4 of the multifunctional chip, and a power supply end V of the multifunctional chipEEThe multi-functional chip comprises a grounding end GND, an amplifier, a grid end power supply end VG, a drain end power supply end VD, a one-to-four power divider, four phase shifters, three serial-parallel drivers, a DATA latch end LD, a DATA input end DATA, a clock end CLK and a chip selection end CS;
the four outputs of the multifunctional chip include a first output RFout1 of the multifunctional chip, a second output RFout2 of the multifunctional chip, a third output RFout3 of the multifunctional chip, and a fourth output RFout4 of the multifunctional chip;
the four phase shifters comprise a first phase shifter, a second phase shifter, a third phase shifter and a fourth phase shifter;
the three serial-to-parallel drivers comprise a first serial-to-parallel driver, a second serial-to-parallel driver and a third serial-to-parallel driver;
the amplifier is respectively connected with an input end RFin, a grid end power supply end VG, a drain end power supply end VD and a one-to-four power divider of the multifunctional chip;
the four-in-one power divider is respectively connected with a first phase shifter, a second phase shifter, a third phase shifter and a fourth phase shifter, the first phase shifter is connected with a first output end RFout1 of the multifunctional chip, the second phase shifter is connected with a second output end RFout2 of the multifunctional chip, the third phase shifter is connected with a third output end RFout3 of the multifunctional chip, and the fourth phase shifter is connected with a fourth output end RFout4 of the multifunctional chip;
the first serial-to-parallel driver is respectively connected with the second serial-to-parallel driver, the third serial-to-parallel driver and the power supply end V of the multifunctional chipEEThe second serial-to-parallel driver is connected with the third serial-to-parallel driver;
the third serial-parallel driver is connected with the first phase shifter and the second phase shifter, and the second serial-parallel driver is connected with the third phase shifter and the fourth phase shifter;
at least one of the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter includes a phase shift functional module including at least an attenuation circuit.
In one embodiment, the amplifier amplifies an input signal input through an input terminal RFin of the multifunction chip, the amplified input signal is distributed to a first phase shifter, a second phase shifter, a third phase shifter and a fourth phase shifter through a 1-4-division power divider, and the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter process the respective amplified input signals, wherein the phase shifters are in a digital control mode, the phase shift is performed by 5.625 °, and the phase shift range is 0 ° to 354.375 °.
Further, the first serial-parallel driver, the second serial-parallel driver and the third serial-parallel driver form a 24-serial-parallel driver, 24 paths of 0V/-5V complementary voltages are output, and 0V or-5V voltages are respectively provided for gates of the PHEMT devices in the four phase shifters. The first cascode driver is connected to external input terminals (a DATA latch terminal LD, a DATA input terminal DATA, a clock terminal CLK, and a chip select terminal CS) to implement input level shift and single-ended to differential functions. The second serial-to-parallel driver and the third serial-to-parallel driver are both 12-bit serial-to-parallel driver circuits, share a clock and latch, are cascaded to form a 24-bit serial-to-parallel driver circuit, and realize conversion from 24-bit serial codes to parallel codes at a specified time sequence; an input signal of a clock end CLK enters a first serial-parallel driver to generate differential signals 1 and 2 which are respectively input into a second serial-parallel driver and a third serial-parallel driver; an input signal of the data latch end LD enters a first serial-parallel driver to generate differential signals 3 and 4 which are respectively input into a second serial-parallel driver and a third serial-parallel driver; the input signal at DATA input terminal DATA enters the first deserializer driver to generate differential signals 5 and 6, enters the second deserializer driver, is output serially by the second deserializer driver to generate signals 7 and 8, and enters the third deserializer driver. The input signal of the chip select terminal CS enters the first cascode driver and performs a logic operation with the input signal of the clock terminal CLK to control the input signal of CLK.
In an embodiment, the attenuation circuit in the phase shift functional module arranged in at least one of the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter can effectively improve the voltage standing wave ratio of the output port connected with the corresponding phase shifter, so as to improve the performance of the multi-channel multifunctional chip.
The four-channel multifunctional chip of the embodiment of the invention comprises: the circuit comprises an input end of a multifunctional chip, four output ends of the multifunctional chip, a power supply end of the multifunctional chip, a grounding end of the multifunctional chip, an amplifier, a grid end power supply end, a drain end power supply end, a one-to-four power divider, four phase shifters, three serial-parallel drivers, a data latch end, a data input end, a clock end and a chip selection end, wherein the input end of the multifunctional chip is connected with the four output ends of the multifunctional chip; at least one of the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter includes a phase shift functional module including at least an attenuation circuit. The phase shifter is provided with the attenuation circuit to attenuate the output signal, so that the voltage standing wave ratio of the output port connected with the phase shifter is effectively improved, and the performance of the four-channel multifunctional chip is improved.
Fig. 2 is a circuit diagram of a four-channel multifunctional chip according to another embodiment of the invention. As shown in fig. 2, a four-channel multifunction chip of this embodiment includes:
an input end RFin of the multifunctional chip, four output ends RFout1-RFout4 of the multifunctional chip, and a power supply end V of the multifunctional chipEEThe multi-functional chip comprises a grounding end GND, an amplifier, a grid end power supply end VG, a drain end power supply end VD, a one-to-four power divider, four phase shifters, three serial-parallel drivers, a DATA latch end LD, a DATA input end DATA, a clock end CLK and a chip selection end CS;
the four outputs of the multifunctional chip include a first output RFout1 of the multifunctional chip, a second output RFout2 of the multifunctional chip, a third output RFout3 of the multifunctional chip, and a fourth output RFout4 of the multifunctional chip;
the four phase shifters comprise a first phase shifter, a second phase shifter, a third phase shifter and a fourth phase shifter;
the three serial-to-parallel drivers comprise a first serial-to-parallel driver, a second serial-to-parallel driver and a third serial-to-parallel driver;
a first input end 1 of the amplifier is connected with an input end RFin of the multifunctional chip, a second input end 2 of the amplifier is connected with a grid end power supply end VG, a third input end 3 of the amplifier is connected with a drain end power supply end VD, and an output end 4 of the amplifier is connected with an input end 1 of the one-to-four power divider;
a first output end 2 of the four-way power divider is connected with a first input end 1 of a first phase shifter, and an output end 3 of the first phase shifter is connected with a first output end RFout1 of the multifunctional chip; a second output end 3 of the one-fourth power divider is connected with a first input end 1 of a second phase shifter, and an output end 3 of the second phase shifter is connected with a second output end RFout2 of the multifunctional chip; a third output end 4 of the one-fourth power divider is connected with a first input end 1 of a third phase shifter, and an output end 3 of the third phase shifter is connected with a third output end RFout3 of the multifunctional chip; a fourth output end 5 of the one-fourth power divider is connected with a first input end 1 of a fourth phase shifter, and an output end 3 of the fourth phase shifter is connected with a fourth output end RFout4 of the multifunctional chip;
the pin 1 and the pin 7 of the first cascode driver are both connected to the ground terminal GND of the multifunctional chip, the pin 2 of the first cascode driver is connected to the clock terminal CLK, and the pin 3 of the first cascode driver is connected to the power supply terminal V of the functional chipEEPin 4 of the first cascode driver is connected to the chip select terminal CS, pin 5 of the first cascode driver is connected to the DATA input terminal DATA, pin 6 of the first cascode driver is connected to the DATA latch terminal LD, pin 8 of the first cascode driver is connected to pin 12 of the second cascode driver, pin 9 of the first cascode driver is connected to pin 11 of the second cascode driver, pin 10 of the first cascode driver is connected to pin 10 of the second cascode driver, pin 11 of the first cascode driver is connected to pin 9 of the second cascode driver, pin 12 of the first cascode driver is connected to pin 8 of the second cascode driver, pin 13 of the first cascode driver is connected to pin 7 of the second cascode driver, and pin 14 of the first cascode driver is connected to pin 14 of the second cascode driverPin 6, pin 15 of the first deserializer driver is connected with pin 5 of the second deserializer driver, pin 16 of the first deserializer driver is connected with pin 5 of the third deserializer driver, pin 17 of the first deserializer driver is connected with pin 4 of the third deserializer driver, pin 18 of the first deserializer driver is connected with pin 3 of the third deserializer driver, and pin 19 of the first deserializer driver is connected with pin 2 of the third deserializer driver;
a pin 6 of the third serial-to-parallel driver is connected with a pin 4 of the second serial-to-parallel driver, and a pin 7 of the third serial-to-parallel driver is connected with a pin 3 of the second serial-to-parallel driver;
a pin 8 of the third serial-parallel driver is connected with the second input end 2 of the first phase shifter, and a pin 1 of the third serial-parallel driver is connected with the second input end 2 of the second phase shifter; pin 2 of the second serial-parallel driver is connected with the second input end 2 of the third phase shifter, and pin 1 of the second serial-parallel driver is connected with the second input end 2 of the fourth phase shifter;
at least one of the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter includes a phase shift functional module including at least an attenuation circuit.
In an embodiment, the connection of the third serial-parallel driver to the first phase shifter and the second phase shifter may be in the form of a plurality of wire connections, and the specific number of the wire connections is not limited. Taking the number of leads equal to 5 as an example, when the third serial-parallel driver is connected to the first phase shifter, pin 8a of the third serial-parallel driver is connected to pin 2a of the first phase shifter, pin 8b of the third serial-parallel driver is connected to pin 2b of the first phase shifter, pin 8c of the third serial-parallel driver is connected to pin 2c of the first phase shifter, pin 8d of the third serial-parallel driver is connected to pin 2d of the first phase shifter, and pin 8e of the third serial-parallel driver is connected to pin 2e of the first phase shifter. Under the condition that the third serial-parallel driver is connected with the second phase shifter, a pin 1a of the third serial-parallel driver is connected with a pin 2a of the second phase shifter, a pin 1b of the third serial-parallel driver is connected with a pin 2b of the second phase shifter, a pin 1c of the third serial-parallel driver is connected with a pin 2c of the second phase shifter, a pin 1d of the third serial-parallel driver is connected with a pin 2d of the second phase shifter, and a pin 1e of the third serial-parallel driver is connected with a pin 2e of the second phase shifter.
As in the above embodiments, the connection between the second serial-parallel driver and the third phase shifter and the connection between the second serial-parallel driver and the fourth phase shifter may also be in the form of multiple wire connections, which are not described herein again.
In the prior art, the circuit structures of the phase shift functional modules of the four-channel multifunctional chip RFin-RFout1 channel, RFin-RFout2 channel, RFin-RFout3 channel, and RFin-RFout4 channel are prone to cause voltage standing wave ratio differences of four output ports of the four-channel multifunctional chip, thereby affecting the performance of the four-channel multifunctional chip, and the following description will take the circuit schematic diagram of the phase shift functional module in the prior art as an example.
FIG. 3 is a circuit diagram of a phase shift functional module of a four-channel multifunctional chip RFin-RFout1 channel in the prior art, which is composed of inductors Ind 1-Ind 7, capacitors C1-C6, resistors R1-R2 and PHEMT devices D1-D16. The IN port is connected to the first output terminal 2 of the 1-4 power divider IN the four-channel multifunctional chip, and the OUT port is the first output terminal RFout1 of the four-channel multifunctional chip. The capacitor C3-C5, the inductor Ind 5-Ind 7 and the PHEMT device D13-D16 form 180 degrees, the PHEMT device D12 is 5.625 degrees, the resistor R2, the inductor Ind4 and the PHEMT device D9-D11 form 22.5 degrees, the inductor Ind3 and the PHEMT device D8 form 11.25 degrees, the resistor R1, the inductor Ind2 and the PHEMT device D5-D7 form 45 degrees, the capacitor C1-C2, the inductor Ind1 and the PHEMT device D1-D4 form 90 degrees, and the specific power-up operation mode is shown in Table 1.
TABLE 1 PHEMT device grid voltage and phase shifter basic state comparison table
Reference state 5.625° 11.25° 22.5° 45° 90° 180° 354.375°
D1 0V 0V 0V 0V 0V -5V 0V -5V
D2 0V 0V 0V 0V 0V -5V 0V -5V
D3 -5V 0V 0V 0V 0V 0V 0V 0V
D4 -5V 0V 0V 0V 0V 0V 0V 0V
D5 0V 0V 0V 0V -5V 0V 0V -5V
D6 -5V 0V 0V 0V 0V 0V 0V 0V
D7 -5V 0V 0V 0V 0V 0V 0V 0V
D8 0V 0V -5V 0V 0V 0V 0V -5V
D9 0V 0V 0V -5V 0V 0V 0V -5V
D10 -5V 0V 0V 0V 0V 0V 0V 0V
D11 -5V 0V 0V 0V 0V 0V 0V 0V
D12 0V -5V 0V 0V 0V 0V 0V -5V
D13 -5V 0V 0V 0V 0V 0V 0V 0V
D14 -5V 0V 0V 0V 0V 0V 0V 0V
D15 0V 0V 0V 0V 0V 0V -5V -5V
D16 0V 0V 0V 0V 0V 0V -5V -5V
Fig. 4 is a circuit layout of a phase shift functional module of the channels of the four-channel multifunctional chip RFin-RFout1 in the prior art, and a capacitor C6 with a capacitance value of 0.58pF is arranged in a black frame. FIG. 5 is a diagram showing a test curve of voltage standing wave ratio of the first output port RFout1 of the four-channel multifunctional chip in the prior art, wherein the total number of the reference state and the phase-shifted state is 2 due to the 6-bit phase shifter with 5.625 degree step as the phase-shifting functional unit664 states, there are 64 voltage standing wave ratio curves. It can be seen from fig. 5 that the maximum value of all the voltage standing wave ratio curves reaches 2.6. FIG. 6 is a Smith chart test curve of RFout1 port impedance of the four-channel multifunctional chip under 64 states, the real part impedance of the circle center of the Smith chart is 50 Ω, and the corresponding voltage standing wave ratio is the best principleThe desired value is 1. Fig. 6 is a schematic diagram of a smith chart testing curve of impedance of the first output port RFout1 of the four-channel multifunctional chip in the prior art, and it can be seen from fig. 6 that a point farthest from the center of the smith chart is a point m1, and its partial impedance is 0.431 × 50 ═ 21.55 Ω, so that the voltage standing wave ratio at this point is the worst.
To the problem of the voltage standing wave ratio difference of four output ports of the multi-functional chip of four passageways among the prior art, this application provides an improved phase shift functional module, and wherein, improved phase shift functional module includes: the input end of the phase-shifting functional module, the phase-shifting circuit, the input end of the phase-shifting functional module and the output end of the phase-shifting functional module are sequentially connected. Wherein, decay circuit includes: and a pi-type fixed attenuator. The phase shift functional module is provided with the pi-shaped fixed attenuator, so that the voltage standing wave ratio of the output port of the multifunctional chip can be effectively improved.
Fig. 7 is a circuit diagram of an improved phase shift functional module according to an embodiment of the present invention.
As shown in fig. 7, the circuit of an improved phase shift functional module of this embodiment includes:
a third resistor R3, a fourth resistor R4, a fifth resistor R5, and a first ground GND 1; a first end of the third resistor R3 is connected to a first end of the fifth resistor R5, a second end of the fifth resistor R5 is connected to a first ground terminal, the first ground terminal is further connected to a first end of the fourth resistor R4, and a second end of the fourth resistor R4 is connected to a second end of the third resistor R3;
a first resistor R, a second resistor R, a first capacitor C, a second capacitor C, a third capacitor C, a fourth capacitor C, a fifth capacitor C, a first inductor Ind, a second inductor Ind, a third inductor Ind, a fourth inductor Ind, a fifth inductor Ind, a sixth inductor Ind, a seventh inductor Ind, a first PHEMT D, a second PHEMT D, a third PHEMT D, a fourth PHEMT D, a fifth PHEMT D, a sixth PHEMT D, a seventh PHEMT D, an eighth PHEMT D, a ninth PHEMT D, a tenth PHEMT D, an eleventh PHEMT D, a twelfth PHEMT D, a thirteenth PHEMT D, a fourteenth PHEMT D, a fifteenth PHEMT D, a sixteenth PHEMT D, a second ground terminal, a third ground terminal, a fourth GND terminal, a fifth ground terminal, a sixth ground terminal, and a seventh ground terminal GND;
a first end S of a fourteenth PHEMT D14 is connected to a first end of a fourth capacitor C4, a second end of a fourth capacitor C4 is connected to a first end of a seventh inductor Ind7 and a first end of a third capacitor C3, respectively, a second end of a seventh inductor Ind7 is connected to a second ground GND2, a second end of a third capacitor C3 is connected to a first end S of a thirteenth PHEMT D13, a second end D of a thirteenth PHEMT D13 is connected to a first end D of a twelfth PHEMT D12 and a first end D of a fifteenth PHEMT D15, a second end S of a fifteenth PHEMT D15 is connected to a first end of a fifth inductor Ind5, a second end of a fifth inductor Ind5 is connected to a first end of a sixth inductor Ind6 and a first end of a fifth capacitor, a second end of the fifth capacitor is connected to the third ground, a second end of the sixth inductor Ind6 is connected to a second end S16, and a second end of the fourteenth PHEMT 14 is connected to a second end S16;
a second end S of a twelfth PHEMT D12 is connected to a first end D of a ninth PHEMT D9, a third end M of the ninth PHEMT D9 is connected to a first end D of a tenth PHEMT D10 and a first end of a second resistor R2, respectively, a second end S of a tenth PHEMT D10 is connected to a first end S of an eleventh PHEMT D11 and a second end of a second resistor R2, respectively, a second end of the second resistor R2 is further connected to a first end of a fourth inductor Ind4, and a second end of the fourth inductor Ind4 and a second end D of the eleventh PHEMT D11 are both connected to a fourth ground terminal GND 4;
a second terminal S of the ninth PHEMT D9 is connected to the first terminal D of the eighth PHEMT D8, a third terminal M of the eighth PHEMT D8 is connected to the first terminal of the third inductor Ind3, and a second terminal of the third inductor Ind3 is connected to the fifth ground GND 5;
a second end S of the eighth PHEMT D8 is connected to a first end D of a fifth PHEMT D5, a third end M of the fifth PHEMT D5 is connected to a first end D of a sixth PHEMT D6 and a first end of a first resistor R1, respectively, a second end S of the sixth PHEMT D6 is connected to a first end S of a seventh PHEMT D7 and a second end of a first resistor R1, respectively, the second end of the first resistor R1 is further connected to a first end of a second inductor Ind2, and the second end D of the seventh PHEMT D7 and the second end of the second inductor Ind2 are both connected to a sixth ground terminal GND 6;
a second end S of a fifth PHEMT D5 is connected to a first end D of a second PHEMT D2, a second end S of a second PHEMT D2 is connected to a first end of a second capacitor C2, a second end of the second capacitor C2 is connected to a first end of a first capacitor C1 and a first end of a first inductor Ind1, respectively, a second end of the first inductor Ind1 is connected to a seventh ground GND7, a second end of the first capacitor C1 is connected to a first end S of the first PHEMT D1, a second end D of the first PHEMT D1 is connected to a first end D of a third PHEMT D3, a second end S of the third PHEMT D3 is connected to a first end S of a fourth PHEMT D4, and a second end D of the fourth PHEMT D4 is connected to a first end D of the second PHEMT D2;
the input terminal IN of the phase shift functional module is connected to the second terminal D of the first PHEMT D1, the second terminal D of the fourteenth PHEMT D14 is connected to the second terminal of the third resistor R3, and the first terminal of the third resistor R3 is connected to the output terminal OUT of the phase shift functional module.
As can be seen from fig. 7, in order to improve the voltage standing wave ratio of the RFout1 port, the capacitor C6 in fig. 3 is replaced by a pi-type fixed attenuator composed of R3 to R5 in fig. 7, where R3 is 10 Ω, R4 is 2900 Ω, and R5 is 2460 Ω. Fig. 8 is a circuit layout of the improved multi-function chip RFin-RFout1 channel phase shift functional module, and comparing fig. 4 and fig. 8, it can be seen that the layout in the black frame is replaced by a pi-type fixed attenuator formed by a capacitor C6 and resistors R3-R5.
FIG. 9 is a test curve of the voltage standing wave ratio of the port of the improved multifunctional chip RFout1 in 64 states, wherein the maximum value of the voltage standing wave ratio is 1.8; fig. 10 is a smith chart test curve of the RFout1 port impedance of the improved multifunction chip in 64 states, and it can be seen that the real impedance at point m1, which is farthest from the center of the smith chart, in all the curves is 0.726 × 50 — 36.3 Ω, which is closer to the center of the smith chart than 21.55 Ω before the improvement.
The phase shift functional units in the RFin-RFout2, RFin-RFout3 and RFin-RFout4 channels are the same as the phase shift functional units in the RFin-RFout1 channels, and the voltage standing wave ratios of the RFout2, RFout3 and RFout4 ports can be improved in the same way.
As can be seen by comparing fig. 5, 6, 9 and 10, the port voltage standing wave ratio can be effectively improved by replacing the capacitor with the pi-type fixed attenuator formed by the resistor and changing the port real part impedance of the circuit.
IN an embodiment, referring to fig. 2, an input terminal IN of the phase shift functional module is connected to an output port of the 1-to-4 power divider of the multifunctional chip, and an output terminal OUT of the phase shift functional module is an output port of the multifunctional chip.
Specifically, IN the case where the phase shift functional module is disposed IN the first phase shifter, the input terminal IN of the phase shift functional module is connected to the first output port 2 of the 1-to-4 power divider of the multifunctional chip, and the output terminal OUT of the phase shift functional module is the first output port RFout1 of the multifunctional chip. For the second phase shifter, the third phase shifter and the fourth phase shifter, the phase shift functional module is arranged, and the connection relationship between the input end IN of the phase shift functional module and the output end OUT of the phase shift functional module is the same as the principle, which is not described herein again.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.

Claims (10)

1.一种四通道多功能芯片，其特征在于，包括：1. a four-channel multifunctional chip, is characterized in that, comprises: 多功能芯片的输入端、多功能芯片的四个输出端、多功能芯片的供电端、多功能芯片的接地端、放大器、栅端供电端、漏端供电端、一分四功分器、四个移相器、三个串转并驱动器、数据锁存端、数据输入端、时钟端和片选端；The input terminal of the multifunctional chip, the four output terminals of the multifunctional chip, the power supply terminal of the multifunctional chip, the ground terminal of the multifunctional chip, the amplifier, the power supply terminal of the gate terminal, the power supply terminal of the drain terminal, the one-to-four power divider, the four A phase shifter, three serial-to-parallel drivers, a data latch terminal, a data input terminal, a clock terminal and a chip select terminal; 所述多功能芯片的四个输出端包括多功能芯片的第一输出端、多功能芯片的第二输出端、多功能芯片的第三输出端和多功能芯片的第四输出端；The four output terminals of the multifunctional chip include a first output terminal of the multifunctional chip, a second output terminal of the multifunctional chip, a third output terminal of the multifunctional chip, and a fourth output terminal of the multifunctional chip; 所述四个移相器包括第一移相器、第二移相器、第三移相器和第四移相器；The four phase shifters include a first phase shifter, a second phase shifter, a third phase shifter and a fourth phase shifter; 所述三个串转并驱动器包括第一串转并驱动器、第二串转并驱动器和第三串转并驱动器；The three serial-to-parallel drivers include a first serial-to-parallel driver, a second serial-to-parallel driver, and a third serial-to-parallel driver; 所述放大器分别连接所述多功能芯片的输入端、所述栅端供电端、所述漏端供电端和所述一分四功分器；The amplifier is respectively connected to the input end of the multi-function chip, the power supply end of the gate end, the power supply end of the drain end and the one-to-four power divider; 所述一分四功分器分别连接所述第一移相器、所述第二移相器、所述第三移相器和所述第四移相器，所述第一移相器连接所述多功能芯片的第一输出端，所述第二移相器连接所述多功能芯片的第二输出端，所述第三移相器连接所述多功能芯片的第三输出端，所述第四移相器连接所述多功能芯片的第四输出端；The one-to-four power divider is respectively connected to the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter, and the first phase shifter is connected to The first output terminal of the multifunctional chip, the second phase shifter is connected to the second output terminal of the multifunctional chip, and the third phase shifter is connected to the third output terminal of the multifunctional chip, so the the fourth phase shifter is connected to the fourth output end of the multi-function chip; 所述第一串转并驱动器分别连接所述第二串转并驱动器、所述第三串转并驱动器、所述功能芯片的供电端、所述多功能芯片的接地端、所述数据锁存端、所述数据输入端、所述时钟端和所述片选端，所述第二串转并驱动器与所述第三串转并驱动器连接；The first serial-to-parallel driver is respectively connected to the second serial-to-parallel driver, the third serial-to-parallel driver, the power supply terminal of the functional chip, the ground terminal of the multifunctional chip, and the data latch terminal, the data input terminal, the clock terminal and the chip selection terminal, the second serial-to-parallel driver is connected to the third serial-to-parallel driver; 所述第三串转并驱动器连接所述第一移相器和所述第二移相器，所述第二串转并驱动器连接所述第三移相器和所述第四移相器；The third serial-to-parallel driver is connected to the first phase shifter and the second phase shifter, and the second serial-to-parallel driver is connected to the third phase shifter and the fourth phase shifter; 所述第一移相器、第二移相器、第三移相器和第四移相器中的至少之一包括移相功能模块，所述移相功能模块至少包括衰减电路。At least one of the first phase shifter, the second phase shifter, the third phase shifter and the fourth phase shifter includes a phase shifting function module, and the phase shifting function module at least includes an attenuation circuit. 2.如权利要求1所述的四通道多功能芯片，其特征在于，所述移相功能模块还包括：2. The four-channel multifunctional chip according to claim 1, wherein the phase-shifting functional module further comprises: 移相电路、移相功能模块的输入端和移相功能模块的输出端，所述移相功能模块的输入端、所述移相电路、所述衰减电路和所述移相功能模块的输出端依次连接。A phase-shift circuit, the input end of the phase-shift function module, and the output end of the phase-shift function module, the input end of the phase-shift function module, the phase-shift circuit, the attenuation circuit, and the output end of the phase-shift function module Connect in sequence. 3.如权利要求2所述的四通道多功能芯片，其特征在于，所述衰减电路包括：3. The four-channel multi-function chip according to claim 2, wherein the attenuation circuit comprises: π型固定衰减器。Pi-type fixed attenuator. 4.如权利要求3所述的四通道多功能芯片，其特征在于，所述π型固定衰减器包括：4. The four-channel multifunctional chip according to claim 3, wherein the π-type fixed attenuator comprises: 第三电阻、第四电阻、第五电阻和第一接地端；a third resistor, a fourth resistor, a fifth resistor and a first ground terminal; 所述第三电阻的第一端与所述第五电阻的第一端连接，所述第五电阻的第二端与所述第一接地端连接，所述第一接地端还与所述第四电阻的第一端连接，所述第四电阻的第二端与所述第三电阻的第二端连接。The first end of the third resistor is connected to the first end of the fifth resistor, the second end of the fifth resistor is connected to the first ground terminal, and the first ground terminal is also connected to the first ground terminal. The first end of the four resistors is connected, and the second end of the fourth resistor is connected with the second end of the third resistor. 5.如权利要求2所述的四通道多功能芯片，其特征在于，所述移相电路包括：5. The four-channel multifunctional chip of claim 2, wherein the phase-shift circuit comprises: 第一电阻、第二电阻、第一电容、第二电容、第三电容、第四电容、第五电容、第一电感、第二电感、第三电感、第四电感、第五电感、第六电感、第一PHEMT、第二PHEMT、第三PHEMT、第四PHEMT、第五PHEMT、第六PHEMT、第七PHEMT、第八PHEMT、第九PHEMT、第十PHEMT、第十一PHEMT、第十二PHEMT、第十三PHEMT、第十四PHEMT、第十五PHEMT、第十六PHEMT、第二接地端、第三接地端、第四接地端、第五接地端、第六接地端和第七接地端；First resistor, second resistor, first capacitor, second capacitor, third capacitor, fourth capacitor, fifth capacitor, first inductor, second inductor, third inductor, fourth inductor, fifth inductor, sixth Inductance, First PHEMT, Second PHEMT, Third PHEMT, Fourth PHEMT, Fifth PHEMT, Sixth PHEMT, Seventh PHEMT, Eighth PHEMT, Ninth PHEMT, Tenth PHEMT, Eleventh PHEMT, Twelfth PHEMT PHEMT, Thirteenth PHEMT, Fourteenth PHEMT, Fifteenth PHEMT, Sixteenth PHEMT, Second Ground, Third Ground, Fourth Ground, Fifth Ground, Sixth Ground, and Seventh Ground end; 所述第十四PHEMT的第一端连接所述第四电容的第一端，所述第四电容的第二端分别连接所述第七电感第一端和所述第三电容的第一端，所述第七电感第二端连接所述第二接地端，所述第三电容的第二端连接所述第十三PHEMT的第一端，所述第十三PHEMT的第二端分别连接所述第十二PHEMT的第一端和所述第十五PHEMT的第一端，所述第十五PHEMT的第二端连接所述第五电感的第一端，所述第五电感的第二端分别连接所述第六电感的第一端和所述第五电容的第一端，所述第五电容的第二端连接所述第三接地端，所述第六电感的第二端连接所述第十六PHEMT的第一端，所述第十六PHEMT的第二端连接所述第十四PHEMT的第二端；The first end of the fourteenth PHEMT is connected to the first end of the fourth capacitor, and the second end of the fourth capacitor is respectively connected to the first end of the seventh inductor and the first end of the third capacitor , the second end of the seventh inductor is connected to the second ground end, the second end of the third capacitor is connected to the first end of the thirteenth PHEMT, and the second ends of the thirteenth PHEMT are respectively connected The first end of the twelfth PHEMT and the first end of the fifteenth PHEMT, the second end of the fifteenth PHEMT is connected to the first end of the fifth inductor, and the first end of the fifth inductor is connected. The two terminals are respectively connected to the first terminal of the sixth inductor and the first terminal of the fifth capacitor, the second terminal of the fifth capacitor is connected to the third ground terminal, and the second terminal of the sixth inductor connecting the first end of the sixteenth PHEMT, and the second end of the sixteenth PHEMT connecting the second end of the fourteenth PHEMT; 所述第十二PHEMT的第二端连接所述第九PHEMT的第一端，所述第九PHEMT的第三端分别连接所述第十PHEMT的第一端和所述第二电阻的第一端，所述第十PHEMT的第二端分别连接所述第十一PHEMT的第一端和所述第二电阻的第二端，所述第二电阻的第二端还连接所述第四电感的第一端，所述第四电感的第二端和所述第十一PHEMT的第二端均连接第四接地端；The second end of the twelfth PHEMT is connected to the first end of the ninth PHEMT, and the third end of the ninth PHEMT is respectively connected to the first end of the tenth PHEMT and the first end of the second resistor. terminal, the second terminal of the tenth PHEMT is respectively connected to the first terminal of the eleventh PHEMT and the second terminal of the second resistor, and the second terminal of the second resistor is also connected to the fourth inductor The first end of the fourth inductor and the second end of the eleventh PHEMT are both connected to the fourth ground; 所述第九PHEMT的第二端连接所述第八PHEMT的第一端，所述第八PHEMT的第三端连接所述第三电感的第一端，所述第三电感的第二端连接所述第五接地端；The second end of the ninth PHEMT is connected to the first end of the eighth PHEMT, the third end of the eighth PHEMT is connected to the first end of the third inductor, and the second end of the third inductor is connected the fifth ground terminal; 所述第八PHEMT的第二端连接所述第五PHEMT的第一端，所述第五PHEMT的第三端分别连接所述第六PHEMT的第一端和所述第一电阻的第一端，所述第六PHEMT的第二端分别连接所述第七PHEMT的第一端和所述第一电阻的第二端，所述第一电阻的第二端还连接所述第二电感的第一端，所述第七PHEMT的第二端和所述第二电感的第二端均连接所述第六接地端；The second end of the eighth PHEMT is connected to the first end of the fifth PHEMT, and the third end of the fifth PHEMT is respectively connected to the first end of the sixth PHEMT and the first end of the first resistor , the second end of the sixth PHEMT is respectively connected to the first end of the seventh PHEMT and the second end of the first resistor, and the second end of the first resistor is also connected to the first end of the second inductor one end, the second end of the seventh PHEMT and the second end of the second inductor are both connected to the sixth ground end; 所述第五PHEMT的第二端连接所述第二PHEMT的第一端，所述第二PHEMT的第二端连接所述第二电容的第一端，所述第二电容的第二端分别连接所述第一电容的第一端和所述第一电感的第一端，所述第一电感的第二端连接所述第七接地端，所述第一电感的第一端连接所述第一PHEMT的第一端，所述第一PHEMT的第二端连接所述第三PHEMT的第一端，所述第三PHEMT的第二端连接所述第四PHEMT的第一端，所述第四PHEMT的第二端连接所述第二PHEMT的第一端。The second end of the fifth PHEMT is connected to the first end of the second PHEMT, the second end of the second PHEMT is connected to the first end of the second capacitor, and the second ends of the second capacitor are respectively connecting the first end of the first capacitor and the first end of the first inductor, the second end of the first inductor is connected to the seventh ground terminal, and the first end of the first inductor is connected to the The first end of the first PHEMT, the second end of the first PHEMT is connected to the first end of the third PHEMT, the second end of the third PHEMT is connected to the first end of the fourth PHEMT, the The second end of the fourth PHEMT is connected to the first end of the second PHEMT. 6.如权利要求4或5所述的四通道多功能芯片，其特征在于，还包括：6. The four-channel multifunctional chip according to claim 4 or 5, further comprising: 所述移相功能模块的输入端连接所述第一PHEMT的第二端，所述第十四PHEMT的第二端连接所述第三电阻的第二端，所述第三电阻的第一端连接所述移相功能模块的输出端。The input end of the phase shift function module is connected to the second end of the first PHEMT, the second end of the fourteenth PHEMT is connected to the second end of the third resistor, and the first end of the third resistor Connect to the output terminal of the phase-shifting function module. 7.如权利要求1所述的四通道多功能芯片，其特征在于，所述放大器分别连接所述多功能芯片的输入端、所述栅端供电端、所述漏端供电端和所述一分四功分器，包括：7 . The four-channel multi-function chip according to claim 1 , wherein the amplifier is respectively connected to the input terminal of the multi-function chip, the power supply terminal of the gate terminal, the power supply terminal of the drain terminal and the one Divider of four powers, including: 所述放大器的第一输入端连接所述多功能芯片的输入端，所述放大器的第二输入端连接所述栅端供电端，所述放大器的第三输入端连接所述漏端供电端，所述放大器的输出端连接所述一分四功分器的输入端。The first input terminal of the amplifier is connected to the input terminal of the multi-function chip, the second input terminal of the amplifier is connected to the power supply terminal of the gate terminal, and the third input terminal of the amplifier is connected to the power supply terminal of the drain terminal, The output end of the amplifier is connected to the input end of the one-to-four power divider. 8.如权利要求1所述的四通道多功能芯片，其特征在于，所述一分四功分器分别连接所述第一移相器、所述第二移相器、所述第三移相器和所述第四移相器，所述第一移相器连接所述多功能芯片的第一输出端，所述第二移相器连接所述多功能芯片的第二输出端，所述第三移相器连接所述多功能芯片的第三输出端，所述第四移相器连接所述多功能芯片的第四输出端，包括：8 . The four-channel multifunctional chip according to claim 1 , wherein the one-to-four power divider is respectively connected to the first phase shifter, the second phase shifter, and the third phase shifter. 9 . and the fourth phase shifter, the first phase shifter is connected to the first output end of the multi-function chip, the second phase shifter is connected to the second output end of the multi-function chip, so The third phase shifter is connected to the third output terminal of the multifunctional chip, and the fourth phase shifter is connected to the fourth output terminal of the multifunctional chip, including: 所述一分四功分器的第一输出端连接所述第一移相器的第一输入端，所述第一移相器的输出端连接所述多功能芯片的第一输出端；The first output end of the one-to-four power divider is connected to the first input end of the first phase shifter, and the output end of the first phase shifter is connected to the first output end of the multifunctional chip; 所述一分四功分器的第二输出端连接所述第二移相器的第一输入端，所述第二移相器的输出端连接所述多功能芯片的第二输出端；The second output end of the one-to-four power divider is connected to the first input end of the second phase shifter, and the output end of the second phase shifter is connected to the second output end of the multifunctional chip; 所述一分四功分器的第三输出端连接所述第三移相器的第一输入端，所述第三移相器的输出端连接所述多功能芯片的第三输出端；The third output end of the one-to-four power divider is connected to the first input end of the third phase shifter, and the output end of the third phase shifter is connected to the third output end of the multifunctional chip; 所述一分四功分器的第四输出端连接所述第四移相器的第一输入端，所述第四移相器的输出端连接所述多功能芯片的第四输出端。The fourth output end of the one-to-four power divider is connected to the first input end of the fourth phase shifter, and the output end of the fourth phase shifter is connected to the fourth output end of the multifunctional chip. 9.如权利要求1所述的四通道多功能芯片，其特征在于，所述第一串转并驱动器分别连接所述第二串转并驱动器、所述第三串转并驱动器、所述功能芯片的供电端、所述多功能芯片的接地端、所述数据锁存端、所述数据输入端、所述时钟端和所述片选端，所述第二串转并驱动器与所述第三串转并驱动器连接，包括：9 . The four-channel multi-function chip of claim 1 , wherein the first serial-to-parallel driver is respectively connected to the second serial-to-parallel driver, the third serial-to-parallel driver, the function The power supply terminal of the chip, the ground terminal of the multi-function chip, the data latch terminal, the data input terminal, the clock terminal and the chip select terminal, the second serial-to-parallel driver and the first Three serial-to-parallel drive connections, including: 所述第一串转并驱动器的引脚1和引脚7均连接所述多功能芯片的接地端，所述第一串转并驱动器的引脚2连接所述时钟端，所述第一串转并驱动器的引脚3连接所述功能芯片的供电端，所述第一串转并驱动器的引脚4连接所述片选端，所述第一串转并驱动器的引脚5连接所述数据输入端，所述第一串转并驱动器的引脚6连接所述数据锁存端，所述第一串转并驱动器的引脚8连接所述第二串转并驱动器的引脚12，所述第一串转并驱动器的引脚9连接所述第二串转并驱动器的引脚11，所述第一串转并驱动器的引脚10连接所述第二串转并驱动器的引脚10，所述第一串转并驱动器的引脚11连接所述第二串转并驱动器的引脚9，所述第一串转并驱动器的引脚12连接所述第二串转并驱动器的引脚8，所述第一串转并驱动器的引脚13连接所述第二串转并驱动器的引脚7，所述第一串转并驱动器的引脚14连接所述第二串转并驱动器的引脚6，所述第一串转并驱动器的引脚15连接所述第二串转并驱动器的引脚5，所述第一串转并驱动器的引脚16连接所述第三串转并驱动器的引脚5，所述第一串转并驱动器的引脚17连接所述第三串转并驱动器的引脚4，所述第一串转并驱动器的引脚18连接所述第三串转并驱动器的引脚3，所述第一串转并驱动器的引脚19连接所述第三串转并驱动器的引脚2；Pin 1 and pin 7 of the first serial-to-parallel driver are both connected to the ground terminal of the multi-function chip, pin 2 of the first serial-to-parallel driver is connected to the clock terminal, and the first serial-to-parallel driver is connected to the clock terminal. The pin 3 of the parallel-to-parallel driver is connected to the power supply terminal of the functional chip, the pin 4 of the first serial-to-parallel driver is connected to the chip selection terminal, and the pin 5 of the first serial-to-parallel driver is connected to the described chip selection terminal. The data input terminal, the pin 6 of the first serial-to-parallel driver is connected to the data latch terminal, the pin 8 of the first serial-to-parallel driver is connected to the pin 12 of the second serial-to-parallel driver, The pin 9 of the first serial-to-parallel driver is connected to the pin 11 of the second serial-to-parallel driver, and the pin 10 of the first serial-to-parallel driver is connected to the pin of the second serial-to-parallel driver 10. The pin 11 of the first serial-to-parallel driver is connected to the pin 9 of the second serial-to-parallel driver, and the pin 12 of the first serial-to-parallel driver is connected to the second serial-to-parallel driver. Pin 8, the pin 13 of the first serial-to-parallel driver is connected to the pin 7 of the second serial-to-parallel driver, and the pin 14 of the first serial-to-parallel driver is connected to the second serial-to-parallel driver. The pin 6 of the driver, the pin 15 of the first serial-to-parallel driver is connected to the pin 5 of the second serial-to-parallel driver, and the pin 16 of the first serial-to-parallel driver is connected to the third serial The pin 5 of the serial-to-parallel driver, the pin 17 of the first serial-to-parallel driver is connected to the pin 4 of the third serial-to-parallel driver, and the pin 18 of the first serial-to-parallel driver is connected to the third serial-to-parallel driver. The pin 3 of the three serial-to-parallel drivers, the pin 19 of the first serial-to-parallel driver is connected to the pin 2 of the third serial-to-parallel driver; 所述第三串转并驱动器的引脚6连接所述第二串转并驱动器的引脚4，所述第三串转并驱动器的引脚7连接所述第二串转并驱动器的引脚3。The pin 6 of the third serial-to-parallel driver is connected to the pin 4 of the second serial-to-parallel driver, and the pin 7 of the third serial-to-parallel driver is connected to the pin of the second serial-to-parallel driver 3. 10.如权利要求1所述的四通道多功能芯片，其特征在于，所述第三串转并驱动器连接所述第一移相器和所述第二移相器，所述第二串转并驱动器连接所述第三移相器和所述第四移相器，包括：10 . The four-channel multifunctional chip according to claim 1 , wherein the third serial-to-parallel driver is connected to the first phase shifter and the second phase shifter, and the second serial-to-parallel driver is connected to the second phase shifter. 11 . And the driver connects the third phase shifter and the fourth phase shifter, including: 所述第三串转并驱动器的引脚8连接所述第一移相器的第二输入端，所述第三串转并驱动器的引脚1连接所述第二移相器的第二输入端；The pin 8 of the third serial-to-parallel driver is connected to the second input of the first phase shifter, and the pin 1 of the third serial-to-parallel driver is connected to the second input of the second phase shifter end; 所述第二串转并驱动器的引脚2连接所述第三移相器的第二输入端，所述第二串转并驱动器的引脚1连接所述第四移相器的第二输入端。The pin 2 of the second serial-to-parallel driver is connected to the second input of the third phase shifter, and the pin 1 of the second serial-to-parallel driver is connected to the second input of the fourth phase shifter end.
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