CN113556090A - Linearity optimization circuit and low noise amplifier including the same - Google Patents
Linearity optimization circuit and low noise amplifier including the same Download PDFInfo
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- CN113556090A CN113556090A CN202110859664.3A CN202110859664A CN113556090A CN 113556090 A CN113556090 A CN 113556090A CN 202110859664 A CN202110859664 A CN 202110859664A CN 113556090 A CN113556090 A CN 113556090A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/193—High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
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Abstract
The invention provides a linearity optimization circuit and a low noise amplifier comprising the same, wherein the low noise amplifier comprises: the circuit includes an amplifier circuit configured to receive a radio frequency input signal and output a radio frequency output signal, and a linearity optimization circuit connected to the amplifier circuit and configured to programmably compensate for linearity of the amplifier circuit by adjusting a bias current therein.
Description
Technical Field
The present invention relates to a Low Noise Amplifier (LNA), and in particular, to a low noise amplifier including a linearity optimizing circuit for the low noise amplifier.
Background
With the rapid development of the communication market, the rf front-end receiver also develops toward high performance, high integration, and low power consumption. The low noise amplifier is the foremost end of the radio frequency receiving chain, and the performance of the low noise amplifier directly influences the performance of the whole receiver. In 5G rf applications, the lna requires an Automatic Gain Control (AGC) function, for example, the lna requires 7 gain steps to correspond to different signal strengths so as to keep the output signal strength relatively stable. The linearity of the low noise amplifier determines when the low noise amplifier switches gain steps, and the low noise amplifier with higher linearity can work under higher gain under the input signal with fixed power, so that the noise of a following circuit can be better inhibited, and the receiving performance of the receiver is improved.
The current low noise amplifier is mainly of a cascode (cascode) structure, a high gain is required to suppress noise of a subsequent link to obtain good communication quality, and the high gain requires a large amplifying tube and a transistor for the cascode structure, and a large MOS tube introduces a large nonlinear capacitance, thereby reducing the linearity of the LNA.
Furthermore, the linearity of the conventional low noise amplifier LNA is too low. Therefore, as the input signal increases, the LNA can be switched to the low gain position too early, so that the noise suppression capability of the circuit behind the LNA is reduced due to the lower gain, thereby increasing the noise of the receiving link and reducing the communication quality.
Disclosure of Invention
One aspect of the present invention provides a low noise amplifier, including: the circuit includes an amplifier circuit configured to receive a radio frequency input signal and output a radio frequency output signal, and a linearity optimization circuit connected to the amplifier circuit and configured to programmably compensate for linearity of the amplifier circuit by adjusting a bias current therein.
Another aspect of the invention proposes a low noise amplifier, wherein the amplifier circuit comprises a cascode amplifier.
Another aspect of the present invention provides a low noise amplifier, wherein the cascode amplifier includes: a first capacitor C1, a second capacitor C2, a first transistor M1, a second transistor M2, a first resistor R1, a first inductor L1, and a second inductor L2, wherein the first capacitor C1 is connected between the radio frequency input port and the gate of the first transistor M1; one end of the first resistor R1 is connected to the gate of the first transistor M1, and the other end thereof is connected to the first input voltage vb 1; the source of the first transistor M1 is connected to one end of a first inductor L1, and the drain thereof is connected to the source of a second transistor M2; one end of the first inductor L1 is connected with the source of the first transistor M1, and the other end thereof is connected to a ground node; the gate of the second transistor M2 is connected to a second input voltage vb2, the source of the second transistor M2 is connected to the drain of the first transistor M1, and the drain of the second transistor M2 is connected between a second capacitor C2 and a second inductor L2; one end of the second capacitor C2 is connected to the drain of the second transistor M2, and the other end thereof is connected to the radio frequency output port; and one end of the second inductor L2 is connected to the drain of the second transistor M2, and the other end thereof is connected to the power supply voltage VDD.
Another aspect of the present invention provides a low noise amplifier, wherein the linearity optimization circuit includes a current mirror circuit including a current source and n mirror current branches, wherein the linearity optimization circuit is configured to programmably control on and off of the n mirror current branches to provide a bias current, where n is a natural number greater than or equal to 2.
Another aspect of the present invention provides a low noise amplifier, wherein the current mirror circuit includes a third transistor M3, a fourth transistor M4, an eleventh transistor M11 and a current source Ib, wherein the source of the third transistor M3 is grounded, and the gate and the drain thereof are connected to connect to the switching tube connected to the amplifier circuit and the drain of the fourth transistor M4, respectively; the gate of the fourth transistor M4 is connected to the gate of the eleventh transistor M11, and the source thereof is connected to the power supply voltage VDD; the eleventh transistor M11 has a source connected to the power supply voltage VDD, a gate connected to the drain, and connected to the current source Ib to receive a current therefrom.
Another aspect of the present invention provides a low noise amplifier, wherein n is 3, wherein the first mirror current branch includes a fifth transistor M5 and an eighth transistor M8, a source of the fifth transistor M5 is connected to the power voltage VDD, and a drain thereof is connected to a source of the eighth transistor M8, a gate of the transistor M8 is connected to the first control terminal, and a drain thereof is connected to a drain of the transistor M3; the second mirror current branch comprises a sixth transistor M6 and a ninth transistor M9, said sixth transistor M6 having a source connected to the supply voltage VDD and a drain connected to the source of the ninth transistor M9, said ninth transistor M9 having a gate connected to the second control terminal and a drain connected to the drain of said transistor M3, the third mirror current branch comprises a seventh transistor M7 and a tenth transistor M10, said seventh transistor M7 having a source connected to the supply voltage VDD and a drain connected to the source of the tenth transistor M10, said tenth transistor M10 having a gate connected to the third control terminal and a drain connected to the drain of the transistor M3.
Another aspect of the present invention provides a low noise amplifier, wherein the source of the switching tube is connected to the gate of the third transistor M3, the gate thereof is connected to a third input voltage and the drain thereof is connected to a third capacitor, and wherein one end of the third capacitor is connected to the drain of the switching tube and the other end thereof is connected to the drain of the first transistor M1.
Another aspect of the present invention is to provide a low noise amplifier, wherein the third transistor M3 is a transistor of the same type as the first transistor M1 and having the same single transistor size.
Another aspect of the present invention provides a low noise amplifier, wherein the number of fingers of the third transistor M3 is one tenth of that of the first transistor M1.
Another aspect of the present invention proposes a low noise amplifier, wherein the low noise amplifier includes at least one of an HBT transistor, a CMOS transistor, a BJT transistor, a BiCMOS transistor, and a GaN transistor.
Drawings
FIG. 1 is a block diagram illustrating one example of a low noise amplifier LNA in accordance with an embodiment of the invention;
fig. 2 is a circuit diagram showing an example of a low noise amplifier according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating simulation results of the IIP3 of a low noise amplifier according to an embodiment of the present invention; and
fig. 4 is a diagram illustrating another simulation result of the IIP3 of the low noise amplifier according to an embodiment of the present invention.
Detailed Description
Before proceeding with the following detailed description, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document. The terms "couple," "connect," and derivatives thereof refer to any direct or indirect communication or connection between two or more elements, whether or not those elements are in physical contact with one another. The terms "transmit," "receive," and "communicate," as well as derivatives thereof, encompass both direct and indirect communication. The terms "include" and "comprise," as well as derivatives thereof, mean inclusion without limitation. The term "or" is inclusive, meaning and/or. The phrase "associated with … …" and derivatives thereof means including, included within … …, interconnected, contained within … …, connected or connected with … …, coupled or coupled with … …, in communication with … …, mated, interwoven, juxtaposed, proximate, bound or bound with … …, having an attribute, having a relationship or having a relationship with … …, and the like. The term "controller" refers to any device, system, or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or a combination of hardware and software and/or firmware. The functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. The phrase "at least one of, when used with a list of items, means that a different combination of one or more of the listed items can be used and only one item in the list may be required. For example, "at least one of A, B, C" includes any one of the following combinations: A. b, C, A and B, A and C, B and C, A and B and C.
Definitions for other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.
In this patent document, the application combination of modules and the division levels of sub-modules are only used for illustration, and the application combination of modules and the division levels of sub-modules may have different manners without departing from the scope of the present disclosure.
In the present invention, the complementary metal oxide transistor CMOS is taken as an example for illustration, but it should be understood by those skilled in the art that the concept of the present invention can also be applied to other fields, for example, the design and implementation can be realized by HBT, BJT, BiCMOS, GaN, etc. processes.
Fig. 1 is a block diagram illustrating an example of a low noise amplifier LNA according to an embodiment of the present invention.
Referring to fig. 1, a low noise amplifier LNA 100 includes an amplifier circuit 101 and a linearity (IIP3) optimization circuit 102. The circuit 102 can be optimized by the IIP3 to provide higher linearity by canceling the non-linear transconductance of the transistors in the amplifier circuit 101, so that the low noise amplifier switches the gain step downwards under the condition of higher gain, thereby better suppressing the noise of the following circuit, improving the receiving performance of the receiver, and improving the communication quality of the receiving link.
In the example of fig. 1, the amplifier circuit 101 adopts a cascode amplifier structure to achieve the effects of high gain, high bandwidth, and better isolation. However, it should be clear to those skilled in the art that the amplifier circuit 101 may also adopt a unipolar common-source amplifier, a common-gate amplifier, a distributed amplifier, a feedback amplifier, etc., as required.
Fig. 2 is a circuit diagram showing an example of a low noise amplifier according to an embodiment of the present invention.
Referring to fig. 2, transistors M1 and M2, inductors L1 and L2, capacitors C1 and C2, and resistor R1 constitute a cascode-structured amplifier circuit, which has the characteristics of high gain, high isolation, and high stability. In addition, the transistors M3-M12, the capacitor C3 and the current source Ib constitute a linearity (IIP3) optimization circuit for the low noise amplifier, which adds an additional linearity improvement circuit to the cascode-structured amplifier circuit to improve the linearity of the low noise amplifier.
Specifically, in the amplifier circuit of the cascode structure of fig. 2, the capacitor C1 is connected between the radio frequency input port rfin and the gate of the transistor M1, serving as a dc blocking capacitor. One end of the resistor R1 is connected to the gate of the transistor M1, and the other end is connected to the first input voltage vb1 for providing a bias voltage for the transistor M1. A source of the transistor M1 is connected to one end of the inductor L1, and a drain of the transistor M1 is connected to a source of the transistor M2. One end of the inductor L1 is connected to the source of the transistor M1, and the other end thereof is connected to the ground node. The gate of the transistor M2 is connected to the second input voltage vb2, the source of the transistor M2 is connected to the drain of the transistor M1, and the drain of the transistor M2 is connected between the capacitor C2 and the inductor L2. One terminal of the capacitor C2 is connected to the drain of the transistor M2, and the other terminal thereof is connected to the radio frequency output port rfout. The inductor L2 has one end connected to the drain of the transistor M2, and the other end connected to the power supply voltage VDD. When the lna operates normally, the voltage variation of the drain V1 of the transistor M1 in the amplifier circuit will cause the transistor M1 to generate a large ac current I2, and the varying ac current I2 will generate a time-varying transconductance gm, thereby deteriorating the linearity IIP3 of the lna.
In the linearity (IIP3) optimization circuit of fig. 2, one end of a capacitor C3 is connected between the transistors M1 and M2, and the other end thereof is connected to the drain of the transistor M12. The gate of the transistor M12 is connected to the third input voltage pd _ IIP3, and the source thereof is connected to the gate of the transistor M3. The transistor M12 can be set to turn on and off according to the third input voltage pd _ IIP3, thereby controlling the linearity (IIP3) to optimize the turning on and off of the circuit.
The source of the transistor M3 is grounded, and the gate and the drain thereof are connected to be connected to the source of the transistor M12, and the drain of the transistor M4, the drain of the transistor M8, the drain of the transistor M9, and the drain of the transistor M10, respectively.
The gate of the transistor M4 is connected to the gates of the transistors M5, M6, M7, and M11, respectively, and the source thereof is connected to the power supply voltage VDD.
The source of the transistor M5 is connected to the power supply voltage VDD, and the drain thereof is connected to the source of the transistor M8. The gate of the transistor M8 is connected to the first control terminal ct0, and the drain thereof is connected to the drain of the transistor M3. The transistor M5 and the transistor M8 form a first current branch for adjusting the on and off of the current branch according to the control of the first control terminal ct 0.
The source of the transistor M6 is connected to the power supply voltage VDD, and the drain thereof is connected to the source of the transistor M9. The gate of the transistor M9 is connected to the second control terminal ct1, and the drain thereof is connected to the drain of the transistor M3. The transistor M6 and the transistor M9 form a second current branch for adjusting the on and off of the current branch according to the control of the second control terminal ct 1.
The source of the transistor M7 is connected to the power supply voltage VDD, and the drain thereof is connected to the source of the transistor M10. The gate of the transistor M10 is connected to the third control terminal ct2, and the drain thereof is connected to the drain of the transistor M3. The transistor M7 and the transistor M10 form a third current branch for adjusting the on and off of the current branch according to the control of the third control terminal ct 2.
The transistor M11 has a source connected to the power supply voltage VDD, a gate connected to the drain, and to the gates of the transistors M4-M7, and one terminal of the current source Ib. The current source Ib has one end connected to the drain of the transistor M11, and the other end grounded.
Referring to fig. 2, in the IIP3 optimization circuit of fig. 2, a current mirror circuit composed of transistors M4, M5, M6, M7 and M11 provides a bias current to the transistor M3, and a switch array composed of transistors M8, M9 and M10 provides a 3 bits-8 th level current control to control the on and off of the first current branch to the third current branch for adjusting the bias current provided to the transistor M3. The transistor M3 is a transistor of the same type as the transistor M1 and having the same single transistor size. Preferably, the finger (finger) number of the transistor M3 is about one tenth of that of the transistor M1. When the IIP3 optimization circuit is turned on by the conduction of the switch M12, the diode-connected transistor M3 also generates an ac current I3, wherein the relationship between I1, I2, and I3 is: i3 ═ I1-I2, so I3 and I2 are in the reverse phase relationship. By adjusting the control voltage of the first control terminal ct 0-the third control terminal ct2, eight steps can be realized to adjust the current of the transistor M3, thereby adjusting the phase and amplitude of I3, and realizing the compensation of the linearity of the amplifier circuit. When the vector-added magnitudes of I3 and I2 are minimal, most of the transistor M1 nonlinearity can be cancelled out. By adjusting the bias current through transistor M3, current I3 can be adjusted to cancel the nonlinearity of transistor M1, thereby improving the linearity IIP3 of the low noise amplifier.
Fig. 3 is a graph showing simulation results of the IIP3 of the low noise amplifier according to the embodiment of the present invention.
Assume that a 50ohm port0 is added at the input and a 50ohm port1 is added at the output of the lna. Two radio frequency signals with frequency difference of 1MHz are added to the input port0, and the frequencies are respectively the middle frequency 3749MHz and 3750MHz of the N77 frequency band. The linearity simulation results when the transistor M12 serving as a switch is in the off state are shown in fig. 3. In fig. 3, the simulation result of IIP3 was 9.43 dBm.
Figure 4 shows another simulation result diagram of the IIP3 of the low noise amplifier according to an embodiment of the invention.
Assume that a 50ohm port0 is added at the input and a 50ohm port1 is added at the output of the lna. Two radio frequency signals with frequency difference of 1MHz are added to the input port0, and the frequencies are respectively the middle frequency 3749MHz and 3750MHz of the N77 frequency band. The results of the linearity simulation when the transistor M12 serving as a switch is in an on (conducting) state are shown in fig. 4. By alternately setting the turning on and off of M8, M9, and M10, 8-step adjustment of the bias current can be achieved. Simulation by adjusting three switches M8/M9/M10 shows that under the load, the simulation result of IIP3 is 12.67dBm at the optimal linearity when transistor M12 is on. It can be seen that the linearity is improved by about 3 dB.
The linearity optimization circuit has the advantages of low power consumption, simple structure, programmability and the like, and the linearity can be improved by more than 3dB under the condition of starting the linearity optimization circuit through simulation.
Although three current branches are shown in the present invention, those skilled in the art will appreciate that the configuration and number of current branches may be adjusted without departing from the scope of the present invention.
Although the present disclosure has been described with exemplary embodiments, various changes and modifications may be suggested to one skilled in the art. The present disclosure is intended to embrace such alterations and modifications as fall within the scope of the appended claims.
None of the description in this specification should be read as implying that any particular element, step, or function is an essential element which must be included in the claim scope. The scope of patented subject matter is defined only by the claims.
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110859664.3A CN113556090A (en) | 2021-07-28 | 2021-07-28 | Linearity optimization circuit and low noise amplifier including the same |
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| CN202110859664.3A CN113556090A (en) | 2021-07-28 | 2021-07-28 | Linearity optimization circuit and low noise amplifier including the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025161840A1 (en) * | 2024-01-29 | 2025-08-07 | 深圳飞骧科技股份有限公司 | Low-noise amplifier and radio frequency chip |
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| CN101939907A (en) * | 2008-01-04 | 2011-01-05 | 高通股份有限公司 | Multi-linearity mode lna having a deboost current path |
| CN103401514A (en) * | 2013-08-14 | 2013-11-20 | 锐迪科创微电子（北京）有限公司 | Low-noise amplifier |
| CN103546104A (en) * | 2013-10-23 | 2014-01-29 | 北京工业大学 | High Linearity Low Noise Amplifier with Small Area and Tunable Linearity |
| US20170070252A1 (en) * | 2015-09-08 | 2017-03-09 | Mediatek Inc. | Radio frequency receiver front-end with gain control capability as well as improved impedance matching control capability |
| CN106849940A (en) * | 2016-12-19 | 2017-06-13 | 深圳艾科创新微电子有限公司 | A kind of frequency deviation controls crystal oscillating circuit |
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2021
- 2021-07-28 CN CN202110859664.3A patent/CN113556090A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101939907A (en) * | 2008-01-04 | 2011-01-05 | 高通股份有限公司 | Multi-linearity mode lna having a deboost current path |
| CN103401514A (en) * | 2013-08-14 | 2013-11-20 | 锐迪科创微电子（北京）有限公司 | Low-noise amplifier |
| CN103546104A (en) * | 2013-10-23 | 2014-01-29 | 北京工业大学 | High Linearity Low Noise Amplifier with Small Area and Tunable Linearity |
| US20170070252A1 (en) * | 2015-09-08 | 2017-03-09 | Mediatek Inc. | Radio frequency receiver front-end with gain control capability as well as improved impedance matching control capability |
| CN106849940A (en) * | 2016-12-19 | 2017-06-13 | 深圳艾科创新微电子有限公司 | A kind of frequency deviation controls crystal oscillating circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025161840A1 (en) * | 2024-01-29 | 2025-08-07 | 深圳飞骧科技股份有限公司 | Low-noise amplifier and radio frequency chip |
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