CN113568850B - Data transmission method, device, electronic device and storage medium - Google Patents
Data transmission method, device, electronic device and storage medium Download PDFInfo
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Abstract
本申请实施例提供了数据传输方法、装置、电子设备及存储介质，该方法包括：获取待发送数据的数字编码；根据预设帧时间及预设编码电平转换规则，确定待发送数据的数字编码对应的各通用输入/输出端口GPIO电平帧，得到各目标GPIO电平帧，其中，预设帧时间为单帧GPIO电平帧的时长，预设编码电平转换规则为数字编码与GPIO电平帧的对应规则；依次向接收端发送各目标GPIO电平帧。本申请实施例的数据传输方法中，采用GPIO电平帧的形式进行数据传输，各单帧GPIO电平帧的时长均为预设帧时间，能够通过时长有效区分各GPIO电平帧，从而能够有效区分各数据，降低了采样难度，有效的实现了点对点的单线GPIO数据传输。
The embodiment of the present application provides a data transmission method, device, electronic device and storage medium, the method comprising: obtaining the digital code of the data to be sent; determining the GPIO level frames of each general input/output port corresponding to the digital code of the data to be sent according to the preset frame time and the preset coding level conversion rule, and obtaining each target GPIO level frame, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rule is the correspondence rule between the digital code and the GPIO level frame; and sending each target GPIO level frame to the receiving end in sequence. In the data transmission method of the embodiment of the present application, data transmission is carried out in the form of GPIO level frames, and the duration of each single-frame GPIO level frame is the preset frame time. Each GPIO level frame can be effectively distinguished by the duration, so that each data can be effectively distinguished, which reduces the sampling difficulty and effectively realizes point-to-point single-line GPIO data transmission.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a data transmission method, a data transmission device, an electronic device, and a storage medium.
Background
Among the point-to-point single-WIRE communication protocols, UART (Universal Asynchronous Receiver/Transmitter, universal asynchronous receiver Transmitter), 1-WIRE protocol, etc. are most commonly used. In these protocols, the receiving end needs to continuously detect the received signal at a sampling frequency far exceeding the baud rate of the transmitting end, and the load on the CPU is very large. Moreover, the existing UART or 1-WIRE protocol is difficult to implement on GPIO (General Purpose Input/Output, general purpose input/Output port) through software, and the main reason is that 2 points are available, 1 is BIT (BIT) edge sampling inaccuracy, and 2 is a plurality of continuous 0 or continuous 1 data sampling difficulties, so that a single-line GPIO data transmission mode capable of being effectively applied to point-to-point is needed.
Disclosure of Invention
The embodiment of the application aims to provide a data transmission method, a device, electronic equipment and a storage medium, so as to realize an effective single-wire GPIO data transmission mode applied to point-to-point. The specific technical scheme is as follows:
In a first aspect, an embodiment of the present application provides a data transmission method, applied to a transmitting end, where the method includes:
acquiring a digital code of data to be transmitted;
Determining GPIO level frames of all general input/output ports corresponding to digital codes of the data to be transmitted according to preset frame time and preset coding level conversion rules, and obtaining all target GPIO level frames, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rules are corresponding rules of the digital codes and the GPIO level frames;
And sequentially sending each target GPIO level frame to a receiving end.
Optionally, the GPIO level frames represent different digital codes by different numbers of level interrupts and/or levels.
Optionally, the digital code is a binary code, the binary code includes 0 and the GPIO level frame corresponding to 1,0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.
Optionally, each GPIO level frame corresponding to the start signal and the end signal includes 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Alternatively, during the transmission phase, the first digital bit is represented by a two frame GPIO level frame.
Optionally, the sending end is a master device or a slave device, where the communication process is initiated by the master device.
In a second aspect, an embodiment of the present application provides a data transmission method, applied to a receiving end, where the method includes:
receiving each GPIO level frame to be decoded sent by a sending end;
and sequentially decoding each GPIO level frame to be decoded into digital codes according to preset frame time and preset coding level conversion rules, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rules are the corresponding rules of the digital codes and the GPIO level frames.
Optionally, the GPIO level frames represent different digital codes by different numbers of level interrupts and/or levels.
Optionally, the digital code is a binary code, the binary code includes 0 and the GPIO level frame corresponding to 1,0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.
Optionally, each GPIO level frame corresponding to the start signal and the end signal includes 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Alternatively, during the transmission phase, the first digital bit is represented by a two frame GPIO level frame.
Optionally, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.
In a third aspect, an embodiment of the present application provides a data transmission device, applied to a transmitting end, where the device includes:
the digital code acquisition module is used for acquiring the digital code of the data to be transmitted;
The GPIO level frame determining module is used for determining GPIO level frames of all general input/output ports corresponding to digital codes of the data to be transmitted according to preset frame time and preset coding level conversion rules to obtain all target GPIO level frames, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rules are corresponding rules of the digital codes and the GPIO level frames;
and the GPIO level frame transmitting module is used for sequentially transmitting each target GPIO level frame to the receiving end.
Optionally, the GPIO level frames represent different digital codes by different numbers of level interrupts and/or levels.
Optionally, the digital code is a binary code, the binary code includes 0 and the GPIO level frame corresponding to 1,0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.
Optionally, each GPIO level frame corresponding to the start signal and the end signal includes 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Alternatively, during the transmission phase, the first digital bit is represented by a two frame GPIO level frame.
Optionally, the sending end is a master device or a slave device, where the communication process is initiated by the master device.
In a fourth aspect, an embodiment of the present application provides a data transmission device, applied to a receiving end, where the device includes:
The GPIO level frame receiving module is used for receiving each GPIO level frame to be decoded sent by the sending end;
And the digital code conversion module is used for sequentially decoding each GPIO level frame to be decoded into digital codes according to preset frame time and preset code level conversion rules, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset code level conversion rules are the corresponding rules of the digital codes and the GPIO level frames.
Optionally, the GPIO level frames represent different digital codes by different numbers of level interrupts and/or levels.
Optionally, the digital code is a binary code, the binary code includes 0 and the GPIO level frame corresponding to 1,0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.
Optionally, each GPIO level frame corresponding to the start signal and the end signal includes 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Alternatively, during the transmission phase, the first digital bit is represented by a two frame GPIO level frame.
Optionally, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.
In a fifth aspect, an embodiment of the present application provides an electronic device, including a memory and at least two processors, where the at least two processors are connected by a GPIO;
the memory is used for storing a computer program;
the processor is configured to implement any one of the data transmission methods described above when executing the program stored in the memory.
In a sixth aspect, an embodiment of the present application provides a computer readable storage medium, where a computer program is stored, where the computer program is executed by a processor to implement any one of the above-mentioned data transmission methods.
The data transmission method, the device, the electronic equipment and the storage medium provided by the embodiment of the application acquire digital codes of data to be transmitted, determine GPIO level frames of all general purpose input/output ports corresponding to the digital codes of the data to be transmitted according to preset frame time and preset code level conversion rules, and acquire all target GPIO level frames, wherein the preset frame time is the duration of a single-frame GPIO level frame, the preset code level conversion rules are corresponding rules of the digital codes and the GPIO level frames, and sequentially transmit all target GPIO level frames to a receiving end. The data transmission mode based on the GPIO level frames is provided, the data transmission is carried out in the form of the GPIO level frames, the duration of each single-frame GPIO level frame is the preset frame time, each GPIO level frame can be effectively distinguished according to the duration, even if a plurality of continuous 0 s or 1 s are transmitted, the effective distinction can be carried out according to the duration, the sampling difficulty is reduced, and the point-to-point single-line GPIO data transmission is effectively realized. Of course, it is not necessary for any one product or method of practicing the application to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the embodiments of the application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a data transmission method applied to a transmitting end according to an embodiment of the present application;
fig. 2 is a schematic diagram of an application scenario according to an embodiment of the present application;
FIG. 3 is a schematic diagram of levels in a data transmission method according to an embodiment of the application;
Fig. 4 is a schematic diagram of a data transmission method applied to a receiving end according to an embodiment of the present application;
Fig. 5 is a schematic diagram of a data transmission device applied to a transmitting end according to an embodiment of the present application;
Fig. 6 is a schematic diagram of a data transmission device applied to a receiving end according to an embodiment of the present application;
fig. 7 is a schematic diagram of an electronic device according to an embodiment of the application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
First, terms of art in the embodiments of the present application will be explained:
GPIO (General Purpose Input/Output, general purpose input/Output port) is a controllable pin of the embedded device, and is connected with external equipment, thereby realizing the functions of external communication, control and data acquisition.
The interruption refers to that when some unexpected situations occur in the running process of the computer and the intervention of the host is needed, the machine can automatically stop the running program and transfer to the program for processing the new situation, and the original suspended program is returned to continue running after the processing is finished. The interruption of the GPIO level frame in the embodiment of the application is triggered by the rising edge and the falling edge of the level.
The embedded device is a special computer system with strict requirements on functions, reliability, cost, volume, power consumption and the like, and is a complex of software and hardware.
The baud rate, which is an indicator of the data transmission rate, is expressed as the number of carrier modulation state changes per unit time, representing the number of symbols transmitted per second.
CPU (Central Processing Unit) is a very large scale integrated circuit, and is the operation Core (Core) and Control Core (Control Unit) of a computer. Its function is mainly to interpret computer instructions and process data in computer software.
GPIO is widely used in existing CPU chips, and in many communication modes, a device is divided into a plurality of sub-boards, in many cases, signal interfaces between the sub-boards are relatively few, but communication needs to be implemented between each module. In the prior art, network communication is adopted among the modules in many cases, but when the IP address and the MAC address are not configured among the sub-boards, the network communication cannot be used.
In view of this, an embodiment of the present application provides a data transmission method, applied to a transmitting end, see fig. 1, where the method includes:
S101, acquiring digital codes of data to be transmitted.
The data transmission method applied to the transmitting end in the embodiment of the application can be realized through electronic equipment, specifically, can be realized through a CPU of the electronic equipment, and the receiving end and the transmitting end can be different CPUs, for example, referring to fig. 2, only one GPIO signal connecting line is needed for data transmission between the two devices. When the interface signals between the two devices are less and the network communication is not established, the embodiment of the application can meet the requirement of simple communication between the two devices. The GPIO interface is the most common in the chip, and the GPIO has the advantages of low power consumption and simple wiring, so the GPIO interface is highly applicable, and the GPIO interface is used for communication in the embodiment of the application.
The data to be transmitted may be transmitted in the form of a digital code, and the data to be transmitted is converted into the digital code, for example, a binary code or a decimal code, etc., to obtain the digital code of the data to be transmitted.
S102, determining each GPIO level frame corresponding to the digital code of the data to be transmitted according to a preset frame time and a preset code level conversion rule, and obtaining each target GPIO level frame, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset code level conversion rule is a rule for the digital code and the GPIO level frame.
In the embodiment of the application, the data transmission is performed in the form of GPIO level frames. The GPIO level frame refers to the GPIO level in a unit time length, which is a preset frame time and can be set in a self-defined manner according to actual conditions. The preset coding level conversion rule is a corresponding rule of digital coding and GPIO level frames. Different digital codes correspond to different GPIO level frames. The data transmission in the embodiment of the application can be divided into three stages, including Start, trans and Stop. Start indicates Start of data transmission, trans indicates specific data transmitted, i.e. data to be transmitted, stop indicates Stop of data transmission. And sequentially generating each GPIO level frame corresponding to the digital code of the data to be transmitted, namely each target GPIO level frame according to a preset code level conversion rule and with preset frame time as the duration of each frame of GPIO level frame.
In one possible implementation, the GPIO level frames represent different digital codes by different numbers of level interrupts and/or levels.
In the embodiment of the application, the interruption of the level is triggered by the rising edge and the falling edge of the level, and the interruption of the level is triggered once when the level is converted from the low level to the high level, and the interruption of the level is triggered once when the level is converted from the high level to the low level. The number of level interruptions and/or the level height (i.e., high level, low level) within a unit duration (i.e., in a GPIO level frame) can be used to distinguish between different digital codes, start, stop, etc.
Because the number of interruption is used to represent different digital codes in the embodiment of the application, the method is particularly important for selecting counting time points, and in order to avoid counting confusion between different stages and BYTE, frame time (preset frame time) is introduced after each stage and each BIT transmission is finished, so that each GPIO level frame is distinguished. The interval between successive breaks in baud rate is negligible compared to the frame time.
And S103, sequentially sending the target GPIO level frames to a receiving end.
The transmitting end sequentially transmits each target GPIO level frame to the receiving end.
In the embodiment of the application, a data transmission mode based on GPIO level frames is provided, the data transmission is carried out in the form of the GPIO level frames, the duration of each single-frame GPIO level frame is preset frame time, each GPIO level frame can be effectively distinguished according to the duration, even if a plurality of continuous 0s or 1s are transmitted, the data can be effectively distinguished according to the duration, the sampling difficulty is reduced, and the point-to-point single-line GPIO data transmission is effectively realized.
Taking binary coding as an example, the interrupt times of 0 (BIT 0) and 1 (BIT 1) in the Trans phase are adjustable, and can be customized according to the actual situation. In one possible implementation, the digital code is a binary code, referring to fig. 3, where the binary code includes 0 and 1, and the GPIO level frame corresponding to 0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.
The GPIO level frames are distinguished by taking frame time as an interval, and the interrupt times are calculated by combining counting characteristics of different stages, so that each target GPIO level frame corresponding to data to be transmitted is finally calculated. Intermediate the Start and Stop phases is a Trans phase. One BYTE in the transit phase consists of eight BITs, each BIT may be either 0 or 1. To distinguish between BIT0 and BIT1, BIT0 may be designed as 1 interrupt and BIT1 as 3 consecutive interrupts.
In one possible implementation, referring to fig. 3, each GPIO level frame corresponding to the start signal and the end signal includes 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
The Start signal indicates Start, i.e. transmission Start, and the end signal indicates Stop, i.e. transmission end. In the Start phase, 5 interrupts are consecutive, and in the Stop phase, 5 interrupts are consecutive. Although both Start and Stop phases are 5 interrupts in succession, start and Stop may be distinguished by different Start levels. For example, the Start phase Start level is high, 5 flipped levels remain low, and the Stop phase Start level is low, 5 flipped levels remain high. Of course, the starting level of the Start phase and the Stop phase can be changed, and the starting level can be set in a self-defined mode according to actual conditions.
In the embodiment of the application, the Start level of the Start signal is different from the Start level of the end signal, so that the Start stage and the Stop stage can be effectively distinguished.
In one possible implementation, during the transmission phase, the first digital bit is represented by a two frame GPIO level frame.
In the Trans phase, for counting the first digital BIT, only one frame of GPIO level frame is used, and whether BIT0 or BIT1 cannot be effectively distinguished, so that the Trans phase is divided into two parts, namely the first digital BIT and other BITs.
For the first digital bit, two frames of GPIO level frames are selected, namely, one frame time after the end of Start is added with the frame time after the end of one digital bit. For example, for a single frame BIT0 of 1 interrupt, a single frame BIT1 of 3 consecutive interrupts, if the first digital BIT is BIT0, the GPIO interrupt count is 2 after the end of two frames, and if the first digital BIT is BIT1, the GPIO interrupt count is 4 after the end of two frames.
In the Trans-phase, the counting of other bits except the first digital bit only needs one frame of GPIO level frame, and the counting ending time is the frame time after the end of the bit. If a BIT other than the first digital BIT is BIT0, the GPIO interrupt count is 1 after the GPIO level frame of that BIT is over, and if a BIT other than the first digital BIT is BIT1, the GPIO interrupt count is 3 after the GPIO level frame of that BIT is over.
In one possible implementation manner, the transmitting end is a master device or a slave device, wherein the communication process is initiated by the master device.
In the single GPIO mode, in order not to cause the two parties of the GPIO connection to preempt the GPIO transmission, one party is provided with a HOST (master) and the other party is provided with a SLAVE (SLAVE), all communication processes must be initiated by the HOST, that is, the data transmitted by the SLAVE party is initiated after being notified by the HOST, so that the situation that the two parties transmit data simultaneously to cause an abnormality can be avoided.
The embodiment of the application also provides a data transmission method, which is applied to the receiving end, and referring to fig. 4, the method comprises the following steps:
S201, each GPIO level frame to be decoded sent by the sending end is received.
S202, sequentially decoding each GPIO level frame to be decoded into digital codes according to preset frame time and preset code level conversion rules, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset code level conversion rules are the corresponding rules of the digital codes and the GPIO level frames.
In one possible implementation, the GPIO level frames represent different digital codes by different numbers of level interrupts and/or levels.
In one possible implementation, the digital code is a binary code, where the binary code includes 0 and 1,0 corresponding GPIO level frames include one interrupt, and 1 corresponding GPIO level frames include three interrupts.
In one possible implementation, each of the GPIO level frames corresponding to the start signal and the end signal includes 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
In one possible implementation, during the transmission phase, the first digital bit is represented by a two frame GPIO level frame.
In one possible implementation manner, the receiving end is a master device or a slave device, wherein the communication process is initiated by the master device.
The GPIO interrupt mode is set to be triggered by rising and falling edges. The counting is distinguished by taking the frame time as an interval, and the interrupt number comparison is carried out by combining the counting characteristics of different stages, so that the transmission data is finally calculated.
In the Start and Stop phases, the number of interrupts is different from that in the Trans phase, and the level state is also different after the transmission is finished, the level is low after the transmission is finished, and the level is high after the transmission is finished, so that the Start and Stop phases are very easy to distinguish in time sequence.
In the Trans phase, only one frame time is used for counting the first BIT, whether BIT0 or BIT1 can not be judged, so the counting is divided into two parts, namely the counting of the first BIT and the counting of other BITs. For the first BIT, two frame times are selected, namely, one frame time after the end of Start is added with the frame time after the end of the first BIT, if the first BIT is BIT0, the GPIO interrupt count is 2 after the end of the two frames, and if the first BIT is BIT1, the GPIO interrupt count is 4 after the end of the two frames.
For counting of other bits than the first bit in the Trans phase, only one frame time is required, which is the frame time after the end of the bit. If the first BIT is BIT0, the GPIO interrupt count is 1 after the frame is over, and if the first BIT is BIT1, the GPIO interrupt count is 3 after the frame is over.
Although the Stop phase is defined as 5 interrupts, since the count of each bit in the transit phase is the frame time after that bit, only 4 interrupts remain in the Stop bit in the actual judgment.
In the embodiment of the application, a data transmission mode based on GPIO level frames is provided, and point-to-point single-line GPIO data transmission is effectively realized.
The embodiment of the application also provides a data transmission device, referring to fig. 5, applied to a transmitting end, the device comprises:
a digital code acquisition module 11, configured to acquire a digital code of data to be transmitted;
the GPIO level frame determining module 12 is configured to determine GPIO level frames of each general purpose input/output port corresponding to the digital code of the data to be sent according to a preset frame time and a preset code level conversion rule, to obtain each target GPIO level frame, where the preset frame time is a duration of a single frame GPIO level frame, and the preset code level conversion rule is a rule corresponding to the digital code and the GPIO level frame;
and the GPIO level frame transmitting module 13 is configured to sequentially transmit each target GPIO level frame to a receiving end.
Optionally, the GPIO level frame indicates different digital codes through different level interrupt times and/or levels.
Optionally, the digital code is a binary code, the binary code includes 0 and the GPIO level frame corresponding to 1,0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.
Optionally, each of the GPIO level frames corresponding to the start signal and the end signal includes 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Alternatively, during the transmission phase, the first digital bit is represented by a two frame GPIO level frame.
Optionally, the sending end is a master device or a slave device, where the communication process is initiated by the master device.
The embodiment of the application also provides a data transmission device, referring to fig. 6, applied to a receiving end, where the device includes:
A GPIO level frame receiving module 21, configured to receive each GPIO level frame to be decoded sent by the sending end;
The digital code conversion module 22 is configured to sequentially decode each of the GPIO level frames to be decoded into a digital code according to a preset frame time and a preset code level conversion rule, where the preset frame time is a duration of a single frame GPIO level frame, and the preset code level conversion rule is a rule corresponding to the digital code and the GPIO level frame.
Optionally, the GPIO level frame indicates different digital codes through different level interrupt times and/or levels.
Optionally, the digital code is a binary code, the binary code includes 0 and the GPIO level frame corresponding to 1,0 includes one interrupt, and the GPIO level frame corresponding to 1 includes three interrupts.
Optionally, each of the GPIO level frames corresponding to the start signal and the end signal includes 5 interrupts, and the start level of the start signal is different from the start level of the end signal.
Alternatively, during the transmission phase, the first digital bit is represented by a two frame GPIO level frame.
Optionally, the receiving end is a master device or a slave device, where the communication process is initiated by the master device.
The embodiment of the application also provides an electronic device, referring to fig. 7, which comprises a memory 32 and at least two processors 31, wherein the at least two processors 31 are connected through GPIOs;
the memory 32 is used for storing a computer program;
The processor 31 is configured to implement any one of the above data transmission methods when executing the program stored in the memory 32.
The Memory may include RAM (Random Access Memory ) or NVM (Non-Volatile Memory), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the aforementioned processor.
The processor may be a general-purpose processor including a CPU (Central Processing Unit ), NP (Network Processor, network processor), DSP (DIGITAL SIGNAL Processing unit), ASIC (Application SPECIFIC INTEGRATED Circuit), FPGA (Field-Programmable gate array) or other Programmable logic device, discrete gate or transistor logic device, or discrete hardware component.
The embodiment of the application also provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program realizes any data transmission method when being executed by a processor.
It should be noted that, in this document, the technical features in each alternative may be combined to form a solution, so long as they are not contradictory, and all such solutions are within the scope of the disclosure of the present application. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
In this specification, each embodiment is described in a related manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for embodiments of the apparatus, electronic device and storage medium, the description is relatively simple as it is substantially similar to the method embodiments, where relevant see the section description of the method embodiments.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.
Claims (10)
1. A data transmission method, applied to a transmitting end, the method comprising:
acquiring a digital code of data to be transmitted;
Determining GPIO level frames of all general input/output ports corresponding to digital codes of the data to be transmitted according to preset frame time and preset code level conversion rules, and obtaining all target GPIO level frames;
sequentially sending each target GPIO level frame to a receiving end;
The method comprises the steps of receiving a preset frame time, wherein the preset frame time is the duration of a single-frame GPIO level frame, the preset coding level conversion rule is a rule corresponding to the digital code and the GPIO level frame, in a transmission stage, a first digital bit is represented by two frames of GPIO level frames, the digital code is a binary code, the binary code comprises 0 and 1, the GPIO level frame corresponding to 0 comprises an interrupt, the GPIO level frame corresponding to 1 comprises three interrupts, the starting signal and the ending signal respectively correspond to the GPIO level frame and comprise 5 interrupts, the starting signal and the ending signal are different from the starting level of the ending signal, and the data transmission is divided into three stages including starting, transmission and stopping, and waiting for the preset frame time after each stage and each bit transmission are finished.
2. The method of claim 1 wherein the GPIO level frames represent different digital codes by the high and low levels.
3. The method of claim 1, wherein the sender is a master or a slave, and wherein the communication process is initiated by the master.
4. A data transmission method, applied to a receiving end, the method comprising:
receiving each GPIO level frame to be decoded sent by a sending end;
Sequentially decoding each GPIO level frame to be decoded into digital codes according to preset frame time and preset coding level conversion rules, wherein the preset frame time is the duration of a single-frame GPIO level frame, and the preset coding level conversion rules are the corresponding rules of the digital codes and the GPIO level frames;
In the transmission stage, the first digital bit is represented by two frames of GPIO level frames;
the digital code is binary code, the binary code comprises 0 and 1, the GPIO level frame corresponding to 0 comprises an interrupt, and the GPIO level frame corresponding to 1 comprises three interrupts;
The GPIO level frames corresponding to the start signal and the end signal respectively comprise 5 interrupts, and the start level of the start signal is different from the start level of the end signal;
the data transmission is divided into three stages including start, transmission, stop, and wait for a preset frame time after each stage and each bit transmission is completed.
5. The method of claim 4 wherein the GPIO level frames represent different digital codes by the high and low levels.
6. The method of claim 4, wherein the receiving end is a master device or a slave device, and wherein the communication process is initiated by the master device.
7. A data transmission apparatus, applied to a transmitting end, comprising:
the digital code acquisition module is used for acquiring the digital code of the data to be transmitted;
The GPIO level frame determining module is used for determining GPIO level frames of all general input/output ports corresponding to digital codes of data to be transmitted according to preset frame time and preset coding level conversion rules to obtain all target GPIO level frames, wherein the preset frame time is the duration of a single-frame GPIO level frame, the preset coding level conversion rules are the corresponding rules of the digital codes and the GPIO level frames, in a transmission stage, a first digital bit is represented by two frames of GPIO level frames, the digital codes are binary codes, the binary codes comprise 0 and 1,0, the GPIO level frames corresponding to 1 comprise one interrupt, the GPIO level frames corresponding to 1 comprise three interrupts, the starting signal and the ending signal respectively comprise 5 interrupts, and the starting level of the starting signal and the ending signal are different;
and the GPIO level frame transmitting module is used for sequentially transmitting each target GPIO level frame to the receiving end.
8. A data transmission apparatus for use at a receiving end, the apparatus comprising:
The GPIO level frame receiving module is used for receiving each GPIO level frame to be decoded sent by the sending end;
The digital code conversion module is used for sequentially decoding each GPIO level frame to be decoded into digital codes according to preset frame time and preset code level conversion rules, wherein the preset frame time is the duration of a single-frame GPIO level frame, the preset code level conversion rules are the corresponding rules of the digital codes and the GPIO level frames, in a transmission stage, the first digital bit is represented by two frames of GPIO level frames, the digital codes are binary codes, the binary codes comprise 0 and 1,0, the GPIO level frames corresponding to 1 comprise one interrupt, the GPIO level frames corresponding to 1 comprise three interrupts, the starting signal and the ending signal respectively comprise 5 interrupts, the starting signal and the ending signal are different in starting level, and the data transmission is divided into three stages, wherein the three stages comprise starting, stopping and waiting for the preset frame time after each stage and each bit transmission are finished.
9. The electronic equipment is characterized by comprising a memory and at least two processors, wherein the at least two processors are connected through GPIO;
the memory is used for storing a computer program;
the processor is configured to implement the data transmission method according to any one of claims 1 to 6 when executing the program stored in the memory.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements the data transmission method according to any one of claims 1-6.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103812557A (en) * | 2013-07-31 | 2014-05-21 | 深圳光启创新技术有限公司 | Visible light signal encoding and decoding method, device and system |
Family Cites Families (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11212904A (en) * | 1998-01-26 | 1999-08-06 | Toshiba Corp | Data transfer system |
| EP1075738B1 (en) * | 1998-04-28 | 2002-03-20 | Siemens Aktiengesellschaft | Data transfer with interruption phases |
| CN100455038C (en) * | 2004-03-03 | 2009-01-21 | 华为技术有限公司 | Data Transmission Method in Enhanced General Packet Radio Service System |
| KR100845811B1 (en) * | 2007-09-05 | 2008-07-14 | 주식회사 하이닉스반도체 | Digital / Analog Conversion Circuit and On-Determination Control Device Using the Same |
| JP2010272925A (en) * | 2009-05-19 | 2010-12-02 | Sony Corp | Information processing apparatus, encoding method, and frame synchronization method |
| US8837628B2 (en) * | 2012-06-19 | 2014-09-16 | Richtek Technology Corporation | Method of transmission through single wire |
| DE102012106210A1 (en) * | 2012-07-10 | 2014-01-16 | Trinamic Motion Control Gmbh & Co. Kg | Method for serial data transmission |
| US9619427B2 (en) * | 2014-04-21 | 2017-04-11 | Qualcomm Incorporated | Hybrid virtual GPIO |
| CN107404319B (en) * | 2016-11-24 | 2020-06-09 | 天地融科技股份有限公司 | Data receiving method and device |
| CN108734944B (en) * | 2017-04-18 | 2021-07-13 | 陕西万方汽车零部件有限公司 | Wireless remote control decoding method and device |
| CN109739709A (en) * | 2019-01-03 | 2019-05-10 | 郑州云海信息技术有限公司 | A kind of I2C line detection method, system and device |
| CN110324115B (en) * | 2019-06-10 | 2022-01-04 | 普联技术有限公司 | Data transmission method and device, storage medium and terminal equipment |
| CN110908940B (en) * | 2019-10-14 | 2021-03-19 | 百富计算机技术（深圳）有限公司 | Method for adjusting serial port communication parameters and terminal equipment |
-
2020
- 2020-04-29 CN CN202010354572.5A patent/CN113568850B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103812557A (en) * | 2013-07-31 | 2014-05-21 | 深圳光启创新技术有限公司 | Visible light signal encoding and decoding method, device and system |
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