CN113594263A

CN113594263A - Silicon carbide diode and method of manufacture

Info

Publication number: CN113594263A
Application number: CN202110802475.2A
Authority: CN
Inventors: 陈俊峰; 廖奇泊; 陈本昌
Original assignee: Zibo Lvnengxinchuang Electronic Technology Co ltd
Current assignee: Zibo Lvnengxinchuang Electronic Technology Co ltd
Priority date: 2021-07-15
Filing date: 2021-07-15
Publication date: 2021-11-02

Abstract

The invention provides a silicon carbide diode and a manufacturing method, comprising: a wafer base layer, a wafer epitaxial layer, a doped region, doped polysilicon, a first metal layer, a front metal layer, a front protective layer and a back metal; One side of the wafer base layer is adjacent to one side of the wafer epitaxial layer; the other side of the wafer base layer is provided with a back metal, and a crystal back ohmic contact is set between the back metal and the wafer base layer; the other side of the wafer epitaxial layer is provided with multiple a groove, the bottom of the groove is set as a doped area, the plane where the top of the groove is located and the side of the groove are set with doped polysilicon; the doped area and the outside of the doped polysilicon are set with a first metal layer, and the outside of the first metal layer is set with a front surface A metal layer, and a front protective layer is arranged outside the front metal layer. Since the interface characteristics are not affected by high temperature, the present invention optimizes the process flow and reduces the process steps after wafer thinning.

Description

Silicon carbide diode and method of manufacture

Technical Field

The invention relates to the field of diode manufacturing, in particular to a silicon carbide diode and a manufacturing method thereof.

Background

The conventional SiC Schottky Barrier Diode (SBD) mainly has a rectifying characteristic because a Schottky Barrier is formed by a specific metal and SiC, but because the characteristic of the interface is very sensitive to the process temperature, it cannot withstand the high temperature process required for forming an ohmic contact on the back of a subsequent wafer, and therefore, a metal process and a passivation structure related to the front of the Schottky Barrier Diode are required to be completed after the ohmic contact on the back of the wafer is formed in the process flow of the Schottky Barrier Diode, which increases the complexity of the process and further limits the yield of production.

Patent document CN110291646A relates to a silicon carbide schottky diode including an N-type SiC layer and a P-type SiC layer, the P-type SiC layer being in contact with the N-type SiC layer to form a P-N junction. The anode is in contact with both the N-type SiC layer and the P-type SiC layer, and schottky contacts are formed between the anode and both the N-type SiC layer and the P-type SiC layer. The edges of the P-type SiC layer are electrically active and include a tapered negative charge density at the P-N junction.

Patent document CN112701165A discloses a method for manufacturing a silicon carbide diode, which comprises the following steps: extending SiC on the SiC substrate to form a SiC epitaxial layer; thermally oxidizing the surface of the SiC epitaxial layer to form SiO₂A layer; in the SiO₂Depositing a mask layer on the layer; etching the active area mask layer to expose the active area ion implantation area; partially etching the JTE area mask layer to expose the JTE area ion implantation area; and (4) performing ion implantation to form a P-doped JTE region and a P + doped active region.

Disclosure of Invention

In view of the defects in the prior art, the present invention provides a silicon carbide diode and a manufacturing method thereof.

According to the present invention, there is provided a silicon carbide diode comprising: the device comprises a wafer substrate layer, a wafer epitaxial layer, a doping area, doped polycrystalline silicon, a first metal layer, a front protective layer and back metal;

one side of the wafer substrate layer is adjacent to one side of the wafer epitaxial layer;

the other side of the wafer substrate layer is provided with the back metal, and a back ohmic contact is arranged between the back metal and the wafer substrate layer;

a plurality of grooves are formed in the other side of the wafer epitaxial layer, the bottom of each groove is provided with the doped region, and the plane where the top of each groove is located and the side face of each groove are provided with the doped polycrystalline silicon;

the first metal layer is arranged on the outer sides of the doped region and the doped polycrystalline silicon, the front metal layer is arranged on the outer side of the first metal layer, and the front protective layer is arranged on the outer side of the front metal layer.

The invention also provides a manufacturing method of the silicon carbide diode, which comprises the following steps:

step S1, depositing SiO on the epitaxial layer of the wafer₂Layer and face the SiO₂Photoetching and etching the layer to expose a first groove expected to be formed, etching the first groove arranged on the epitaxial layer of the wafer to form a second groove, wherein the SiO is₂The layer is doped P-type by ion implantation to form doped region, and the SiO is removed₂A layer;

step S2, forming a carbon film on the surface after processing in the step S1, removing the carbon film after tempering, exposing the silicon carbide region in the doped region through photoetching and etching, and forming doped polysilicon on the side surface and the top of the second groove;

step S3, depositing a first metal layer on the surface after processing in the step S2, performing first metal tempering, and forming ohmic contact on the silicon carbide region and the surface of the doped polysilicon;

step S4, depositing a front metal layer on the surface after the processing in the step S3, and carrying out photoetching and etching, and depositing a front protective layer on the surface of the front metal layer, and carrying out photoetching and etching;

and step S5, carrying out wafer thickness reduction and back metal deposition on the wafer substrate layer, and tempering the back metal to form a back ohmic contact.

Preferably, in step S1, the SiO₂The layers are deposited by chemical vapor deposition.

Preferably, in step S1, the second trench etching manner includes a dry etching manner.

Preferably, in step S1, the SiO₂The layer removal method includes a wet etching method.

Preferably, in step S2, the carbon film forming means includes depositing and sintering a photoresist.

Compared with the prior art, the invention has the following beneficial effects:

1. because the interface characteristic is not influenced by high temperature, the process flow is optimized, and the process steps after the wafer is thinned are reduced;

2. the invention has the advantage of adjustable initial voltage because the difference of work function between the polysilicon and the silicon carbide interface can be changed by adjusting the doping of the polysilicon;

3. the silicon carbide doped region can reduce the leakage current of a polycrystalline silicon and silicon carbide junction in reverse bias, and can provide hole injection to cause conductance modulation to reduce conduction voltage drop in large-current conduction.

Drawings

Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:

FIG. 1 is a schematic diagram of a fabricated silicon carbide diode structure;

FIG. 2 is SiO₂A structural schematic diagram after layer photoetching and etching;

FIG. 3 is a schematic diagram of the structure after etching of silicon carbide;

FIG. 4 illustrates high temperature ion implantation and SiO removal₂A schematic diagram of a post-layer structure;

FIG. 5 is a schematic diagram of the structure after removing the carbon film and etching;

FIG. 6 is a schematic diagram of the structure after deposition of a first metal layer and formation of an ohmic contact;

FIG. 7 is a schematic view of a front-side passivation layer deposited and lithographically etched;

shown in the figure:

Detailed Description

The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.

Example 1

As shown in fig. 1, a silicon carbide diode includes: the structure comprises a wafer substrate layer 1, a wafer epitaxial layer 2, a doping region 3, doped polycrystalline silicon 4, a first metal layer 5, a front metal layer 6, a front protective layer 7 and back metal 9; wafer stratum basale 1 one side adjacent wafer epitaxial layer 2 one side, wafer stratum basale 1 opposite side sets up back metal 9, set up back ohmic contact 8 between back metal 9 and the wafer stratum basale 1, wafer epitaxial layer 2 opposite side sets up a plurality of recesses, the recess bottom sets up to doped region 3, recess top place plane and recess side set up doping polycrystalline silicon 4, doped region 3 and doping polycrystalline silicon 4 outside set up first layer metal level 5, first layer metal level 5 outside sets up positive metal level 6, the positive metal level 6 outside sets up positive sheath 7.

As shown in fig. 2 to 7, a method for manufacturing a silicon carbide diode includes the steps of:

step S1, depositing SiO on the wafer epitaxial layer 2₂ Layer 10 and to SiO₂Layer 10 is subjected to photolithography and etching, SiO₂The layer 10 is deposited by chemical vapor deposition, the expected first groove 11 is exposed, the first groove 11 is arranged on the epitaxial layer 2 of the wafer and etched to form a second groove 12, the etching mode of the second groove 12 comprises a dry etching mode, doping is carried out by an ion implantation mode to form a doping area 3, and then SiO is removed₂ Layer 10, SiO₂The layer 10 removal mode comprises a wet etching mode;

step S2, forming a carbon film on the surface after processing in step S1, removing the carbon film after tempering, exposing a silicon carbide region in the doped region 3 through photoetching and etching, wherein the carbon film forming mode comprises a photoresist deposition and sintering mode, and doped polysilicon is formed on the side surface and the top of the second groove 12;

step S3, depositing a first metal layer 5 on the surface after processing in step S2, performing first metal tempering, and forming ohmic contact on the silicon carbide area and the surface of the doped polysilicon 4;

step S4, depositing a front metal layer 6 on the surface after processing in the step S3, and carrying out photoetching and etching, and depositing a front protective layer 7 on the surface of the front metal layer 6, and carrying out photoetching and etching;

in step S5, the wafer base layer 1 is thinned and deposited with the back metal 9, and the back metal 9 is annealed to form the back ohmic contact 8.

Example 2

Example 2 is a preferred example of example 1.

In the silicon carbide diode of the present invention, as shown in fig. 1, an ohmic contact is formed in the P-type doped region 3 at the bottom of the second trench 12, and a heterojunction having a rectifying property, i.e., doped polysilicon 4, is formed at the top and sidewall of the second trench 12 by polysilicon and N-type silicon carbide.

The specific process steps are as follows:

step 1, as shown in FIG. 2, a layer of SiO is deposited by Chemical Vapor Deposition (CVD)₂Using the existing standard process to align the layer mask to SiO₂Photoetching and etching the layer to expose a first groove 11 which is expected to be formed on the design;

step 2, as shown in fig. 3, etching SiC in a dry etching manner to form a second trench 12, and adjusting SiO technologically₂The etching ratio of SiC; ensuring SiO₂The residual thickness of the silicon nitride can effectively block the ion implantation in the next step;

step 3, as shown in FIG. 4, P-type doping is performed by high temperature ion implantation, and SiO is removed by wet etching₂A layer;

step 4, forming a layer of thin carbon film on the surface of the wafer in a photoresist deposition and sintering manner, and removing the layer of carbon film after high-temperature tempering;

step 5, as shown in fig. 5, the doping type (N-type or P-type) and the doping concentration are adjusted according to the design requirement by the polysilicon deposition, and photolithography and polysilicon etching are performed to expose the silicon carbide P-type doped region 3 at the bottom of the second trench 12;

step 6, as shown in fig. 6, depositing a first metal layer 5, performing a first metal tempering, and forming ohmic contacts on the silicon carbide P-type doped region 3 at the bottom of the second trench 12 and the polysilicon surfaces at the top and side of the second trench 12;

step 7, photoetching and etching are carried out after the front metal layer 6 is deposited;

step 8, as shown in fig. 7, the front surface protective layer 7 is deposited and then is subjected to photoetching and etching;

and 9, reducing the thickness of the wafer, depositing and tempering back metal 9 to form a back ohmic contact 8, and depositing back thick metal.

In the description of the present application, it is to be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience in describing the present application and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present application.

The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.

Claims

1. A silicon carbide diode, characterized in that it comprises: a wafer base layer (1), a wafer epitaxial layer (2), a doped region (3), doped polysilicon (4), a first metal layer ( 5), the front metal layer (6), the front protective layer (7) and the back metal (9);

One side of the wafer base layer (1) is adjacent to one side of the wafer epitaxial layer (2);

The back metal (9) is provided on the other side of the wafer base layer (1), and a crystal back ohmic contact (8) is provided between the back metal (9) and the wafer base layer (1);

The other side of the epitaxial layer of the wafer (2) is provided with a plurality of grooves, the bottom of the groove is set as the doped region (3), and the plane where the top of the groove is located and the side of the groove are provided with the grooves. Doped polysilicon (4);

The first metal layer (5) is arranged outside the doped region (3) and the doped polysilicon (4), and the front metal layer (6) is arranged outside the first metal layer (5). and the front protective layer (7) is arranged on the outer side of the front metal layer (6).

2. A method of manufacturing a silicon carbide diode according to claim 1, characterized in that, comprising the steps of:

Step S1, depositing a SiO ₂ layer (10) on the wafer epitaxial layer (2) and performing photolithography and etching on the SiO ₂ layer (10), exposing the first trench (11) to be formed, and performing photolithography and etching on the SiO 2 layer (10). The wafer epitaxial layer (2) is etched at the first trench (11) to form a second trench (12), and the SiO ₂ layer (10) is P-type doped by ion implantation, After doping to form a doped region (3), the SiO ₂ layer (10) is removed;

Step S2, after the carbon film is formed on the surface after the processing in the step S1 and the carbon film is removed after tempering, the doped region (3) is exposed to the silicon carbide region through photolithography and etching, and the second Doping polysilicon is formed on the side and top of the trench (12);

Step S3, after the processing in step S2, a first metal layer (5) is deposited on the surface and a first metal tempering is performed to form an ohmic contact on the surface of the silicon carbide region and the doped polysilicon (4);

Step S4, depositing a front metal layer (6) on the surface after the processing in step S3 and performing photolithography and etching, depositing a front protective layer (7) on the surface of the front metal layer (6) and performing photolithography and etching ;

In step S5, wafer thickness reduction and backside metal (9) deposition are performed on the wafer base layer (1), and the backside metal (9) is tempered to form a backside ohmic contact (8).

3 . The method for manufacturing a silicon carbide diode according to claim 1 , wherein in step S1 , the SiO ₂ layer ( 10 ) is deposited by chemical vapor deposition. 4 .

4 . The method for manufacturing a silicon carbide diode according to claim 1 , wherein in step S1 , the etching method of the second trench ( 12 ) comprises a dry etching method. 5 .

5 . The method for manufacturing a silicon carbide diode according to claim 1 , wherein in step S1 , the removal method of the SiO ₂ layer ( 10 ) includes a wet etching method. 6 .

6 . The method for manufacturing a silicon carbide diode according to claim 1 , wherein in step S2 , the carbon film formation method includes a method of depositing and sintering photoresist. 7 .