CN113644138B - Single layer MoS 2 -Si-based tunneling diode and preparation method thereof - Google Patents

Abstract

The invention discloses a single-layer MoS ₂ A-Si-based tunneling diode and a preparation method thereof relate to the technical field of semiconductors, and the method comprises the following steps: providing a first substrate, and preparing SiO on one side surface of the first substrate ₂ An isolation region to obtain a first substrate structure; obtaining a second substrate comprising a pre-grown single-layer MoS ₂ (ii) a Single layer MoS using epitaxial layer transfer technique ₂ Transferring to a first surface; patterning the single layer MoS ₂ Forming a single layer of MoS ₂ A channel layer; depositing a first electrode and a second electrode on the first surface to make the second electrode and SiO ₂ Isolation region and single-layer MoS ₂ The channel layer is in direct contact with the substrate to obtain a single-layer MoS ₂ -a Si-based tunneling diode. The invention provides a single-layer MoS ₂ The Si-based tunneling diode and the preparation method thereof can reduce the interface defect density, further inhibit trap-assisted tunneling and improve the subthreshold swing of the device from the process perspective.

Description

Single layer MoS2-Si based tunneling diode and its preparation method

technical field

The invention belongs to the technical field of semiconductors, and in particular relates to a single-layer MoS ₂ -Si-based tunneling diode and a preparation method thereof.

Background technique

As the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide Semiconductor Field-Effect Transistor) device feature size gradually reaches deep submicron, the short channel effect appears, resulting in an increase in leakage current, which in turn reduces the power consumption of the device. Increased and reduced reliability, so ultra-steep devices need to be pursued. However, due to the Boltzmann smearing effect, the subthreshold swing of MOSFET cannot break through the limit of 60mV/dec at room temperature. This is determined by the conduction mechanism of MOSFET using hot electron transport. Therefore, ultra-steep devices with new mechanisms are sought without delay.

In related technologies, the new device TFET (Tunneling Field-Effect Transistor, Tunneling Field-Effect Transistor) has attracted widespread attention. The working principle of TFET is a band-band tunneling mechanism, so it can get rid of the influence of Boltzmann tailing effect, has a steeper sub-threshold slew rate and excellent off-state characteristics. However, in terms of material selection, the traditional Si-based TFET has low tunneling efficiency due to its indirect bandgap and large forbidden band width. Threshold slew rate and off-state characteristics deteriorate. In addition, the heterojunction energy band structure that forms the type II energy band structure is the most ideal tunneling junction, but the heterogeneous tunneling junction formed by the bulk material in the traditional sense has serious lattice mismatch and trap-assisted tunneling. A series of problems, which in turn lead to poor device performance.

Contents of the invention

In order to solve the above-mentioned problems in the prior art, the present invention provides a single-layer MoS ₂ -Si-based tunneling diode and a preparation method thereof. The technical problem to be solved in the present invention is realized through the following technical solutions:

In the first aspect, the present invention provides a method for preparing a single-layer MoS ₂ -Si-based tunneling diode, comprising:

A first substrate is provided, and an _SiO2 isolation region is prepared on one side surface of the first substrate to obtain a first substrate structure; wherein, along a first direction, the first substrate structure includes a first substrate structure oppositely arranged a surface and a second surface, the first direction is perpendicular to the plane where the first substrate structure is located;

Obtaining a second substrate, the second substrate comprising pre-grown monolayer MoS ₂ ;

Using an epitaxial layer transfer technique, transferring the single layer MoS ₂ to the first surface;

Patterning the single-layer MoS ₂ to form a single-layer MoS ₂ channel layer; the orthographic projection of the single-layer MoS ₂ channel layer in the first direction covers at least part of the first boundary, and the first boundary is The orthographic projection of the contact surface between the _SiO2 isolation region and the first substrate on the plane where the first substrate structure is located, wherein the contact surface is perpendicular to the plane where the first substrate structure is located;

Deposit and form a first electrode and a second electrode on the first surface, make the second electrode directly contact with the _SiO2 isolation region and the single-layer _MoS2 channel layer, and obtain the completed single-layer MoS ₂ - Si-based tunneling diodes.

In one embodiment of the present invention, the step of providing the first substrate and preparing a _SiO2 isolation region on one side surface of the first substrate to obtain the first substrate structure includes:

providing a first substrate;

Etching one side surface of the first substrate to form a pattern area;

SiO ₂ is deposited on the side surface where the pattern area is etched, and the first substrate after the SiO ₂ deposition is polished to form a SiO ₂ isolation area to obtain the first substrate structure.

In an embodiment of the present invention, the thickness of the SiO ₂ isolation region in the first direction is h, wherein 1 μm<h<10 μm.

In one embodiment of the present invention, the first substrate is a silicon substrate, and the second substrate is a sapphire substrate.

In one embodiment of the present invention, the step of transferring the single layer of _MoS2 to the first surface using epitaxial layer transfer technology includes:

Spin-coat polymethyl methacrylate PMMA solution on the surface of the pre-grown monolayer MoS away from the _second substrate side, and use a hot plate to bake the polymethyl methacrylate solution to solidify ;

The second substrate with the cured PMMA/monolayer _MoS2 film was immersed in deionized water and kept warm after heating to a preset temperature;

The second substrate with cured PMMA/ _monolayer MoS film was taken out from deionized water, the PMMA/monolayer MoS film was separated from the _second substrate by mechanical peeling, and the PMMA/monolayer MoS ₂ transferring the thin film to the first surface of the first substrate structure;

Make described PMMA/monolayer MoS ₂ in the thin film through hot plate baking Monolayer MoS ₂ and described first surface are bonded;

Put the first substrate structure with cured PMMA/monolayer MoS ₂ film into acetone solution, remove PMMA and soak with ethanol;

Remove the first substrate structure with monolayer _MoS2 from ethanol and wash using deionized water.

In one embodiment of the present invention, the step of patterning the single-layer MoS ₂ to form a single-layer MoS ₂ channel layer includes:

Spin-coat photoresist on the surface of the single-layer MoS ₂ away from the first substrate structure, after exposure and development, leave a photoresist mask in the first predetermined area, and etch the monolayer MoS ₂ , forming a monolayer MoS ₂ channel layer.

In one embodiment of the present invention, the deposition on the first surface forms the first electrode and the second electrode, so that the second electrode is isolated from the SiO ₂ and the patterned single-layer MoS ₂ Direct contact, the steps to obtain the completed single-layer MoS ₂ -Si-based tunneling diode include:

Spin-coating photoresist on the first surface, leaving a photoresist mask in the second predetermined area after exposure and development;

Electron beam evaporation is used to deposit nickel/titanium/gold on the first surface, and the excess nickel/titanium/gold in the second preset area is stripped to form the first electrode and the second electrode, and the completed single-layer MoS ₂ is obtained - Si-based tunneling diode; wherein said second electrode is in direct contact with said monolayer _MoS2 channel layer and said _SiO2 isolation region.

In an embodiment of the present invention, along the first direction, the thickness of nickel is 80 nm, the thickness of titanium is 20 nm, and the thickness of gold is 50 nm.

In a second aspect, the present invention provides a single-layer MoS ₂ -Si-based tunneling diode, which is prepared by the preparation method described in any one of the above-mentioned first aspects.

Compared with prior art, the beneficial effect of the present invention is:

1. In the method for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by the present invention, a single-layer MoS ₂ channel layer is prepared on the first substrate by using epitaxial layer transfer technology to form a van der Waals heterojunction, It can alleviate the thermal expansion coefficient mismatch to a certain extent, reduce the interface defect density, thereby suppress trap-assisted tunneling, and improve the subthreshold swing of the device from a process perspective.

2. The present invention combines the monolayer _MoS2 channel layer prepared by epitaxial layer transfer printing technology with the structure of the device, and the formed tunneling diode is a planar structure, which is beneficial to realize the alignment, electrode isolation and The interconnection of devices is conducive to the realization of high-performance heterogeneous integrated systems.

The present invention will be described in further detail below in conjunction with the accompanying drawings and embodiments.

Description of drawings

Fig. 1 is a schematic flow chart of a method for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention;

Fig. 2 is a schematic diagram of a process for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention;

3 is a schematic diagram of another process for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention;

Fig. 4 is a schematic diagram of another process for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention;

5 is a schematic diagram of another process for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention;

6 is a schematic diagram of another process for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention;

Fig. 7 is a schematic structural diagram of a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention;

Fig. 8 is a top view of a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with specific examples, but the embodiments of the present invention are not limited thereto.

Fig. 1 is a schematic flow chart of a method for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention, and Figs. 2-6 are preparations of a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention 7 is a schematic diagram of the structure of a single-layer MoS ₂ -Si-based tunneling diode provided by an embodiment of the present invention. Please refer to Figures 1-7, the present invention provides a method for preparing a single-layer MoS ₂ -Si-based tunneling diode, including:

S1. A first substrate 101 is provided, and an SiO ₂ isolation region 102 is prepared on one side surface of the first substrate 101 to obtain a first substrate structure 10; wherein, along the first direction x, the first substrate structure 10 includes For the first surface s1 and the second surface s2 arranged oppositely, the first direction x is perpendicular to the plane where the first substrate structure 10 is located;

S2. Acquiring the second substrate 201, the second substrate 201 includes a pre-grown single-layer MoS ₂ 202;

S3, using the epitaxial layer transfer technology to transfer the single layer of MoS ₂ 202 to the first surface s1;

S4. Patterning the single-layer MoS ₂ 202 to form a single-layer MoS ₂ channel layer 103; the orthographic projection of the single-layer MoS ₂ channel layer 103 in the first direction x covers at least part of the first boundary L1, and the first boundary L1 is The orthographic projection of the contact surface s3 between the _SiO2 isolation region 102 and the first substrate 101 on the plane where the first substrate structure 10 is located, wherein the contact surface s3 is perpendicular to the plane where the first substrate structure 10 is located;

S5, deposit and form the first electrode 1041 and the second electrode 1042 on the first surface s1, make the second electrode 1042 directly contact with the SiO ₂ isolation region 102 and the single-layer MoS ₂ channel layer 103, and obtain the completed single-layer MoS ₂ - Si-based tunneling diodes.

Exemplarily, the first substrate 101 is a P-type heavily doped Si substrate with a crystal orientation of <100> and a doping concentration of 1×10 ²⁰ to 1×10 ²¹ cm ⁻³ . As shown in Figure 2, SiO ₂ isolation regions 102 are prepared on one side surface of the first substrate 101 to form the first substrate structure 10, that is to say, the first substrate structure 10 includes the first substrate 101 and SiO ₂ Quarantine 102. Wherein, the first substrate structure 10 includes a first surface s1 and a second surface s2 oppositely disposed in the first direction x, and the SiO ₂ isolation region 102 is located on the side of the first surface s1 of the first substrate structure 10 .

Please refer to Fig. 3. In the above step S2, the second substrate 201 is a sapphire substrate, and MoS ₂ can be deposited on the sapphire bottom by chemical vapor deposition, so as to obtain a single-layer MoS ₂ 202 with good quality. . Certainly, in some other embodiments of the present invention, the second substrate of other materials may also be selected, which is not limited in the present invention.

Further, as shown in FIGS. 4-5 , the pre-grown single-layer MoS ₂ on the second substrate 201 is transferred to the first surface s1 of the first substrate structure 10 by using the epitaxial layer transfer technology, and the single-layer MoS ₂ The orthographic projection in one direction covers the first substrate structure 10; then the above-mentioned single-layer MoS ₂ is patterned to form a single-layer MoS ₂ channel layer 103. In the top view as shown in FIG. 6 , the single-layer MoS ₂ channel The orthographic projection of the layer 103 on the first direction x covers at least part of the first boundary L1, which is the positive plane of the contact surface s3 between the SiO ₂ isolation region 102 and the first substrate 101 on the plane where the first substrate structure 10 is located. projection, and the contact surface s3 is perpendicular to the plane where the first substrate structure 10 is located.

It should be noted that in this embodiment, the single-layer _MoS2 channel layer 103104 can be etched to form strips, and the area of the strips can be etched according to the area of the channel layer 103 required by the device, which is not limited in the present invention .

As shown in FIGS. 7-8, in the above step S5, the first electrode 1041 and the second electrode 1042 are deposited and formed on the first surface s1 of the first substrate structure 10, wherein the second electrode 1042 is separated from the SiO ₂ 102 and the single-layer MoS ₂ channel layer 103 are in direct contact, so as to obtain a fabricated single-layer MoS ₂ -Si-based tunneling diode.

On the one hand, this embodiment adopts the epitaxial layer transfer technology to prepare the single-layer _MoS2 channel layer 103 on the first substrate 101, which can not only avoid directly growing the single-layer _MoS2 channel layer 103 on the first substrate 101 but also The resulting interface defects can prevent the degradation of the film quality of the single-layer MoS ₂ channel layer 103, and can also alleviate the lattice mismatch to a certain extent, reduce the density of interface defects, thereby inhibiting trap-assisted tunneling, and improving the sub- threshold swing. On the other hand, the preparation method provided in this embodiment is aimed at preparing a planar tunneling diode. The channel layer 103 prepared by epitaxial layer transfer technology is combined with the structure of the tunneling device to prepare a planar tunneling diode. The structure is beneficial to realize the alignment of triode devices, electrode isolation and device interconnection, and further facilitates the realization of high-performance heterogeneous integrated systems.

Optionally, in the above step S1, the first substrate 101 is provided, and the SiO ₂ isolation region 102 is prepared on one side surface of the first substrate 101 to obtain the first substrate structure 10, including:

providing a first substrate 101;

Etching one side surface of the first substrate 101 to form a pattern area;

SiO ₂ is deposited on the side surface where the pattern area is etched, and the first substrate 101 after SiO ₂ deposition is polished to form a SiO 2 isolation area 102 to obtain the first substrate structure 10 .

Specifically, a pattern area is formed by etching on one side of the first substrate 101, the pattern area is a groove, and the groove is recessed toward the side close to the second surface s2 of the first substrate structure 10, optionally Specifically, the orthographic projection of the groove in one direction is a square with a size of 150*150 μm. Further, an oxide layer, namely SiO ₂ , is deposited on the surface of the side where the patterned area is etched by using plasma enhanced chemical vapor deposition (PECVD) at a temperature of 250-450°C. During the deposition process, SiO ₂ will overflow the pattern area and cover part of the first substrate 101. Therefore, it is necessary to further use chemical mechanical polishing (CMP) to polish SiO ₂ to ensure that the SiO ₂ obtained is isolated. The contact surface s3 between the region 102 and the first substrate 101 is completely exposed.

It should be understood that the function of the _SiO2 isolation region 102 is to block the conductive path between the metal electrode and the first substrate 101. Due to the limitation of the manufacturing process, the _SiO2 isolation region 102 cannot be made too thick, but if the _SiO2 isolation region 102 If it is made too thin, there is a risk of _SiO2 being broken down. Therefore, as shown in FIG. 2, in this embodiment, the thickness h of the SiO2 isolation region 102 in the first direction x is set to 1-10 μm, for example, the thickness h of the _SiO2 isolation region 102 in the first direction x is 5 μm, 6 μm Or 8 μm, so that not only can the SiO ₂ isolation region 102 fully exert the electrical isolation function, but also can reduce the process difficulty and save the production cost.

Optionally, in the above step S3, the step of transferring the single layer of _MoS2 to the first surface s1 using the epitaxial layer transfer technology includes:

Spin-coat polymethyl methacrylate PMMA solution on the surface of the pre-grown monolayer MoS ₂ away from the second substrate 201, and use a hot plate to bake the polymethyl methacrylate solution to solidify;

Immerse the second substrate 201 with the cured PMMA/monolayer _MoS2 film in deionized water, and keep it warm after being heated to a preset temperature;

Take out the second substrate 201 with the cured PMMA/ _monolayer MoS film from deionized water, separate the PMMA/ _monolayer MoS film from the second substrate 201 by mechanical peeling, and separate the PMMA/ _monolayer MoS film transferred to the first surface s1 of the first substrate structure 10;

The monolayer MoS in the PMMA/monolayer MoS ₂ film is bonded to the first surface s1 by heating _plate baking;

Put the first substrate structure 10 with solidified PMMA/monolayer _MoS2 thin film into acetone solution, remove PMMA and soak with ethanol;

The first substrate structure 10 with monolayer _MoS2 was taken out from ethanol and cleaned using deionized water.

In this embodiment, firstly, a polymethyl methacrylate PMMA solution with a volume fraction of 8% is coated on the surface of the pre-grown monolayer MoS ₂ away from the second substrate 201. For example, a coater can be used to Spin coating at a speed of 1000r/min for 30s, then heat to 100°C with a hot plate, and bake for 60s to cure the PMMA; place the second substrate 201 with a cured PMMA/monolayer _MoS2 film into a container filled with deionized water In a beaker, heated to 80°C and held for 3 hours, and the second substrate 201 with cured PMMA/monolayer MoS ₂ film was taken out from the deionized water, and the PMMA/monolayer MoS ₂ film was obtained by mechanical peeling.

Further, after peeling off from the second substrate 201 to obtain the PMMA/monolayer _MoS2 film, the _MoS2 in the PMMA/monolayer _MoS2 film is attached to the first surface s1 of the first substrate structure 10, followed by The heating plate was heated to 140°C and baked for 30 minutes, and the monolayer MoS ₂ was closely attached to the first surface s1.

Alternatively, after transferring the PMMA/monolayer _MoS2 thin film to the first substrate structure 10, the first substrate structure 10 with the cured PMMA/monolayer _MoS2 thin film is immersed in acetone solution for 10 minutes, after removing the PMMA After soaking in ethanol, the first substrate structure 10 with a single layer of MoS ₂ was pulled out and cleaned with deionized water, so as to obtain the first substrate structure 10 with a single layer of MoS ₂ thin film.

Optionally, in the above step S4, the step of patterning the single-layer MoS ₂ to form the single-layer MoS ₂ channel layer 103 includes:

Spin-coat photoresist on the surface of the single-layer MoS ₂ away from the first substrate structure 10, after exposure and development, leave a photoresist mask in the first predetermined area, and etch the single-layer MoS ₂ , A single-layer MoS ₂ channel layer 103 is formed.

Specifically, a 5214 photoresist was spin-coated at a speed of 4000 r/min for 30 s on the first substrate structure 10 with a single-layer MoS ₂ film (that is, on the side of the first surface s1), and the MA-6 stepping photoresist was used to The engraving machine aligns the mask plate with the first substrate structure 10 on which the photoresist has been spin-coated. After exposure and development, the photoresist mask in the first predetermined area is left, and is etched using an ion beam etching machine IBE. The single layer MoS ₂ is etched to form the single layer MoS ₂ channel layer 103 .

In this embodiment, the first electrode 1041 and the second electrode 1042 are deposited and formed on the first surface s1, so that the second electrode 1042 is directly connected to the SiO ₂ isolation region 102 and the patterned single-layer MoS ₂ . Contact, the steps to obtain the completed single-layer MoS ₂ -Si-based tunneling diode, including:

Spin-coat photoresist on the first surface s1, and leave a photoresist mask in the second predetermined area after exposure and development;

Electron beam evaporation is used to deposit nickel/titanium/gold on the first surface, and the excess nickel/titanium/gold in the second preset area is stripped to form the first electrode and the second electrode, and the completed single-layer MoS ₂ is obtained - Si-based tunneling diode; wherein said second electrode is in direct contact with said monolayer _MoS2 channel layer and said _SiO2 isolation region.

Specifically, after the first surface s1 of the first substrate structure 10 is spin-coated with 5214 photoresist at a speed of 4000r/min for 30s, after exposure and development, the photoresist mask of the second predetermined area is left , use electron beam evaporation to deposit nickel/titanium/gold on the first surface s1 of the first substrate structure 10, then put the first substrate structure 10 into acetone to clean the photoresist, and remove the metal layer ( That is, nickel/titanium/gold within the second predetermined area), thereby forming the first electrode 1041 and the second electrode 1042, and the second electrode 1042 is in direct contact with the single-layer MoS2 channel layer 103 and the SiO2 isolation region 102.

Exemplarily, along the first direction, the thickness of nickel in the first electrode 1041 and the second electrode 1042 is 80 nm, the thickness of titanium is 20 nm, and the thickness of gold is 50 nm. It should be noted that, in the actual manufacturing process, the thicknesses of nickel, titanium, and gold in the first electrode and the second electrode can be flexibly adjusted according to process requirements, which is not limited in this application.

As shown in FIG. 7 , the embodiment of the present invention also provides a single-layer MoS ₂ -Si-based tunneling diode, which can be prepared by the above-mentioned preparation method of the single-layer MoS ₂ -Si-based tunneling diode.

Can know by above-mentioned each embodiment, beneficial effect of the present invention is:

1. In the method for preparing a single-layer MoS ₂ -Si-based tunneling diode provided by the present invention, a single-layer MoS ₂ channel layer is prepared on the first substrate by using epitaxial layer transfer technology to form a van der Waals heterojunction, It can alleviate the thermal expansion coefficient mismatch to a certain extent, reduce the interface defect density, thereby suppress trap-assisted tunneling, and improve the subthreshold swing of the device from a process perspective.

2. The present invention combines the monolayer _MoS2 channel layer prepared by epitaxial layer transfer printing technology with the structure of the device, and the formed tunneling diode is a planar structure, which is beneficial to realize the alignment, electrode isolation and The interconnection of devices is conducive to the realization of high-performance heterogeneous integrated systems.

In describing the present invention, it should be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Orientation indicated by rear, left, right, vertical, horizontal, top, bottom, inside, outside, clockwise, counterclockwise, etc. The positional relationship is based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, Therefore, it should not be construed as limiting the invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

In the present invention, unless otherwise clearly specified and limited, terms such as "installation", "connection", "connection" and "fixation" should be understood in a broad sense, for example, it can be a fixed connection or a detachable connection , or integrated; it can be mechanically connected or electrically connected; it can be directly connected or indirectly connected through an intermediary, and it can be the internal communication of two components or the interaction relationship between two components. Those of ordinary skill in the art can understand the specific meanings of the above terms in the present invention according to specific situations.

In the present invention, unless otherwise clearly specified and limited, a first feature being "on" or "under" a second feature may include direct contact between the first and second features, and may also include the first and second features Not in direct contact but through another characteristic contact between them. Moreover, "above", "above" and "above" the first feature on the second feature include that the first feature is directly above and obliquely above the second feature, or simply means that the first feature is horizontally higher than the second feature. "Below", "beneath" and "under" the first feature to the second feature include that the first feature is directly below and obliquely below the second feature, or simply means that the first feature has a lower level than the second feature.

In the description of this specification, descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific examples", or "some examples" mean that specific features described in connection with the embodiment or example , structure, material or characteristic is included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

Although the present application has been described in conjunction with various embodiments here, however, in the process of implementing the claimed application, those skilled in the art can understand and Other variations of the disclosed embodiments are implemented. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that these measures cannot be combined to advantage.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (8)

1. Single-layer MoS ₂ -a method of manufacturing a Si-based tunneling diode, comprising:

providing a first substrate, and preparing SiO on one side surface of the first substrate ₂ An isolation region to obtain a first substrate structure; the first substrate structure comprises a first surface and a second surface which are oppositely arranged along a first direction, and the first direction is vertical to a plane where the first substrate structure is located;

obtaining a second substrate comprising a pre-grown single-layer MoS ₂ ；

In the pre-grown single layer MoS ₂ Spin coating poly-A on the surface of the side far away from the second substrateThe PMMA solution is baked by a hot plate to be solidified;

with cured PMMA/single layer MoS ₂ Immersing a second substrate of the film into deionized water, and preserving heat after heating to a preset temperature;

removing the cured PMMA/monolayer MoS from the deionized water ₂ A second substrate of thin film, PMMA/single layer MoS by mechanical stripping ₂ Separating the thin film from the second substrate and applying PMMA/monolayer MoS ₂ Transferring the thin film to a first surface of the first substrate structure;

baking the PMMA/single layer MoS by a hot plate ₂ Single layer MoS in thin films ₂ Attaching to the first surface;

with cured PMMA/single layer MoS ₂ Putting the first substrate structure of the film into an acetone solution, removing PMMA, and then soaking with ethanol;

removal of MoS with monolayer from ethanol ₂ And cleaning the first substrate structure with deionized water;

patterning the single layer MoS ₂ Forming a single layer of MoS ₂ A channel layer; the single-layer MoS ₂ The orthographic projection of the channel layer in the first direction covers at least part of a first boundary, and the first boundary is the SiO ₂ The orthographic projection of a contact surface of the isolation region and the first substrate on a plane where the first substrate structure is located is performed, wherein the contact surface is vertical to the plane where the first substrate structure is located;

depositing a first electrode and a second electrode on the first surface to make the second electrode and the SiO ₂ Isolation region and single-layer MoS ₂ The channel layer is in direct contact with the substrate to obtain a single-layer MoS ₂ -a Si-based tunneling diode.

2. The single layer MoS of claim 1 ₂ The preparation method of the-Si-based tunneling diode is characterized in that a first substrate is provided, and SiO is prepared on one side surface of the first substrate ₂ An isolation region, the step of obtaining a first substrate structure, comprising:

providing a first substrate;

etching a side surface of the first substrate to form a pattern area;

depositing SiO on the side surface etched with the pattern region ₂ And depositing SiO ₂ Polishing the first substrate to form SiO ₂ And (5) isolating the region to obtain a first substrate structure.

3. Single layer MoS according to claim 2 ₂ -Si-based tunneling diode, characterized in that the SiO ₂ The thickness of the isolation region in the first direction is h, wherein the thickness is 1 μm<h<10μm。

4. The single layer MoS of claim 1 ₂ The preparation method of the Si-based tunneling diode is characterized in that the first substrate is a silicon substrate, and the second substrate is a sapphire substrate.

5. The single layer MoS of claim 1 ₂ -Si-based tunneling diode, characterized in that said patterning of said single MoS layer ₂ Forming a single layer of MoS ₂ A channel layer step, comprising:

in the single layer MoS ₂ Spin-coating photoresist on the surface of one side far away from the first substrate structure, exposing and developing to leave a photoresist mask of a first preset area, and etching the single-layer MoS ₂ Forming a single layer of MoS ₂ And a channel layer.

6. The single layer MoS of claim 1 ₂ The preparation method of the-Si-based tunneling diode is characterized in that a first electrode and a second electrode are formed on the first surface in a deposition mode, and the second electrode and the SiO are enabled to be connected ₂ Isolation region and single-layer MoS after patterning ₂ Direct contact to obtain the finished single-layer MoS ₂ -a step of Si-based tunneling diode, comprising:

spin-coating a photoresist on the first surface, and after exposure and development, leaving a photoresist mask in a second preset area;

depositing nickel/titanium/gold on the first surface by using electron beam evaporation, and stripping redundant nickel/titanium/gold in the range of the second preset area to form a first electrode and a second electrode to obtain the manufactured single-layer MoS ₂ -a Si-based tunneling diode; wherein the second electrode and the single layer MoS ₂ Channel layer and the SiO ₂ The isolation regions are in direct contact.

7. The single layer MoS of claim 6 ₂ -a method of manufacturing a Si-based tunneling diode, characterized in that along said first direction, the thickness of nickel is 80nm, the thickness of titanium is 20nm, and the thickness of gold is 50nm.

8. Single-layer MoS ₂ -Si-based tunneling diode, characterized in that it is obtained by means of a method according to any one of claims 1 to 7.

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