CN113690138B - Semiconductor structure and method for forming semiconductor structure - Google Patents
Semiconductor structure and method for forming semiconductor structure Download PDFInfo
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- CN113690138B CN113690138B CN202010420663.4A CN202010420663A CN113690138B CN 113690138 B CN113690138 B CN 113690138B CN 202010420663 A CN202010420663 A CN 202010420663A CN 113690138 B CN113690138 B CN 113690138B
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 175
- 239000010410 layer Substances 0.000 claims description 238
- 238000005530 etching Methods 0.000 claims description 34
- 239000011241 protective layer Substances 0.000 claims description 26
- 238000001312 dry etching Methods 0.000 claims description 10
- 238000002955 isolation Methods 0.000 claims description 8
- 238000001039 wet etching Methods 0.000 claims description 4
- 239000000463 material Substances 0.000 description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 5
- 239000010941 cobalt Substances 0.000 description 5
- 229910017052 cobalt Inorganic materials 0.000 description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 5
- 229910052721 tungsten Inorganic materials 0.000 description 5
- 239000010937 tungsten Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 2
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- -1 silicon carbide nitride Chemical class 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/62—Fin field-effect transistors [FinFET]
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- Condensed Matter Physics & Semiconductors (AREA)
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- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
一种半导体结构及半导体结构的形成方法，结构包括：衬底，衬底包括相对的第一面和第二面，衬底包括有效区和连接区；位于衬底连接区内的第一凹槽，在沿衬底第一面至第二面的方向上，第一凹槽包括第一区、第二区和第三区，第一区在衬底表面具有第一投影，第二区在衬底表面具有第二投影，第三区在衬底表面具有第三投影，第二投影的面积大于第一投影的面积，第二投影的面积大于第三投影的面积，且第一投影在第二投影的范围内，第三投影在所述第二投影的范围内；位于第一凹槽内的可被电连接的第一连接层触。所述半导体结构的性能得到提升。
A semiconductor structure and a method for forming the semiconductor structure, the structure comprising: a substrate, the substrate comprising a first surface and a second surface opposite to each other, the substrate comprising an effective area and a connection area; a first groove located in the connection area of the substrate, in the direction from the first surface to the second surface of the substrate, the first groove comprises a first area, a second area and a third area, the first area has a first projection on the substrate surface, the second area has a second projection on the substrate surface, the third area has a third projection on the substrate surface, the area of the second projection is greater than the area of the first projection, the area of the second projection is greater than the area of the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection; a first connection layer contact that can be electrically connected is located in the first groove. The performance of the semiconductor structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the semiconductor structure.
Background
As semiconductor technology nodes continue to shrink, so does the size of standard logic semiconductor cells. It is necessary to increase the density of the logic semiconductor circuit so that the size of the standard cell can be made extremely small.
Currently, a shrinking approach is adopted to increase the density of logic semiconductor circuits. However, the density of logic semiconductor circuits that are improved in a miniaturized manner is limited. Therefore, a way to reduce the height of the transistor cells is proposed to increase the density of the logic semiconductor circuit, i.e. to reduce the number of standard cell fins and to embed the power supply lines (Buried Power Rail, BPR for short). The embedded power line is usually used in combination with a back-side PDN (back-side power deliver network for short) to boost the voltage drop.
However, the performance of the existing embedded power line and the back side power transmission network is still to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a method for forming the semiconductor structure to improve the performance of the semiconductor structure.
In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a first groove and a first connecting layer, wherein the substrate comprises a first surface and a second surface which are opposite, the substrate comprises an effective area and a connecting area, the first groove is positioned in the connecting area of the substrate, extends from the first surface to the second surface of the substrate, comprises a first area, a second area and a third area in the direction from the first surface to the second surface of the substrate, the first area is provided with a first projection on the surface of the substrate, the second area is provided with a second projection on the surface of the substrate, the third area is provided with a third projection on the surface of the substrate, the area of the second projection is larger than the area of the first projection, the area of the second projection is larger than the area of the third projection, the first projection is positioned in the range of the second projection, the third projection is positioned in the range of the second projection, and the first connecting layer which can be electrically connected in the first groove.
Optionally, in a first direction parallel to the surface of the substrate, the cross-sectional shape of the first groove is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5.
Optionally, the first surface active area of the substrate is further provided with a plurality of fin structures, the fin structures are arranged in parallel along a first direction parallel to the surface of the substrate, and the connection area is located between the adjacent fin structures.
Optionally, the fin structure further comprises a protective layer located on the first surface of the substrate and covering the top surface and the side wall surface of the fin structure, a second groove located in the protective layer and communicated with the first groove, part of the first connecting layer is located in the second groove, and an isolation layer located in the second groove on the first connecting layer.
Optionally, the substrate comprises a second connecting layer positioned in the substrate connecting area, the second connecting layer extends from the second surface of the substrate to the first surface of the substrate, and the second connecting layer is contacted with the first connecting layer.
Optionally, the bottom of the first connection layer has a first size, and the top of the second connection layer, which is in contact with the first connection layer, has a second size, and the first size is larger than the second size.
Optionally, the first dimension is greater than the second dimension by 10% -50%.
Optionally, the substrate further comprises a plurality of conductive structures positioned on the second surface of the substrate, and the conductive structures are electrically connected with the second connecting layer.
Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises a first surface and a second surface which are opposite, the substrate comprises an effective area and a connecting area, forming a first groove in the substrate connecting area, the first groove extends from the first surface to the second surface of the substrate, the first groove comprises a first area, a second area and a third area in the direction from the first surface to the second surface of the substrate, the first area is provided with a first projection on the surface of the substrate, the second area is provided with a second projection on the surface of the substrate, the third area is provided with a third projection on the surface of the substrate, the area of the second projection is larger than the area of the first projection, the area of the second projection is larger than the area of the third projection, the first projection is in the range of the second projection, the third projection is in the range of the second projection, and the first connecting layer capable of being electrically connected is formed in the first groove.
Optionally, in a first direction parallel to the surface of the substrate, the cross-sectional shape of the first groove is spherical or polygonal, and the number of sides of the polygon is greater than or equal to 5.
Optionally, the first surface active area of the substrate is further provided with a plurality of fin structures, the fin structures are arranged in parallel along a first direction parallel to the surface of the substrate, and the connection area is located between the adjacent fin structures.
Optionally, the method for forming the first groove comprises the steps of forming a protective layer on the first surface of the substrate, wherein the protective layer covers the top surface and the side wall surface of the fin structure, forming a first mask layer on the protective layer, wherein the first mask layer exposes the surface of the protective layer on the connection region, etching the protective layer by taking the first mask layer as a mask until the surface of the substrate is exposed, forming a second groove in the protective layer, and etching the substrate exposed by the second groove to form the first groove.
Optionally, the method for etching the substrate exposed by the second groove comprises the steps of adopting a first etching process to etch the substrate to form an initial first groove, enabling the side wall of the initial first groove to be perpendicular to the bottom surface of the initial first groove, and adopting a second etching process to etch the substrate exposed by the initial first groove to form a first groove, wherein the side wall of the first groove is recessed into the effective area.
Optionally, the first etching process includes an anisotropic dry etching process.
Optionally, the second etching process includes one or more combinations of wet etching processes and isotropic dry etching processes.
Optionally, a portion of the first connection layer is further located in the second groove.
Optionally, after forming the first connection layer, forming an isolation layer in the second groove.
Optionally, after forming the first connection layer, forming a second connection layer in the substrate connection region, wherein the second connection layer extends from the second surface of the substrate to the first surface of the substrate, and the second connection layer is in contact with the first connection layer.
Optionally, the bottom of the first connection layer has a first size, and the top of the second connection layer, which is in contact with the first connection layer, has a second size, and the first size is larger than the second size.
Optionally, the first dimension is greater than the second dimension by 10% -50%.
Optionally, the forming method of the second connection layer comprises the steps of forming a second mask layer on the second surface of the substrate, wherein the second mask layer exposes the surface of the connection region, etching the substrate by taking the second mask layer as a mask until the surface of the first connection layer is exposed, forming a third groove in the substrate, and forming a second connection layer in the third groove.
Optionally, after forming the second connection layer, forming a plurality of conductive structures on the second surface of the substrate, wherein the conductive structures are electrically connected with the second connection layer.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the semiconductor structure disclosed by the technical scheme of the invention, the first groove is formed in the first surface connection area of the substrate, the first groove comprises a first area, a second area and a third area along the direction from the first surface to the second surface of the substrate, the first area is provided with a first projection on the surface of the substrate, the second area is provided with a second projection on the surface of the substrate, the third area is provided with a third projection on the surface of the substrate, the area of the second projection is larger than the area of the first projection, the area of the second projection is larger than the area of the third projection, the first projection is in the range of the second projection, the third projection is in the range of the second projection, and the first connection layer is positioned in the first groove, so that the bottom area of the first connection layer is increased. On one hand, when the second connecting layer is formed in the substrate connecting area, the bottom of the second connecting layer is easy to contact with the bottom of the first connecting layer, the situation that the second connecting layer is in poor contact with the first connecting layer is reduced, and therefore the first connecting layer can be electrically connected with a conductive structure formed subsequently through the second connecting layer, and on the other hand, the contact resistance of the first connecting layer and the second connecting layer can be reduced. In conclusion, the performance of the semiconductor structure is improved.
According to the method for forming the semiconductor structure, the first groove is formed in the connecting area of the first surface of the substrate, the first groove comprises the first area, the second area and the third area along the direction from the first surface to the second surface of the substrate, the first area is provided with the first projection on the surface of the substrate, the second area is provided with the second projection on the surface of the substrate, the third area is provided with the third projection on the surface of the substrate, the area of the second projection is larger than the area of the first projection, the area of the second projection is larger than the area of the third projection, the first projection is in the range of the second projection, the third projection is in the range of the second projection, and the first connecting layer is formed in the first groove, so that the bottom area of the first connecting layer is increased. On one hand, when the second connecting layer is formed in the substrate connecting area, the bottom of the second connecting layer is easy to contact with the bottom of the first connecting layer, the situation that the second connecting layer is in poor contact with the first connecting layer is reduced, and therefore the first connecting layer can be electrically connected with a conductive structure formed subsequently through the second connecting layer, and on the other hand, the contact resistance of the first connecting layer and the second connecting layer can be reduced. In conclusion, the performance of the semiconductor structure is improved.
Further, in a first direction parallel to the substrate surface, the first groove has a spherical or polygonal cross-sectional shape, and the number of sides of the polygon is 5 or more, so that the bottom area of the first groove increases, thereby making the second connection layer easily contact with the bottom of the first connection layer.
Further, the bottom of the first connection layer has a first size, and the top of the second connection layer, which is in contact with the first connection layer, has a second size, which is larger than the first size, such that the second connection layer is easily in contact with the bottom of the first connection layer when the second connection layer is formed.
Drawings
FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to one embodiment;
fig. 2 to 7 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Detailed Description
As described in the background art, the performance of the existing embedded power line and the back power transmission network in cooperation needs to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment.
Referring to fig. 1, the semiconductor device comprises a substrate 100, a fin structure 101, a dielectric layer 102, a first connecting layer 103, a second connecting layer 104, a conductive layer 105 and a second connecting layer 104, wherein the substrate 100 comprises a first surface and a second surface which are opposite, the substrate 100 comprises an effective area (not labeled) and a connecting area (not labeled), the fin structure 101 is arranged on the effective area of the first surface of the substrate 100, the dielectric layer 102 is arranged on the first surface of the substrate 100 and covers the top surface and the side wall surface of the fin structure 101, the first connecting layer 103 is arranged in the connecting area of the first surface of the substrate 100, the first connecting layer 103 is also arranged in the dielectric layer 102, the second connecting layer 104 is arranged in the connecting area of the second surface of the substrate 100, the second connecting layer 104 is in contact with the bottom of the first connecting layer 103, and the conductive layer 105 is arranged on the second surface of the substrate 100 and is electrically connected with the second connecting layer 104.
In the semiconductor structure, since the size of the semiconductor structure is smaller and smaller, the size of the first connection layer 103 is smaller and smaller, so that when the second connection layer 104 contacting with the first connection layer 103 is formed in the second surface connection area of the substrate 100, the formed second connection layer 104 is affected by the accuracy of the photolithography process and the accuracy of the etching process, and the formed second connection layer 104 has a risk of poor contact with the bottom of the first connection layer 103, so that the first connection layer 103 cannot be electrically connected with the conductive layer 105 through the second connection layer 104, thereby affecting the performance of the semiconductor structure.
In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming a semiconductor structure, in which a first groove is formed in a connection region on a first surface of a substrate, the first groove includes a first region, a second region and a third region along a direction from the first surface to a second surface of the substrate, the first region has a first projection on a surface of the substrate, the second region has a second projection on a surface of the substrate, the third region has a third projection on the surface of the substrate, an area of the second projection is larger than an area of the first projection, an area of the second projection is larger than an area of the third projection, the first projection is within a range of the second projection, and the third projection is within a range of the second projection, and a first connection layer is formed in the first groove, so that a bottom area of the first connection layer is increased. On one hand, when the second connecting layer is formed in the substrate connecting area, the bottom of the second connecting layer is easy to contact with the bottom of the first connecting layer, the situation that the second connecting layer is in poor contact with the first connecting layer is reduced, and therefore the first connecting layer can be electrically connected with a conductive structure formed subsequently through the second connecting layer, and on the other hand, the contact resistance of the first connecting layer and the second connecting layer can be reduced. In conclusion, the performance of the semiconductor structure is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 7 are schematic cross-sectional views illustrating a semiconductor structure forming process according to an embodiment of the present invention.
Referring to fig. 2, a substrate 200 is provided, the substrate 200 including opposite first and second sides, the substrate 200 including an active area I and a connection area II.
In this embodiment, the substrate 200 is made of monocrystalline silicon, and in other embodiments, the substrate may be made of polycrystalline silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, germanium on insulator, or other semiconductor materials.
The first surface active area I of the substrate 200 further has a plurality of fin structures 201, and the fin structures 201 are arranged in parallel along a first direction X parallel to the surface of the substrate 200.
The connection region II is located between adjacent fin structures 201.
In this embodiment, the fin structure 201 is made of monocrystalline silicon, and in other embodiments, the fin structure may be made of polycrystalline silicon, germanium, silicon germanium, gallium arsenide, silicon on insulator, or semiconductor material such as germanium on insulator.
With continued reference to fig. 2, a protection layer 202 is formed on the first surface of the substrate, and the protection layer 202 covers the top surface and the sidewall surface of the fin structure 201.
The material of the protective layer 202 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride. In this embodiment, the material of the protective layer 202 includes silicon oxide.
Next, a first recess 205 is formed in the connection region II of the substrate 200, said first recess 205 extending from the first side to the second side of the substrate 200. The specific process of forming the first groove 205 is shown in fig. 3 to 4.
Referring to fig. 3, a first mask layer 203 is formed on the protective layer 202, the first mask layer 203 exposes the surface of the protective layer 202 on the connection region II, and the protective layer 202 is etched by taking the first mask layer 203 as a mask until the surface of the substrate 200 is exposed, so that a second groove 204 is formed in the protective layer 202.
The process of etching the protective layer 202 includes a combination of one or more of a dry etching process and a wet etching process.
In this embodiment, the process of etching the protective layer 202 includes a dry etching process.
Referring to fig. 4, the substrate 200 exposed by the second recess 204 is etched, and the first recess 205 is formed in the connection region II.
The method for etching the substrate 200 exposed by the second groove 204 includes etching the substrate 200 by a first etching process to form an initial first groove (not shown), wherein the sidewall of the initial first groove is perpendicular to the bottom surface of the initial first groove, etching the substrate 200 exposed by the initial first groove by a second etching process to form a first groove 205, and the sidewall of the first groove 205 is recessed into the active area I.
The first etching process can obtain an initial first groove with the side wall perpendicular to the bottom surface. In this embodiment, the first etching process includes an anisotropic dry etching process.
The second etching process can obtain a first groove 205 with a sidewall recessed into the active area I. The second etching process includes a combination of one or more of a wet etching process and an isotropic dry etching process.
In the embodiment, the second etching process comprises an isotropic dry etching process, and the parameters of the isotropic dry etching process comprise etching gas which is mixed gas of NF 3、H2、N2 and O 2, air pressure which is 5 mTorr-100 mTorr, power which is 100W-1000W, and gas flow which is 0 sccm-500 sccm.
In a first direction X parallel to the surface of the substrate 200, the cross-sectional shape of the first recess 205 is spherical or polygonal in a direction perpendicular to the extending direction of the fin structure 201, and the number of sides of the polygon is 5 or more, so that the bottom area of the first recess 205 is increased, and a subsequently formed second connection layer is easily contacted with the bottom of the first connection layer.
In this embodiment, the dimension of the first groove 205 in the first direction X is 10nm to 100nm, and the dimension of the first groove 205 in the direction from the first surface to the second surface of the substrate is 10nm to 100nm. When the first groove 205 in the size range is formed in the first groove 205, the bottom area of the first connection layer is increased, so that the second connection layer formed in the subsequent step is easy to contact with the first connection layer, and the first connection layer has a good conductive effect.
In this embodiment, the first groove 205 is spherical in shape.
In a direction along the first side to the second side of the substrate 200, the first recess 205 includes a first region (not labeled), a second region (not labeled), and a third region (not labeled), the first region has a first projection on the surface of the substrate 200, the second region 200 has a second projection on the surface of the substrate, the third region 200 has a third projection on the surface of the substrate, the second projection has an area larger than the first projection, the second projection has an area larger than the third projection, and the first projection is within the range of the second projection, and the third projection is within the range of the second projection, such that when a first connection layer is subsequently formed in the first recess 205, a bottom area of the first connection layer is increased, thereby making a subsequently formed second connection layer easily contact with the first connection layer.
Referring to fig. 5, a first connection layer 206 is formed in the first recess 205.
The first connection layer 206 is formed by forming a connection material layer (not shown) in the second recess 204, in the first recess 205 and on the protection layer 202, planarizing the connection material layer until the surface of the protection layer 202 is exposed, forming an initial connection layer (not shown), and etching back the initial connection layer to form the first connection layer 206.
The material of the first connection layer 206 includes a metal including a combination of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride. The forming process of the connecting material layer comprises a physical vapor deposition process or an electroplating process.
In this embodiment, the material of the first connection layer 206 includes copper, and the formation process of the connection material layer includes a physical vapor deposition process.
In this embodiment, a portion of the first connection layer 206 is also located within the second recess 204.
In a direction along the first side to the second side of the substrate 200, the first recess 205 includes a first region having a first projection on the surface of the substrate 200, a second region having a second projection on the surface of the substrate, and a third region 200 having a third projection on the surface of the substrate, the second projection having an area larger than the first projection, the second projection having an area larger than the third projection, and the first projection being within the second projection, the third projection being within the second projection such that a bottom area of the first connection layer 206 located within the first recess 205 is increased. The bottom area of the first connection layer 206 is increased, so that, on one hand, when the second connection layer is formed in the substrate connection region II, the bottom of the second connection layer is easy to contact with the bottom of the first connection layer 206, and poor contact between the second connection layer and the first connection layer 206 is reduced, and therefore, the first connection layer 206 can be electrically connected with a conductive structure formed subsequently through the second connection layer, and on the other hand, contact resistance between the first connection layer 206 and the second connection layer can be reduced.
With continued reference to fig. 5, after the first connection layer 206 is formed, an isolation layer 207 is formed within the second recess 204.
The material of the isolation layer 207 comprises a dielectric material comprising one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, silicon carbide nitride, and silicon oxycarbide nitride. In this embodiment, the material of the isolation layer 207 includes silicon oxide.
Referring to fig. 6, after the first connection layer 206 is formed, a second connection layer 208 is formed in the substrate connection region II, the second connection layer 208 extends from the second surface of the substrate 200 to the first surface of the substrate 200, and the second connection layer 208 contacts the first connection layer 206.
The bottom of the first connection layer 206 has a first size and the top of the second connection layer 208, which is in contact with the first connection layer 206, has a second size, which is larger than the first size, such that the second connection layer 208 is easily in contact with the bottom of the first connection layer 206 when the second connection layer 208 is formed.
In this embodiment, the first dimension is greater than the second dimension by 10% -50%.
The second connection layer 208 is formed by forming a second mask layer (not shown) on the second surface of the substrate, wherein the second mask layer exposes the surface of the connection region II, etching the substrate 200 with the second mask layer as a mask until the surface of the first connection layer 206 is exposed, forming a third groove (not shown) in the connection region II, and forming a second connection layer 208 in the third groove.
The material of the second connection layer 208 includes a metal including a combination of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride.
Since the first dimension is greater than the second dimension by 10% -50%, when the third groove is formed, the area of the bottom of the third groove exposing the bottom of the first connection layer 206 is larger, so that even if the position of the third groove deviates, the second connection layer 208 formed in the third groove can be contacted with the first connection layer 206, and meanwhile, the contact area of the second connection layer 208 and the first connection layer 206 is also larger, so that the contact resistance of the first connection layer 206 and the second connection layer 208 can be reduced, and the process window for forming the third groove can be increased.
Referring to fig. 7, a plurality of conductive structures 209 are formed on the second surface of the substrate 200, and the conductive structures 209 are electrically connected to the second connection layer 208.
The conductive structure 209 is used for electrical connection of the semiconductor structure with external structures.
The material of the conductive structure 209 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride.
The second connection layer 208 is in good contact with the first connection layer 206, so that the first connection layer 206 can be electrically connected to the conductive structure 209 via the second connection layer 208, thereby achieving an electrical connection of the semiconductor structure to an external structure.
Accordingly, embodiments of the present invention further provide a semiconductor structure, with continued reference to fig. 7, comprising a substrate 200, the substrate 200 comprising opposite first and second sides, the substrate 200 comprising an active area I and a connection area II, a first recess 205 located within the connection area II of the substrate 200, the first recess 205 extending from the first side to the second side of the substrate 200, the first recess comprising a first region having a first projection on a surface of the substrate 200, a second region having a second projection on a surface of the substrate 200, and a third region having a third projection on a surface of the substrate 200, the second projection having an area larger than the first projection, the second projection having an area larger than the third projection, the first projection being within the second projection, the third projection being within the second projection, and the first recess 205 being electrically connectable to the first connection layer 206.
In this embodiment, in the first direction X parallel to the surface of the substrate 200, the shape of the first groove 205 is a sphere or a polygon, and the number of sides of the polygon is greater than or equal to 5.
In this embodiment, the first surface active area I of the substrate 200 further has a plurality of fin structures 201, the fin structures 201 are arranged in parallel along a first direction X parallel to the surface of the substrate, and the connection area II is located between adjacent fin structures 201.
In this embodiment, the fin structure further includes a protection layer 202 on the first surface of the substrate 200, the protection layer 202 covering the top surface and the sidewall surface of the fin structure 201, a second groove 204 in the protection layer 202, the second groove 204 communicating with the first groove 205, and a portion of the first connection layer 206 being in the second groove 204, and an isolation layer 207 in the second groove 204 on the first connection layer 206.
In this embodiment, the second connection layer 208 is located in the connection region II of the substrate 200, the second connection layer 208 extends from the second surface of the substrate 200 to the first surface of the substrate 200, and the second connection layer 208 is in contact with the first connection layer 206.
In this embodiment, the bottom of the first connection layer 206 has a first size, and the top of the second connection layer 208, which is in contact with the first connection layer 206, has a second size, and the first size is larger than the second size.
In this embodiment, the first dimension is greater than the second dimension by 10% -50%.
In this embodiment, the material of the first connection layer 206 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride, and the material of the second connection layer 208 comprises a metal comprising a combination of one or more of copper, aluminum, tungsten, cobalt, and titanium nitride.
In this embodiment, the substrate 200 further includes a plurality of conductive structures 209 disposed on the second surface of the substrate 200, and the conductive structures 209 are electrically connected to the second connection layer 208.
The semiconductor structure has a first groove 205 in a first surface connection region II of the substrate 200, the first groove includes a first region, a second region and a third region along a direction from the first surface to the second surface of the substrate, the first region has a first projection on a surface of the substrate, the second region has a second projection on a surface of the substrate, the third region has a third projection on a surface of the substrate, an area of the second projection is larger than an area of the first projection, an area of the second projection is larger than an area of the third projection, the first projection is in a range of the second projection, the third projection is in a range of the second projection, and the first connection layer 206 is located in the first groove 205, so that a bottom area of the first connection layer 206 is increased. On the one hand, when the second connection layer 208 is formed in the connection region II of the substrate 200, the bottom of the second connection layer 208 is easy to contact with the bottom of the first connection layer 206, and the poor contact between the second connection layer 208 and the first connection layer 206 is reduced, so that the first connection layer 206 can be electrically connected with the conductive structure 209 through the second connection layer 208, and on the other hand, the contact resistance between the first connection layer 206 and the second connection layer 208 can be reduced. In conclusion, the performance of the semiconductor structure is improved.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (17)
1. A semiconductor structure, comprising:
A substrate comprising opposing first and second faces, the substrate comprising an active area and a connection area;
A first recess in the substrate connection region, the sidewall of the first recess being recessed into the active region, the first recess extending from the substrate first face to the second face, the first recess including a first region having a first projection on the substrate surface, a second region having a second projection on the substrate surface, and a third region having a third projection on the substrate surface, the second projection having an area greater than the area of the first projection, the second projection having an area greater than the area of the third projection, and the first projection being within the range of the second projection, the third projection being within the range of the second projection;
a first connection layer located in the first groove and capable of being electrically connected;
A second connection layer located within the substrate connection region, the second connection layer extending from the substrate second face toward the substrate first face, the second connection layer being in contact with the first connection layer, a bottom of the first connection layer having a first dimension, a top of the second connection layer in contact with the first connection layer having a second dimension, the first dimension being greater than the second dimension;
a protective layer on the first side of the substrate;
a second groove in the protective layer, the second groove being located on the first groove, the second groove being in communication with the first groove;
and the isolation layer is positioned in the second groove on the first connecting layer.
2. The semiconductor structure of claim 1, wherein the first recess has a cross-sectional shape that is spherical or polygonal in a first direction parallel to a surface of the substrate, the number of sides of the polygon being greater than or equal to 5.
3. The semiconductor structure of claim 1, wherein the substrate first surface active region further has a plurality of fin structures thereon, the plurality of fin structures being arranged in parallel along a first direction parallel to the substrate surface, the connection region being located between adjacent fin structures.
4. The semiconductor structure of claim 3, wherein the protective layer covers a top surface and a sidewall surface of the fin structure, and wherein a portion of the first connection layer is located within the second recess.
5. The semiconductor structure of claim 1, wherein the first dimension is greater than the second dimension by a range of 10% -50%.
6. The semiconductor structure of claim 1, further comprising a plurality of conductive structures on the second side of the substrate, the conductive structures electrically connected to the second connection layer.
7. A method of forming a semiconductor structure, comprising:
Providing a substrate comprising opposing first and second faces, the substrate comprising an active area and a connection area;
forming a protective layer on the first surface of the substrate;
Forming a first groove in a substrate connection region, wherein the side wall of the first groove is recessed into the effective region, the first groove extends from a first surface to a second surface of the substrate, the first groove comprises a first region, a second region and a third region in the direction from the first surface to the second surface of the substrate, the first region has a first projection on the surface of the substrate, the second region has a second projection on the surface of the substrate, the third region has a third projection on the surface of the substrate, the area of the second projection is larger than the area of the first projection, the area of the second projection is larger than the area of the third projection, and the first projection is in the range of the second projection, and the third projection is in the range of the second projection;
forming a first connection layer in the first groove, wherein the first connection layer can be electrically connected;
Forming a second groove in the protection layer on the first connecting layer, wherein the second groove is positioned on the first groove, and the second groove is communicated with the first groove;
forming an isolation layer in the second groove;
And forming a second connecting layer in the substrate connecting area, wherein the second connecting layer extends from the second surface of the substrate to the first surface of the substrate, the second connecting layer is contacted with the first connecting layer, the bottom of the first connecting layer is provided with a first size, the top of the second connecting layer contacted with the first connecting layer is provided with a second size, and the first size is larger than the second size.
8. The method of forming a semiconductor structure of claim 7, wherein a cross-sectional shape of the first recess is spherical or polygonal in a first direction parallel to a surface of the substrate, the number of sides of the polygon being greater than or equal to 5.
9. The method of claim 7, wherein the first active area of the substrate further comprises a plurality of fin structures, the fin structures are arranged in parallel along a first direction parallel to the surface of the substrate, and the connection region is located between adjacent fin structures.
10. The method of claim 9, wherein forming the first recess comprises forming a protective layer on the first surface of the substrate, the protective layer covering the top surface and the sidewall surface of the fin structure, forming a first mask layer on the protective layer, the first mask layer exposing the protective layer surface on the connection region, etching the protective layer with the first mask layer as a mask until the substrate surface is exposed, forming a second recess in the protective layer, and etching the substrate exposed by the second recess to form the first recess.
11. The method of forming a semiconductor structure of claim 10, wherein etching the substrate exposed by the second recess comprises etching the substrate using a first etching process to form an initial first recess, wherein a sidewall of the initial first recess is perpendicular to a bottom surface of the initial first recess, and etching the substrate exposed by the initial first recess using a second etching process to form a first recess, wherein the sidewall of the first recess is recessed into the active region.
12. The method of forming a semiconductor structure of claim 11, wherein the first etching process comprises an anisotropic dry etching process.
13. The method of forming a semiconductor structure of claim 11, wherein the second etching process comprises a combination of one or more of a wet etching process and an isotropic dry etching process.
14. The method of forming a semiconductor structure of claim 10, wherein a portion of the first connection layer is further located within the second recess.
15. The method of forming a semiconductor structure of claim 7, wherein the first dimension is greater than the second dimension by a range of 10% -50%.
16. The method for forming a semiconductor structure according to claim 7, wherein the forming of the second connection layer comprises forming a second mask layer on the second surface of the substrate, wherein the second mask layer exposes the surface of the connection region, etching the substrate with the second mask layer as a mask until the surface of the first connection layer is exposed, forming a third groove in the substrate, and forming a second connection layer in the third groove.
17. The method of forming a semiconductor structure as recited in claim 7, further comprising forming a plurality of conductive structures on a second side of the substrate after forming the second connection layer, the conductive structures being electrically connected to the second connection layer.
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