CN113703093B - Ultra-low loss silicon waveguide and its preparation method - Google Patents

Abstract

The disclosure provides an ultra-low loss silicon waveguide and its preparation method. The preparation method includes the following steps: selecting an SOI wafer as a substrate; thermally oxidizing the upper part of the first silicon layer; etching the second silicon dioxide layer; deposit silicon dioxide to form a third silicon dioxide layer; implant oxygen ions above the third silicon dioxide layer to form an oxygen-rich ion layer; etch to remove the second silicon dioxide layer and the third silicon dioxide layer; Deposit silicon dioxide on top of the first silicon layer to form the fourth silicon dioxide layer; anneal at high temperature to make the oxygen-rich ion layer react to form the fifth silicon dioxide layer; etch to remove the fourth silicon dioxide layer to obtain a finished product , the first silicon layer below the fifth silicon dioxide layer in the finished product is the waveguide layer, and the first silicon layer below the third protrusion is the silicon waveguide. The disclosure transfers the waveguide pattern to the buried layer, avoiding the problem of high side wall roughness caused by etching in the conventional silicon waveguide preparation scheme, and the prepared silicon waveguide has the advantage of ultra-low loss.

Description

Ultra-low loss silicon waveguide and its preparation method

technical field

The disclosure relates to the field of optoelectronic chips and integration, in particular to an ultra-low loss silicon waveguide and a preparation method thereof.

Background technique

Optoelectronic chips and integrated technology have outstanding advantages such as low power consumption, high speed, high reliability, and small size. These advantages are the core key to breaking through the bottlenecks faced by information networks in terms of speed bandwidth, energy consumption volume, intelligence, and reconfigurability. It also has a wide range of applications in optical communication, sensing, computing, biology, medicine, agriculture and other fields.

The carrier for preparing optoelectronic integrated chips includes silicon base, indium phosphide, lithium niobate, silicon nitride, silicon dioxide, polymer and other materials. Among them, silicon base has the advantages of small size, low energy consumption, CMOS process compatibility and easy integration with existing Some electronic devices and photonic devices have the advantages of monolithic and micro-nano integration, and are the most commonly used materials for preparing optoelectronic integrated chips. Silicon photonics, which uses silicon to realize the functions of light generation, modulation, transmission, manipulation, and detection, has been recognized as one of the ideal technologies to break through the bottleneck of super-large capacity, ultra-high-speed information transmission and processing of computers and communications. The high attention of researchers has become a hot spot in the field of optoelectronics research in recent years.

Silicon-based optical waveguide is the medium that guides light waves to propagate in it. It is the most basic unit structure in optoelectronic chips and integration technology. Its main functions include confinement, transmission, and coupling of light waves. The types of optical waveguides include rectangular waveguides and ridge waveguides. Both types of waveguides require an etching process. The sidewalls of the waveguides formed by etching are rough. The greater the roughness, the more serious the scattering of light, and the greater the transmission loss of light inside the waveguide, which limits the integration of large-scale optoelectronic chips.

Contents of the invention

In view of the above defects in the prior art, an ultra-low loss silicon waveguide and its preparation method are provided, which transfers the waveguide pattern to the buried layer, avoiding the sidewall roughness caused by etching in the conventional preparation of silicon waveguide solutions High problem, the prepared silicon waveguide has the advantage of ultra-low loss. At the same time, the silicon waveguide prepared by this scheme can be vertically integrated with the top silicon, which has the advantage of 3D photonic integration.

A method for preparing an ultra-low loss silicon waveguide, comprising the following steps:

S1 selects an SOI wafer as a substrate, the SOI wafer includes a first silicon layer, a first silicon dioxide layer, and a second silicon layer arranged in sequence from top to bottom, the first silicon layer and the second silicon layer The constituent material is silicon, and the constituent material of the first silicon dioxide layer is silicon dioxide;

S2 thermally oxidizing the upper part of the first silicon layer to form a second silicon dioxide layer;

S3 etching the second silicon dioxide layer, so that the etched area of the second silicon dioxide layer forms a first depression, and the remaining area is a first protrusion;

S4 depositing silicon dioxide with the same thickness on the first depression and the first protrusion to form a third silicon dioxide layer;

S5 implants oxygen ions above the third silicon dioxide layer, so that an oxygen-rich ion layer is formed in the first silicon layer, and the oxygen-rich ion layer separates the lower part of the first silicon layer into upper and lower layers, and the oxygen-rich ion layer corresponds to the The first protrusion forms a second protrusion, and a second depression is formed corresponding to the first depression;

S6 using an etching process to remove the second silicon dioxide layer and the third silicon dioxide layer;

S7 depositing silicon dioxide on the first silicon layer to form a fourth silicon dioxide layer;

S8 high-temperature annealing, so that oxygen ions in the oxygen ion-rich layer react with silicon atoms to form a fifth silicon dioxide layer, the second protrusions are converted to form third protrusions, and the second depressions are converted to form third depression;

S9 uses an etching process to remove the fourth silicon dioxide layer to obtain a finished product. In the finished product, the first silicon layer below the fifth silicon dioxide layer is the waveguide layer, and the first silicon layer below the third raised portion is the waveguide layer. Silicon waveguide.

Optionally, the thickness of the first silicon layer in the step S1 is 600 nm; the thickness of the second silicon dioxide layer in the step S2 is 100 nm.

Optionally, in the step S3, the second silicon dioxide layer is etched until the first silicon layer below the second silicon dioxide layer is exposed, and the etching operation is stopped; and/or, the etching method in the step S3 is selected Dry etching or wet etching of plasma etching or reactive ion etching.

Optionally, the thickness of the third silicon dioxide layer in the step S4 is 50 nm; and/or, the deposition method in the step S4 is plasma-enhanced chemical (PECVD) vapor deposition.

Optionally, in the step S5, the oxygen ion implantation dose ranges from 2×10 ¹⁷ to 7×10 ¹⁷ per square centimeter.

Optionally, in the step S5, the ion implantation energy range is 150-200KeV.

Optionally, in the step S5, the wafer is rotated 90° around the center of the wafer in the same direction for every quarter of the total dose of oxygen ions implanted.

Optionally, in the step S7, the thickness of the fourth silicon dioxide layer is 350 nm; and/or, the deposition method in the step S7 is inductively coupled plasma enhanced chemical vapor deposition.

Optionally, in the step S8, the annealing temperature is 1300-1350° C., and the annealing time is 5-8 hours.

An ultra-low-loss silicon waveguide prepared by the above-mentioned preparation method is characterized in that it includes a first silicon layer, a fifth silicon dioxide layer, a waveguide layer, a first silicon dioxide layer and a second silicon dioxide layer arranged in sequence from top to bottom. Two silicon layers; the middle part of the fifth silicon dioxide layer protrudes upwards, and the waveguide layer below the protrusions of the fifth silicon dioxide layer is a silicon waveguide.

The preparation method of an ultra-low loss silicon waveguide disclosed in the present invention transfers the waveguide pattern to the buried layer through oxygen ion implantation and high-temperature annealing, avoiding the roughness of the side wall caused by etching in the conventional preparation of silicon waveguides To solve the problem of high density, the prepared silicon waveguide has the advantage of ultra-low loss. At the same time, the silicon waveguide prepared by this scheme can be vertically integrated with the top silicon, which has the advantage of 3D photonic integration.

Description of drawings

FIG. 1 schematically shows a flow chart of a method for manufacturing an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;

Fig. 2 schematically shows the distribution diagram of the concentration of oxygen ions in the oxygen ion-rich layer with the implantation depth under the condition of the third silicon dioxide layer with different thicknesses according to an embodiment of the present disclosure;

Fig. 3 schematically shows a schematic structural diagram of an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;

In the figure, the first silicon layer-1, the first silicon dioxide layer-2, the second silicon layer-3, the second silicon dioxide layer-4, the first raised portion-5, the third silicon dioxide layer- 6. Oxygen-rich ion layer-7, fourth silicon dioxide layer-8, fifth silicon dioxide layer-9, silicon waveguide-10, waveguide layer-11.

Detailed ways

Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. It should be understood, however, that these descriptions are exemplary only, and are not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the present disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the present disclosure. The terms "comprising", "comprising", etc. used herein indicate the presence of stated features, steps, operations and/or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

Example 1

Embodiments of the present disclosure provide an ultra-low loss silicon waveguide and a manufacturing method thereof.

FIG. 1 schematically shows a flow chart of a method for manufacturing an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;

A method for preparing an ultra-low loss silicon waveguide, comprising the following steps:

S1 selects the SOI wafer as the substrate, the SOI wafer includes the first silicon layer 1, the first silicon dioxide layer 2 and the second silicon layer 3 arranged in sequence from top to bottom, the first silicon layer 1 and the second silicon layer The composition material of the disilicon layer 3 is silicon, and the composition material of the first silicon dioxide layer 2 is silicon dioxide;

S2 thermally oxidizes the upper part of the first silicon layer 1 to form a second silicon dioxide layer 4;

S3 etching the second silicon dioxide layer 4, so that the etched area of the second silicon dioxide layer 4 forms a first depression, and the remaining area is a first protrusion 5;

S4 depositing silicon dioxide with the same thickness above the first concave portion and the first protruding portion 5 to form a third silicon dioxide layer 6;

S5 implants oxygen ions above the third silicon dioxide layer 6, so that an oxygen-rich ion layer 7 is formed in the first silicon layer 1, and the oxygen-rich ion layer 7 separates the lower part of the first silicon layer 1 into upper and lower layers. The oxygen ion layer 7 includes a second protrusion and a second depression, the second protrusion below the first protrusion 5 corresponds to the second depression below the first depression;

S6 using an etching process to remove the second silicon dioxide layer 4 and the third silicon dioxide layer 6;

S7 deposits silicon dioxide on the first silicon layer 1 to form a fourth silicon dioxide layer 8;

S8 high-temperature annealing, so that the oxygen ions in the oxygen-rich ion layer 7 react with silicon atoms, and the oxygen-rich ion layer 7 after the reaction is the fifth silicon dioxide layer 9, and the second raised portion is converted into a third raised portion, the second recess is converted into a third recess;

S9 uses an etching process to remove the fourth silicon dioxide layer 8 to produce a finished product. In the finished product, the first silicon layer 1 below the fifth silicon dioxide layer 9 is the waveguide layer 11, and the first silicon layer 1 below the third raised portion is The silicon layer 1 is the silicon waveguide 10 .

Further, the thickness of the first silicon layer 1 in the step S1 is 600 nm.

By selecting the first silicon layer 1 with a thickness of 600nm, while forming the buried silicon waveguide 10, a sufficient thickness of the remaining first silicon layer 1 can be left for preparing other optoelectronic devices, thereby realizing 3D photonic integration.

Further, the thickness of the second silicon dioxide layer 4 in the step S2 is 100 nm.

Further, in the step S2, the second silicon dioxide layer 4 is etched until the first silicon layer 1 under the second silicon dioxide layer 4 is exposed, and the etching operation is stopped.

Further, the etching method is dry etching or wet etching of plasma etching or reactive ion etching.

Generally speaking, the thickness of the second silicon dioxide layer 4 is the height of the ridge of the silicon waveguide 10, that is, the thickness of the second raised portion is the height of the ridge of the silicon waveguide 10. Such a design can be made according to requirements. thickness of the silicon waveguide 10 .

Further, the thickness of the third silicon dioxide layer 6 in the step S4 is 50 nm.

Further, the deposition method is plasma-enhanced chemical vapor deposition.

Further, in the step S5, the dose range of oxygen ion implantation is 2×10 ¹⁷ per square centimeter.

Further, in the step S5, the ion implantation energy is 150KeV.

Further, in the step S5, the wafer is rotated 90° around the center of the wafer in the same direction for every quarter of the total dose of oxygen ions implanted.

2 schematically shows the distribution of oxygen ion concentration in the oxygen ion-rich layer with implantation depth under the condition of the third silicon dioxide layer with thicknesses of 0nm, 50nm, 100nm and 150nm respectively according to an embodiment of the present disclosure;

Since the thicknesses of the first recessed portion and the first protruding portion 5 formed after the second silicon dioxide layer 4 are etched are different, each region of the silicon dioxide barrier layer formed after it is combined with the third silicon dioxide layer 6 The thickness is also inconsistent. The silicon dioxide barrier layer will reduce the oxygen ion implantation speed, thereby affecting the oxygen ion implantation depth, the thicker the silicon dioxide barrier layer, the shallower the oxygen ion implantation depth, which makes the oxygen-rich area directly below the first raised portion 5 The ion layer 7 is shallower than the oxygen-rich ion layer 7 below the first recess.

Further, in the step S6, the etching method is plasma etching.

Further, in the step S7, the thickness of the fourth silicon dioxide layer 8 is 350 nm, and the deposition method is inductively coupled plasma enhanced chemical vapor deposition.

The provision of the fourth silicon dioxide layer 8 prevents the first silicon layer 1 from being oxidized during the subsequent high temperature annealing process.

Further, in the step S8, the annealing temperature is 1300° C., and the annealing time is 5 hours.

The melting point of silicon is 1410°C, the melting point of silicon dioxide is 1723°C, and the annealing temperature is set to 1300°C, so that silicon and silicon dioxide are in a state between solid and liquid, so that the silicon waveguide 10 and the fifth silicon dioxide layer The interface of 9 is smooth, thereby reducing the loss of the silicon waveguide 10; preferably, the annealing time is 5 hours; during the annealing process, the reaction between oxygen ions and silicon atoms is slow, including the nucleation, growth, merging and final formation of silicon dioxide precipitates For a uniform fifth silicon dioxide layer 9 , the annealing time is too short to form a uniform fifth silicon dioxide layer 9 , and an annealing time of 5 hours is the optimum time for forming a uniform fifth silicon dioxide layer 9 .

Since the oxygen ion implantation depth directly below the first raised portion 5 is shallower than that of other regions, the fifth silicon dioxide layer 9 directly below the first raised portion 5 protrudes upward, thereby forming a silicon waveguide 10 .

Due to the high annealing temperature and long annealing time, silicon and silicon dioxide are in the state of solid and liquid, their viscosity is reduced, and their atoms and molecules are almost in a fluid state, thus forming a very smooth interface between silicon and silicon dioxide, avoiding the conventional Due to the problem of rough side walls caused by etching in the preparation method, the silicon waveguide 10 has ultra-low loss characteristics; the damage caused by ion implantation in the first silicon layer 1 is repaired in high temperature annealing, and can be used to prepare other The optoelectronic device can be vertically integrated with the formed ultra-low loss silicon waveguide 10 to realize 3D integration and adapt to large-scale optoelectronic integration in the future.

Fig. 3 schematically shows a schematic structural view of an ultra-low loss silicon waveguide according to an embodiment of the present disclosure.

An ultra-low-loss silicon waveguide prepared by the above-mentioned preparation method is characterized in that it includes a first silicon layer 1, a fifth silicon dioxide layer 9, a waveguide layer 11, a first silicon dioxide layer arranged in sequence from top to bottom layer 2 and the second silicon layer 3; the middle part of the fifth silicon dioxide layer 9 protrudes upwards, and the waveguide layer 11 below the fifth silicon dioxide layer 9 is a silicon waveguide 10 .

Example 2

Embodiments of the present disclosure provide an ultra-low loss silicon waveguide and a manufacturing method thereof.

FIG. 1 schematically shows a flow chart of a method for manufacturing an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;

A method for preparing an ultra-low loss silicon waveguide, comprising the following steps:

S1 selects the SOI wafer as the substrate, the SOI wafer includes the first silicon layer 1, the first silicon dioxide layer 2 and the second silicon layer 3 arranged in sequence from top to bottom, the first silicon layer 1 and the second silicon layer The composition material of the disilicon layer 3 is silicon, and the composition material of the first silicon dioxide layer 2 is silicon dioxide;

S2 thermally oxidizes the upper part of the first silicon layer 1 to form a second silicon dioxide layer 4;

S3 etching the second silicon dioxide layer 4, so that the etched area of the second silicon dioxide layer 4 forms a first depression, and the remaining area is a first protrusion 5;

S4 depositing silicon dioxide with the same thickness above the first concave portion and the first protruding portion 5 to form a third silicon dioxide layer 6;

S5 implants oxygen ions above the third silicon dioxide layer 6, so that an oxygen-rich ion layer 7 is formed in the first silicon layer 1, and the oxygen-rich ion layer 7 separates the lower part of the first silicon layer 1 into upper and lower layers. The oxygen ion layer 7 includes a second protrusion and a second depression, the second protrusion below the first protrusion 5 corresponds to the second depression below the first depression;

S6 using an etching process to remove the second silicon dioxide layer 4 and the third silicon dioxide layer 6;

S7 deposits silicon dioxide on the first silicon layer 1 to form a fourth silicon dioxide layer 8;

S8 high-temperature annealing, so that the oxygen ions in the oxygen-rich ion layer 7 react with silicon atoms, and the oxygen-rich ion layer 7 after the reaction is the fifth silicon dioxide layer 9, and the second raised portion is converted into a third raised portion, the second recess is converted into a third recess;

S9 uses an etching process to remove the fourth silicon dioxide layer 8 to produce a finished product. In the finished product, the first silicon layer 1 below the fifth silicon dioxide layer 9 is the waveguide layer 11, and the first silicon layer 1 below the third raised portion is The silicon layer 1 is the silicon waveguide 10 .

Further, the thickness of the first silicon layer 1 in the step S1 is 600 nm.

By selecting the first silicon layer 1 with a thickness of 600nm, while forming the buried silicon waveguide 10, a sufficient thickness of the remaining first silicon layer 1 can be left for preparing other optoelectronic devices, thereby realizing 3D photonic integration.

Further, the thickness of the second silicon dioxide layer 4 in the step S2 is 100 nm.

Further, in the step S2, the second silicon dioxide layer 4 is etched until the first silicon layer 1 under the second silicon dioxide layer 4 is exposed, and the etching operation is stopped.

Further, the etching method is dry etching or wet etching of plasma etching or reactive ion etching.

Generally speaking, the thickness of the second silicon dioxide layer 4 is the height of the ridge of the silicon waveguide 10, that is, the thickness of the second raised portion is the height of the ridge of the silicon waveguide 10. Such a design can be made according to requirements. thickness of the silicon waveguide 10 .

Further, the thickness of the third silicon dioxide layer 6 in the step S4 is 50 nm.

Further, the deposition method is plasma-enhanced chemical vapor deposition.

Further, in the step S5, the dose range of oxygen ion implantation is 7×10 ¹⁷ per square centimeter.

Further, in the step S5, the ion implantation energy range is 200KeV.

Further, in the step S5, the wafer is rotated 90° around the center of the wafer in the same direction for every quarter of the total dose of oxygen ions implanted.

2 schematically shows the distribution of oxygen ion concentration in the oxygen ion-rich layer with implantation depth under the condition of the third silicon dioxide layer with thicknesses of 0nm, 50nm, 100nm and 150nm respectively according to an embodiment of the present disclosure;

Since the thicknesses of the first recessed portion and the first protruding portion 5 formed after the second silicon dioxide layer 4 are etched are different, each region of the silicon dioxide barrier layer formed after it is combined with the third silicon dioxide layer 6 The thickness is also inconsistent. The silicon dioxide barrier layer will reduce the oxygen ion implantation speed, thereby affecting the oxygen ion implantation depth, the thicker the silicon dioxide barrier layer, the shallower the oxygen ion implantation depth, which makes the oxygen-rich area directly below the first raised portion 5 The ion layer 7 is shallower than the oxygen-rich ion layer 7 below the first recess.

Further, in the step S6, the etching method is plasma etching.

Further, in the step S7, the thickness of the fourth silicon dioxide layer 8 is 350 nm, and the deposition method is inductively coupled plasma enhanced chemical vapor deposition.

The setting of the fourth silicon dioxide layer 8 prevents the first silicon layer 1 from being oxidized during the subsequent high temperature annealing process

Further, in the step S8, the annealing temperature is 1350° C., and the annealing time is 8 hours.

The melting point of silicon is 1410°C, the melting point of silicon dioxide is 1723°C, and the annealing temperature is set to 1350°C, so that silicon and silicon dioxide are in a state between solid and liquid, so that the silicon waveguide 10 and the fifth silicon dioxide layer The interface of 9 is smooth, thereby reducing the loss of the silicon waveguide 10; preferably, the annealing time is 8 hours; during the annealing process, the reaction between oxygen ions and silicon atoms is slow, including the nucleation, growth, merging and final formation of silicon dioxide precipitates. For a uniform fifth silicon dioxide layer 9 , the annealing time is too short to form a uniform fifth silicon dioxide layer 9 , and an annealing time of 8 hours is the optimum time for forming a uniform fifth silicon dioxide layer 9 .

Since the oxygen ion implantation depth directly below the first raised portion 5 is shallower than that of other regions, the fifth silicon dioxide layer 9 directly below the first raised portion 5 protrudes upward, thereby forming a silicon waveguide 10 .

Due to the high annealing temperature and long annealing time, silicon and silicon dioxide are in the state of solid and liquid, their viscosity is reduced, and their atoms and molecules are almost in a fluid state, thus forming a very smooth interface between silicon and silicon dioxide, avoiding the conventional Due to the problem of rough side walls caused by etching in the preparation method, the silicon waveguide 10 has ultra-low loss characteristics; the damage caused by ion implantation in the first silicon layer 1 is repaired in high temperature annealing, and can be used to prepare other The optoelectronic device can be vertically integrated with the formed ultra-low loss silicon waveguide 10 to realize 3D integration and adapt to large-scale optoelectronic integration in the future.

Fig. 3 schematically shows a schematic structural view of an ultra-low loss silicon waveguide according to an embodiment of the present disclosure.

An ultra-low-loss silicon waveguide prepared by the above-mentioned preparation method is characterized in that it includes a first silicon layer 1, a fifth silicon dioxide layer 9, a waveguide layer 11, a first silicon dioxide layer arranged in sequence from top to bottom layer 2 and the second silicon layer 3; the middle part of the fifth silicon dioxide layer 9 protrudes upwards, and the waveguide layer 11 below the fifth silicon dioxide layer 9 is a silicon waveguide 10 .

Example 3

Embodiments of the present disclosure provide an ultra-low loss silicon waveguide and a manufacturing method thereof.

FIG. 1 schematically shows a flow chart of a method for manufacturing an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;

A method for preparing an ultra-low loss silicon waveguide, comprising the following steps:

S1 selects the SOI wafer as the substrate, the SOI wafer includes the first silicon layer 1, the first silicon dioxide layer 2 and the second silicon layer 3 arranged in sequence from top to bottom, the first silicon layer 1 and the second silicon layer The composition material of the disilicon layer 3 is silicon, and the composition material of the first silicon dioxide layer 2 is silicon dioxide;

S2 thermally oxidizes the upper part of the first silicon layer 1 to form a second silicon dioxide layer 4;

S3 etching the second silicon dioxide layer 4, so that the etched area of the second silicon dioxide layer 4 forms a first depression, and the remaining area is a first protrusion 5;

S4 depositing silicon dioxide with the same thickness above the first concave portion and the first protruding portion 5 to form a third silicon dioxide layer 6;

S5 implants oxygen ions above the third silicon dioxide layer 6, so that an oxygen-rich ion layer 7 is formed in the first silicon layer 1, and the oxygen-rich ion layer 7 separates the lower part of the first silicon layer 1 into upper and lower layers. The oxygen ion layer 7 includes a second protrusion and a second depression, the second protrusion below the first protrusion 5 corresponds to the second depression below the first depression;

S6 using an etching process to remove the second silicon dioxide layer 4 and the third silicon dioxide layer 6;

S7 deposits silicon dioxide on the first silicon layer 1 to form a fourth silicon dioxide layer 8;

S8 high-temperature annealing, so that the oxygen ions in the oxygen-rich ion layer 7 react with silicon atoms, and the oxygen-rich ion layer 7 after the reaction is the fifth silicon dioxide layer 9, and the second raised portion is converted into a third raised portion, the second recess is converted into a third recess;

S9 uses an etching process to remove the fourth silicon dioxide layer 8 to produce a finished product. In the finished product, the first silicon layer 1 below the fifth silicon dioxide layer 9 is the waveguide layer 11, and the first silicon layer 1 below the third raised portion is The silicon layer 1 is the silicon waveguide 10

Further, the thickness of the first silicon layer 1 in the step S1 is 600 nm.

By selecting the first silicon layer 1 with a thickness of 600nm, while forming the buried silicon waveguide 10, a sufficient thickness of the remaining first silicon layer 1 can be left for preparing other optoelectronic devices, thereby realizing 3D photonic integration.

Further, the thickness of the second silicon dioxide layer 4 in the step S2 is 100 nm.

Further, in the step S2, the second silicon dioxide layer 4 is etched until the first silicon layer 1 under the second silicon dioxide layer 4 is exposed, and the etching operation is stopped.

Further, the etching method is dry etching or wet etching of plasma etching or reactive ion etching.

Generally speaking, the thickness of the second silicon dioxide layer 4 is the height of the ridge of the silicon waveguide 10, that is, the thickness of the second raised portion is the height of the ridge of the silicon waveguide 10. Such a design can be made according to requirements. thickness of the silicon waveguide 10 .

Further, the thickness of the third silicon dioxide layer 6 in the step S4 is 50 nm.

Further, the deposition method is plasma-enhanced chemical vapor deposition.

Further, in the step S5, the dose range of oxygen ion implantation is 5×10 ¹⁷ per square centimeter.

Further, in the step S5, the ion implantation energy range is 180KeV.

Further, in the step S5, the wafer is rotated 90° around the center of the wafer in the same direction for every quarter of the total dose of oxygen ions implanted.

2 schematically shows the distribution of oxygen ion concentration in the oxygen ion-rich layer with implantation depth under the condition of the third silicon dioxide layer with thicknesses of 0nm, 50nm, 100nm and 150nm respectively according to an embodiment of the present disclosure;

Since the thicknesses of the first recessed portion and the first protruding portion 5 formed after the second silicon dioxide layer 4 are etched are different, each region of the silicon dioxide barrier layer formed after it is combined with the third silicon dioxide layer 6 The thickness is also inconsistent. The silicon dioxide barrier layer will reduce the oxygen ion implantation speed, thereby affecting the oxygen ion implantation depth, the thicker the silicon dioxide barrier layer, the shallower the oxygen ion implantation depth, which makes the oxygen-rich area directly below the first raised portion 5 The ion layer 7 is shallower than the oxygen-rich ion layer 7 below the first recess.

The oxygen ion implantation dose and energy determine the thickness and depth of the oxygen ion-rich layer 7 respectively. In order to obtain a low defect density, high quality, continuous silicon dioxide buried layer in this figure, the total oxygen ion implantation dose D is 5×10 ¹⁷ / cm ² , the ion implantation energy is 180KeV, and when the thickness of the third silicon dioxide layer 6 is 50nm, the concentration of oxygen ions is mainly distributed at a depth of 380nm, which can easily form the silicon waveguide 10 and leave enough top layer Silicon, so the thickness of the third silicon dioxide layer 6 is set to 50 nm.

Further, in the step S6, the etching method is plasma etching.

Further, in the step S7, the thickness of the fourth silicon dioxide layer 8 is 350 nm, and the deposition method is inductively coupled plasma enhanced chemical vapor deposition.

The setting of the fourth silicon dioxide layer 8 prevents the first silicon layer 1 from being oxidized during the subsequent high temperature annealing process

Further, in the step S8, the annealing temperature is 1325° C., and the annealing time is 6.5 hours.

The melting point of silicon is 1410°C, the melting point of silicon dioxide is 1723°C, and the annealing temperature is set at 1300-1350°C, so that silicon and silicon dioxide are in the state of solid and liquid, so that the silicon waveguide 10 and the fifth dioxide The interface of the silicon layer 9 is smooth, thereby reducing the loss of the silicon waveguide 10; preferably, the annealing time is 5 to 8 hours; during the annealing process, the reaction between oxygen ions and silicon atoms is slow, including the nucleation, growth, and Merge and finally form a uniform fifth silicon dioxide layer 9. The annealing time is too short to form a uniform fifth silicon dioxide layer 9. The annealing time is 5 to 8 hours to form a uniform fifth silicon dioxide layer 9 best time.

Since the oxygen ion implantation depth directly below the first raised portion 5 is shallower than that of other regions, the fifth silicon dioxide layer 9 directly below the first raised portion 5 protrudes upward, thereby forming a silicon waveguide 10 .

Due to the high annealing temperature and long annealing time, silicon and silicon dioxide are in the state of solid and liquid, their viscosity is reduced, and their atoms and molecules are almost in a fluid state, thus forming a very smooth interface between silicon and silicon dioxide, avoiding the conventional Due to the problem of rough side walls caused by etching in the preparation method, the silicon waveguide 10 has ultra-low loss characteristics; the damage caused by ion implantation in the first silicon layer 1 is repaired in high temperature annealing, and can be used to prepare other The optoelectronic device can be vertically integrated with the formed ultra-low loss silicon waveguide 10 to realize 3D integration and adapt to large-scale optoelectronic integration in the future.

Fig. 3 schematically shows a schematic structural view of an ultra-low loss silicon waveguide according to an embodiment of the present disclosure.

An ultra-low-loss silicon waveguide prepared by the above-mentioned preparation method is characterized in that it includes a first silicon layer 1, a fifth silicon dioxide layer 9, a waveguide layer 11, a first silicon dioxide layer arranged in sequence from top to bottom Layer 2 and the second silicon layer 3; the middle part of the fifth silicon dioxide layer 9 protrudes upwards, and the waveguide layer 11 below the fifth silicon dioxide layer 9 is a silicon waveguide 10. At this time, the first silicon layer 1 has a thickness of 220 nm.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (10)

1. A preparation method of an ultra-low loss silicon waveguide is characterized by comprising the following steps:

s1, selecting an SOI wafer as a substrate, wherein the SOI wafer comprises a first silicon layer (1), a first silicon dioxide layer (2) and a second silicon layer (3) which are sequentially arranged from top to bottom, and the first silicon layer (1) is made of silicon;

s2, thermally oxidizing the upper part of the first silicon layer (1) to form a second silicon dioxide layer (4);

s3, etching the second silicon dioxide layer (4) to enable the etched area of the second silicon dioxide layer (4) to form a first concave part, and enabling the rest area to be a first convex part (5);

s4, depositing silicon dioxide with the same thickness above the first concave part and the first convex part (5) to form a third silicon dioxide layer (6);

s5, injecting oxygen ions above the third silicon dioxide layer (6) to form an oxygen-enriched ion layer (7) in the first silicon layer (1), wherein the oxygen-enriched ion layer (7) divides the lower part of the first silicon layer (1) into an upper layer and a lower layer, the oxygen-enriched ion layer (7) forms a second protruding part corresponding to the first protruding part (5) and a second recessed part corresponding to the first recessed part;

s6, removing the second silicon dioxide layer (4) and the third silicon dioxide layer (6) by using an etching process;

s7, depositing silicon dioxide above the first silicon layer (1) to form a fourth silicon dioxide layer (8);

s8, annealing at high temperature, so that oxygen ions in the oxygen-rich ion layer (7) react with silicon atoms to form a fifth silicon dioxide layer (9), the second convex parts are converted to form third convex parts, and the second concave parts are converted to form third concave parts;

and S9, removing the fourth silicon dioxide layer (8) by using an etching process to obtain a finished product, wherein the first silicon layer (1) below the fifth silicon dioxide layer (9) in the finished product is the waveguide layer (11), and the first silicon layer (1) below the third bulge is the silicon waveguide (10).

2. The production method according to claim 1, wherein the thickness of the first silicon layer (1) in step S1 is 600nm; the thickness of the second silicon dioxide layer (4) in the step S2 is 100nm.

3. The manufacturing method according to claim 1, wherein the etching operation is stopped in the step S3 until the second silicon oxide layer (4) is etched until the first silicon layer (1) under the second silicon oxide layer (4) is exposed; and/or the etching method in the step S3 is dry etching or wet etching of plasma etching or reactive ion etching.

4. The method according to claim 1, wherein the thickness of the third silicon dioxide layer (6) in step S4 is 50nm; and/or the deposition method in the step S4 is plasma enhanced chemical vapor deposition.

5. The method according to claim 1, wherein the dose of the oxygen ion implantation in step S5 is in a range of 2 x 10 per square centimeter ¹⁷ ～7×10 ¹⁷ And (4) respectively.

6. The method according to claim 1, wherein in step S5, the ion implantation energy is in a range of 150-200KeV.

7. The method as claimed in claim 1, wherein in step S5, the wafer is rotated 90 ° in the same direction around the center of the wafer for every one-fourth of the total implanted oxygen ion dose.

8. The production method according to claim 1, wherein in the step S7, the thickness of the fourth silicon dioxide layer (8) is 350nm; and/or the deposition method adopts inductively coupled plasma enhanced chemical vapor deposition.

9. The method according to claim 1, wherein in the step S8, the annealing temperature is 1300 to 1350 ℃ and the annealing time is 5 to 8 hours.

10. An ultra-low loss silicon waveguide produced by the production method according to any one of claims 1 to 9, characterized in that: the waveguide structure comprises a first silicon layer (1), a fifth silicon dioxide layer (9), a waveguide layer (11), a first silicon dioxide layer (2) and a second silicon layer (3) which are arranged from top to bottom in sequence; the middle part of the fifth silicon dioxide layer (9) protrudes upwards, and the waveguide layer (11) below the protrusion of the fifth silicon dioxide layer (9) is a silicon waveguide (10).

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