CN113725171A

CN113725171A - Semiconductor package device and method of manufacturing the same

Info

Publication number: CN113725171A
Application number: CN202110885963.4A
Authority: CN
Inventors: 吕文隆
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2021-08-03
Filing date: 2021-08-03
Publication date: 2021-11-30

Abstract

The present disclosure relates to a semiconductor packaging device and a method for manufacturing the same. The semiconductor packaging device includes: a circuit layer having a first surface, the circuit layer including conductive traces, and the conductive traces are at least partially exposed on the first surface; a protection layer, disposed on the first surface Surface and contact the conductive trace, the thermal expansion coefficient of the protective layer is smaller than the thermal expansion coefficient of the conductive trace; a protective layer with a thermal expansion coefficient smaller than the conductive trace is provided on one side of the conductive trace to reduce the risk of cracking of the conductive trace.

Description

Semiconductor package device and method of manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor packaging technologies, and in particular, to a semiconductor packaging device and a method for manufacturing the same.

Background

The thermal expansion coefficient of the Fan-Out on Substrate (FOCoS) product is different among materials, so that thermal stress is generated in the thermal cycle process, the influence of the stress borne by the conductive trace between two chips is generated by the difference between the thermal expansion coefficient of the material of the conductive trace and the material surrounding the conductive trace, namely, the thermal expansion coefficient of the dielectric material surrounding the conductive trace is larger than that of the copper of the conductive trace, and the conductive trace is easy to crack due to the tensor Strain (Strain) or tensile deformation (Elongation) borne by the conductive trace in the thermal cycle process.

Disclosure of Invention

In a first aspect, the present disclosure provides a semiconductor package device, comprising:

a circuit layer having a first surface, the circuit layer including a conductive trace at least partially exposed at the first surface;

and the protective layer is arranged on the first surface and contacts the conductive trace, and the thermal expansion coefficient of the protective layer is smaller than that of the conductive trace.

In some optional embodiments, the apparatus further comprises:

the first chip and the second chip are arranged on the first surface, and the first chip is electrically connected with the second chip through the conductive trace.

In some alternative embodiments, the first chip active or inactive face is disposed towards the first surface.

In some optional embodiments, the second chip active or inactive face is disposed towards the first surface.

In some optional embodiments, the circuit layer further comprises a dielectric layer, the conductive trace being disposed on the dielectric layer;

the contact area of the protective layer and the conductive trace is larger than the contact area of the dielectric layer and the conductive trace.

In some alternative embodiments, the first surface is provided with a groove, and the conductive trace is at least partially disposed at the bottom of the groove and exposed at the first surface through the groove;

the protective layer is at least partially disposed in the recess.

In some alternative embodiments, the protective layer covers the conductive traces.

In some alternative embodiments, the protective layer comprises an underfill.

In some optional embodiments, the apparatus further comprises:

and the packaging material is arranged on the first surface and covers the first chip and the second chip.

In some optional embodiments, the inactive surface of the first chip and/or the inactive surface of the second chip are substantially coplanar with the upper surface of the encapsulant.

In some alternative embodiments, the wiring layer has a second surface opposite the first surface; the device further comprises:

and the electric connecting piece is arranged on the second surface.

In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, comprising:

providing a circuit layer, wherein the circuit layer is provided with a first surface, and a conductive trace is buried in the circuit layer;

removing at least a portion of the circuit layer through the first surface to expose the conductive traces at least partially at the first surface;

and arranging a protective layer on the first surface so that the protective layer is contacted with the conductive traces, wherein the thermal expansion coefficient of the protective layer is smaller than that of the conductive traces.

In a semiconductor package device and a method of manufacturing the same provided by the present disclosure, designing a semiconductor package device includes: a circuit layer having a first surface, the circuit layer including a conductive trace, the conductive trace being at least partially exposed at the first surface; the protective layer is arranged on the first surface and contacts the conductive trace, and the thermal expansion coefficient of the protective layer is smaller than that of the conductive trace; therefore, one side of the conductive trace is contacted with the protective layer with the thermal expansion coefficient smaller than that of the conductive trace, and the tension of the conductive trace on one side of the circuit layer can be transmitted to one side of the protective layer in the thermal process, so that the risk of fracture of the conductive trace caused by the tension deformation of the circuit layer in the thermal process is reduced.

Drawings

Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1A is a schematic longitudinal cross-sectional structure of one embodiment of a semiconductor package device according to the present disclosure;

FIG. 1B is a partially enlarged schematic view of a dotted line portion of FIG. 1A;

FIGS. 1C-1E are enlarged schematic partial longitudinal cross-sectional views of the dotted line portion of FIG. 1A in different embodiments corresponding to a direction perpendicular to the longitudinal cross-sectional view of FIG. 1A;

2A-2G are schematic longitudinal cross-sectional structures of various embodiments of semiconductor packaging devices according to the present disclosure;

fig. 3A-3I are schematic longitudinal cross-sectional structural views of a semiconductor package device fabricated at various stages according to one embodiment of the present disclosure.

Description of the symbols:

11-a line layer; 11 a-a first surface; 11 b-a second surface; 110-sub-circuit layer; 12-a protective layer; 13-a first chip; 14-a second chip; 111-conductive traces; 112-a dielectric layer; 1121-projection; 113-a groove; 1131 — groove extensions; 15-packaging material; 16-an electrical connection; 17-routing; 18-a substrate; 181-substrate conductive traces; 182-substrate protection layer; 21-a first carrier plate; 22-a second carrier.

Detailed Description

The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.

It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.

It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.

In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict.

Referring to fig. 1A and 1B, fig. 1A is a schematic longitudinal cross-sectional structure of an embodiment of a semiconductor package device according to the present disclosure, and fig. 1B is a partially enlarged schematic view of a dotted line portion in fig. 1A.

As shown in fig. 1A and 1B, the semiconductor package device 100A may include: a wiring layer 11 and a protective layer 12. Wherein:

the circuit layer 11 has a first surface 11a, and the circuit layer 11 includes a conductive trace 111, and the conductive trace 111 is at least partially exposed at the first surface 11 a.

The wiring layer 11 may be a wiring layer composed of a conductive material and a Dielectric material (Dielectric). Here, the dielectric material may include organic and/or inorganic substances, wherein the organic substance may be, for example: polyamide fiber (PA), Polyimide (PI), Poly-p-Phenylene Benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, PrePreg material or so-called PrePreg resin, PrePreg), ABF (Ajinomoto Build-up Film), etc., and inorganic matter may be, for example, silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc. The conductive material may include a seed layer and a metal layer. Here, the seed layer may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., and the metal layer may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The conductive traces 111 may be at least part of the conductive material making up the wiring layer 11.

And a protective layer 12 disposed on the first surface 11a and contacting the conductive trace 111, wherein a thermal expansion coefficient of the protective layer 12 is smaller than that of the conductive trace 111.

The material of the protective layer 12 is not particularly limited by the present disclosure, and the thermal expansion coefficient of the protective layer 12 may be smaller than that of the conductive traces 111, for example, the protective layer 12 may include an underfill, which may be, for example, an Epoxy (Epoxy).

One side of the conductive trace 111 is in contact with the dielectric material of the circuit layer 11, and the other side of the conductive trace 111 is at least partially in contact with the protection layer 12, and the thermal expansion coefficient of the protection layer 12 is smaller than that of the conductive trace 111, so that in a thermal process, tension generated by thermal expansion of the dielectric material of the circuit layer 11 is transmitted to the protection layer 12 through the conductive trace 111, thereby preventing tensile stress from concentrating on the conductive trace 111 and reducing the risk of cracking of the conductive trace 111.

In some alternative embodiments, the protective layer 12 covers the conductive traces 111.

In some alternative embodiments, as shown in fig. 1A, the apparatus 100A further comprises:

the first chip 13 and the second chip 14 are disposed on the first surface 11a, and the first chip 13 is electrically connected to the second chip 14 through the conductive trace 111.

The type of the first chip 13 and the second chip 14 is not particularly limited in this disclosure, and the first chip 13 and the second chip 14 may include, for example, a die (die), an ASIC (Application Specific Integrated Circuit) chip, an HBM (High Bandwidth Memory) chip, or the like. Here, the first chip 13 and the second chip 14 may be the same chip or different chips.

In some alternative embodiments, as shown in fig. 1A and 1B, the active surface of the first chip 13 is disposed toward the first surface 11A, and the active surface of the second chip 14 is disposed toward the first surface 11A.

In some alternative embodiments, as shown in fig. 1A and 1B, the circuit layer 11 further includes a dielectric layer 112, and the conductive traces 111 are disposed on the dielectric layer 112.

Fig. 1C is an enlarged view of a partial longitudinal cross section of the dashed portion in fig. 1A corresponding to a direction perpendicular to the longitudinal cross section of fig. 1A, and as shown in fig. 1C, the contact area between the protection layer 12 and the conductive trace 111 is larger than the contact area between the dielectric layer 112 and the conductive trace 111.

In some alternative embodiments, as shown in fig. 1A and 1B, the first surface 11A is provided with a groove 113, and the conductive trace 111 is at least partially disposed at the bottom of the groove 113 and exposed at the first surface 11A through the groove 113.

Here, the groove 113 may be formed by removing a dielectric material covering the conductive trace 111.

The protective layer 12 is at least partially disposed in the recess 113.

Fig. 1D is an enlarged schematic view of a partial longitudinal cross section of the dotted line portion in fig. 1A in a direction perpendicular to the longitudinal cross section of fig. 1A in some alternative embodiments, as shown in fig. 1D, in some alternative embodiments, the conductive traces 111 and the grooves 113 are correspondingly multiple, and a protrusion 1121 is disposed between two adjacent grooves 113, so that a contact area between the protection layer 12 and the grooves 113 can be increased, and adhesion can be improved.

Fig. 1E is an enlarged schematic view of a partial longitudinal cross section of the dashed line portion in fig. 1A corresponding to a direction perpendicular to the longitudinal cross section of fig. 1A in some alternative embodiments, as shown in fig. 1E, in some alternative embodiments, the groove 113 extends at least partially toward the circuit layer 11 through the plane of the conductive trace 111 to form a groove extension 1131, so as to increase the contact area between the protection layer 12 and the groove 113 and improve the adhesion.

In some alternative embodiments, as shown in fig. 1A, the semiconductor package apparatus 100A further includes:

and a sealing material 15 disposed on the first surface 11a and covering the first chip 13 and the second chip 14.

The sealing material 15 may be formed of various Molding compounds (Molding compounds). For example, the molding material may include Epoxy resin (Epoxy resin), Filler (Filler), Catalyst (Catalyst), Pigment (Pigment), Release Agent (Release Agent), Flame Retardant (Flame Retardant), Coupling Agent (Coupling Agent), Hardener (hardner), Low Stress absorbent (Low Stress Absorber), Adhesion Promoter (Adhesion Promoter), Ion trap (Ion Trapping Agent), and the like.

In some alternative embodiments, the inactive side of the first chip 13 and/or the inactive side of the second chip 14 are substantially coplanar with the upper surface of the encapsulation material 15.

Here, two surfaces being substantially coplanar can be considered to be: the difference in height between the two surfaces is no greater than 5 microns, no greater than 2 microns, no greater than 1 micron or no greater than 0.5 microns.

In some alternative embodiments, as shown in fig. 1A, the wiring layer 11 has a second surface 11b opposite to the first surface 11A; the semiconductor package device 100A further includes:

and the electric connection piece 16 is arranged on the second surface 11 b.

The electrical connections 16 may be, for example, Solder balls (Solder balls), Solder bumps (Solder bumps), Conductive pillars (Conductive balls), Solder pads (Solder pads), or the like.

And a substrate 18, wherein the upper surface of the substrate 18 is electrically connected with the second surface 11b through the electric connection piece 16.

The substrate 18 may be various types of substrates, and the present disclosure is not particularly limited thereto. The substrate 18 may include organic and/or inorganic substances, wherein the organic substances may be, for example: polyamide fibers (Polyamide, PA), Polyimide (PI), Epoxy resins (Epoxy), Poly-p-Phenylene Benzobisoxazole (PBO) fibers, FR-4 Epoxy glass cloth laminates, PP (preprg, PrePreg or so-called PrePreg, PrePreg), ABF (Ajinomoto Build-up Film), etc., and inorganic substances such as silicon (Si), glass (glass), ceramic (ceramic), silicon oxide, silicon nitride, tantalum oxide, etc.

The substrate 18 may also be, for example, a printed circuit board such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated fiberglass-based copper foil laminate, or the like.

The substrate 18 may also include interconnect structures (interconnects), such as Conductive traces (Conductive traces), Conductive vias (Conductive vias), and the like. Here, the conductive via may be a through hole, a buried hole, or a blind hole, and the through hole, the buried hole, or the blind hole may be filled with a conductive material such as a metal or a metal alloy, where the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof.

The above-mentioned structure of the conductive trace 111 and the protective layer 12 of the circuit layer 11 shown in fig. 1A can be applied to both the circuit layer and the substrate. Referring to fig. 2A, the semiconductor package device 200A shown in fig. 2A is similar to the semiconductor package device 100A shown in fig. 1A, except that the substrate 18 in fig. 2A is provided with a substrate wire trace 181 at the position of the dotted line, and a substrate protective layer 182 is provided on the wire trace.

With continued reference to fig. 2B, the semiconductor package device 200B shown in fig. 2B is similar to the semiconductor package device 100A shown in fig. 1A, except that the semiconductor package device 200B does not include the encapsulant 15 therein.

With continued reference to fig. 2C, the semiconductor package device 200C shown in fig. 2C is similar to the semiconductor package device 100A shown in fig. 1A, except that the encapsulant 15 is partially disposed between the first chip 13 and the circuit layer 11 and between the second chip 14 and the circuit layer 11, and the passivation layer 12 is not in contact with the first chip 13 and the second chip 14.

With continued reference to fig. 2D, the semiconductor package device 200D shown in fig. 2D is similar to the semiconductor package device 200C shown in fig. 2C, except that the encapsulant 15 covers the upper surface of the substrate 18, and the encapsulant 15 is partially disposed between the substrate 18 and the circuit layer 11.

With continued reference to fig. 2E, the semiconductor package device 200E shown in fig. 2E is similar to the semiconductor package device 100A shown in fig. 1A, except that the passivation layer 12 is partially disposed between the first chip 13 and the second chip 14.

With continued reference to fig. 2F, the semiconductor package device 200F shown in fig. 2F is similar to the semiconductor package device 100A shown in fig. 1A, except that the passivation layer 12 is partially disposed between the first chip 13 and the circuit layer 11, and the encapsulant 15 is partially disposed between the second chip 14 and the circuit layer 11.

With continued reference to fig. 2G, the semiconductor package device 200G shown in fig. 2G is similar to the semiconductor package device 100A shown in fig. 1A, except that the active surface of the first chip 13 is disposed toward the first surface 11A, the inactive surface of the second chip 14 is disposed toward the first surface 11A, and the active surface of the second chip 14 is electrically connected to the circuit layer 11 by the wire bonds 17.

In some alternative embodiments, the inactive side of the first chip 13 is disposed toward the first surface 11a, and the inactive side of the second chip 14 is disposed toward the first surface 11 a.

Referring now to fig. 3A-3I, fig. 3A-3I are schematic longitudinal cross-sectional structures of a semiconductor package device fabricated at various stages according to one embodiment of the present disclosure.

Referring to fig. 3A, a carrier board 21 is provided, a sub-circuit layer 110 is disposed on the carrier board 21, and the sub-circuit layer 110 includes a dielectric layer 112 and a conductive trace 111 disposed on the dielectric layer 112.

Referring to fig. 3B, a dielectric material is disposed on the sub-circuit layer 110 to form a circuit layer 11, and the circuit layer 11 has a first surface 11a far from the carrier plate 21.

Referring to fig. 3C, a groove 113 is formed in the circuit layer 11 through the first surface 11a corresponding to the conductive trace 111, and the conductive trace 111 is at least partially disposed at the bottom of the groove 113 and exposed at the first surface 11a through the groove 113.

Here, photolithography, etching or the like may be used to open the groove 113 in the wiring layer 11.

Referring to fig. 3D, first, the first chip 13 and the second chip 14 are provided.

Then, the first chip 13 and the second chip 14 are bonded to the wiring layer 11, respectively, so that the first chip 13 and the second chip 14 are electrically connected to the first surface 11 a.

Then, an underfill is disposed between the first chip 13 and the second chip 14 and the first surface 11a to form a protection layer 12, the protection layer 12 contacts the conductive traces 111, and a thermal expansion coefficient of the protection layer 12 is smaller than that of the conductive traces 111.

Here, an Underfill paste may be disposed between the first and

second chips

13 and 14 and the first surface 11a by Capillary Underfill (CUF) to form the protective layer 12.

Referring to fig. 3E, the encapsulant 15 is formed by molding, and the encapsulant 15 is disposed on the first surface 11a and covers the first chip 13 and the second chip 14.

The upper surface of the encapsulating material 15 is ground so that the upper surfaces of the first chip 13 and the second chip 14 are substantially coplanar with the upper surface of the encapsulating material 15.

Referring to fig. 3F, a second carrier 22 is disposed on the upper surface of the encapsulant 15.

After the flip, the first carrier 21 is removed.

Referring to fig. 3G, an electrical connection 16 is provided on the second surface 11b of the wiring layer 11.

Here, the electrical Connection members 16 may be disposed on the second surface 11b by a flip Chip bonding (C4) method.

After the inversion, the substrate 18 is disposed under the second surface 11b, and bonded so that the substrate 18 is electrically connected to the second surface 11b through the electrical connection member 16.

For example, Flip Chip Bonding (FCB), Thermal Compression Bonding (TCB), or the like may be used for the electrical connection process.

Referring to fig. 3H, second carrier 22 is removed.

Referring to fig. 3I, after flipping, a solder bump is placed on top of the substrate 18.

Here, the solder bumps may be placed on top of the substrate 18 using the C4 method.

The method for manufacturing the semiconductor structure provided by the present disclosure can achieve similar technical effects to the aforementioned semiconductor structure, and is not described herein again.

While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims

1. A semiconductor packaging device, comprising:

a wiring layer having a first surface, the wiring layer including conductive traces at least partially exposed on the first surface;

A protective layer is disposed on the first surface and contacts the conductive traces, and the thermal expansion coefficient of the protective layer is smaller than the thermal expansion coefficient of the conductive traces.

2. The apparatus of claim 1, wherein the apparatus further comprises:

A first chip and a second chip are disposed on the first surface, and the first chip is electrically connected to the second chip through the conductive traces.

3. The apparatus of claim 2, wherein,

The active surface or the non-active surface of the first chip is disposed toward the first surface;

The active surface or the non-active surface of the second chip is disposed facing the first surface.

4. The device of claim 1, wherein the circuit layer further comprises a dielectric layer, and the conductive traces are disposed on the dielectric layer;

5. The device of claim 1, wherein the first surface is provided with a groove, the conductive traces are disposed at least partially at the bottom of the groove and are exposed at the first surface through the groove ;

The protective layer is at least partially disposed in the groove.

6. The device of claim 1, wherein the protective layer encapsulates the conductive traces.

7. The device of claim 1, wherein the protective layer comprises an underfill.

8. The apparatus of claim 1, wherein the apparatus further comprises:

The packaging material is arranged on the first surface and covers the first chip and the second chip.

9. The apparatus of claim 8, wherein the inactive surface of the first chip and/or the inactive surface of the second chip is substantially coplanar with the upper surface of the package material.

10. The apparatus of claim 1, wherein the wiring layer has a second surface opposite the first surface; the apparatus further comprising:

The electrical connector is arranged on the second surface.