CN113725274A - Pixel circuit, display panel and display device - Google Patents

Abstract

Embodiments of the present disclosure provide a pixel circuit, a display panel, and a display device, which relate to the field of display technology, and are used to improve the problem of bright spots of a display screen on the display panel while taking into account the problem of improving the afterimage problem of the display screen on the display panel. The pixel circuit includes a light emitting device, a driving transistor, a first transistor and a second transistor. The second electrode of the driving transistor is coupled to the light emitting device, and the driving transistor is configured to control the magnitude of the current flowing through the first electrode and the second electrode in response to the voltage of the control electrode. The first electrode of the first transistor is coupled to the control electrode of the driving transistor, and the second electrode is configured to write the first initialization signal. The first electrode of the second transistor is coupled to the light emitting device, and the second electrode is configured to write the second initialization signal. The first transistor includes at least two sub-transistors connected in series, and the width-to-length ratio of the channel of at least one of the sub-transistors is smaller than the width-to-length ratio of the channel of the second transistor.

Description

Pixel circuit, display panel and display device

technical field

The present invention relates to the field of display technology, and in particular, to a pixel circuit, a display panel and a display device.

Background technique

At present, the organic light-emitting diode (Organic Light-Emitting Diode Display, OLED for short) display device has the advantages of self-luminescence, fast response, low power consumption, etc., and thus has been more and more widely used.

In an OLED display device, the OLED can be driven to emit light by a pixel driving circuit. The pixel driving circuit may include a plurality of thin film transistors (Thin Film Transistor, TFT for short). Due to the properties of the thin film transistor itself, when the thin film transistor is in the off state, there will be leakage current in the thin film transistor, which will cause bright spots and afterimages to appear on the display screen of the display device, and the appearance of the display screen will deteriorate.

SUMMARY OF THE INVENTION

Embodiments of the present invention provide a pixel circuit, a display panel, and a display device, which are used to improve the problem of bright spots in a display screen of the display panel while taking into account the problem of improving the afterimage problem of the display screen of the display panel.

To achieve the above object, the embodiments of the present invention adopt the following technical solutions:

In a first aspect, a pixel circuit is provided, including a light emitting device, a driving transistor, a first transistor and a second transistor. The driving transistor includes a first electrode, a second electrode and a control electrode. In the driving transistor, the second electrode is coupled to the light emitting device, and the driving transistor is configured to control the voltage flowing through the first electrode and the second electrode in response to the control electrode. pole current magnitude. The first transistor includes a first electrode, a second electrode and a control electrode. In the first transistor, the first electrode is coupled to the control electrode of the driving transistor, and the second electrode is configured to write a first initialization signal. The second transistor includes a first electrode, a second electrode and a control electrode. In the second transistor, the first electrode is coupled to the light emitting device, and the second electrode is configured to write a second initialization signal. Wherein, the first transistor includes at least two sub-transistors connected in series, the control electrodes of the at least two gold kick gates are coupled to each other to form the control electrode of the first transistor, and the width-length ratio of the channel of at least one sub-transistor is smaller than that of the second transistor. The width to length ratio of the road.

In some embodiments, in the at least two sub-transistors, the channel width to length ratio of each sub-transistor is the same.

In some embodiments, the width of the channel of each sub-transistor is equal to the width of the channel of the second transistor.

In some embodiments, the length of the channel of the at least one sub-transistor is 0.8˜1.2 μm greater than the length of the channel of the second transistor.

In some embodiments, the channel of at least one sub-transistor has a width of 2.0-3.0 μm and a length of 2.7-4.0 μm.

In some embodiments, the channel of at least one sub-transistor has a width of 2.3±0.2 μm and a length of 3.5±0.2 μm.

In some embodiments, the width of the channel of the drive transistor is greater than the width of the channel of the second transistor.

In some embodiments, the width of the channel of the drive transistor is 3.0±0.2 μm.

In some embodiments, the pixel circuit further includes at least one of a capacitor, a fourth transistor, a third transistor, a fifth transistor, and a sixth transistor; wherein the capacitor includes a first electrode plate and a second electrode plate, and the first electrode plate Coupled with the control electrode of the driving transistor, the second electrode plate is configured to write a power supply voltage signal; the third transistor includes a first electrode, a second electrode and a control electrode, in the third transistor, the second electrode is connected to the driving transistor. The first electrode is coupled, and the first electrode is configured to write a data signal; the fourth transistor includes a first electrode, a second electrode and a control electrode, and in the fourth transistor, the first electrode is coupled to the second electrode of the driving transistor , the second pole is coupled to the control pole of the driving transistor; the fifth transistor includes a first pole, a second pole and a control pole, in the fifth transistor, the second pole is coupled to the first pole of the driving transistor, and the first pole is configured to write the power supply voltage signal; the sixth transistor includes a first pole, a second pole and a control pole, in the sixth transistor, the first pole is coupled to the second pole of the driving transistor, and the second pole is connected to the light-emitting device coupling.

In a second aspect, a display panel is provided, including a plurality of pixel circuits, and each pixel circuit is the pixel circuit provided in any of the foregoing embodiments.

In some embodiments, the plurality of pixel circuits includes a first pixel circuit in row N-1 and a second pixel circuit in row N. The display panel also includes reset control signal lines. The first pixel circuit and the second pixel circuit are the pixel circuits provided in any of the foregoing embodiments. The control electrode of the first transistor in the second pixel circuit and the control electrode of the second transistor in the first pixel circuit are both coupled to the reset control signal line. Wherein, N is an integer greater than 1.

In some embodiments, in the first transistor of the second pixel circuit, the control electrodes of the respective sub-transistors are coupled to each other and form an integrated pattern, and the integrated pattern is coupled to the reset control signal line. The reset control signal line, the integrated pattern, and the control electrode of the second transistor in the first pixel circuit are located in the same pattern layer, and the width of the integrated pattern is greater than the width of the control electrode of the second transistor and greater than the width of the reset control signal line .

In some embodiments, the pixel circuit includes a fourth transistor, a third transistor, a fifth transistor, and a sixth transistor. The display panel further includes a first light-emitting control signal line and a second light-emitting control signal line, the control electrode of the fifth transistor and the control electrode of the sixth transistor in the first pixel circuit are coupled to the first light-emitting control signal line, and the second pixel circuit The control electrode of the fifth transistor and the control electrode of the sixth transistor are coupled to the second light-emitting control signal line. The display panel also includes a first scan signal line and a second scan signal line, the control electrode of the fourth transistor and the control electrode of the third transistor in the first pixel circuit are coupled to the first scan signal line, and the second pixel circuit in the second pixel circuit. The control electrodes of the four transistors and the control electrodes of the third transistor are coupled to the second scan signal line. Wherein, the first light-emitting control signal line, the second light-emitting control signal line, the first scanning signal line, the second scanning signal line and the integrated pattern are located in the same pattern layer.

In some embodiments, the pixel circuit includes a capacitor, and the second plate of the capacitor is configured to write the power supply voltage signal. The first electrode plate and the integrated pattern are located in the same pattern layer.

In a third aspect, a display device is provided, including the display panel provided in any of the foregoing embodiments.

In a transistor, the smaller the width-to-length ratio of the channel, the worse the turn-on performance of the transistor, and the smaller the leakage current of the transistor in the off-state can be. In the pixel circuit provided by the embodiments of the present disclosure, in the first transistor, the width-to-length ratio of the channel of at least one sub-transistor is smaller than the width-to-length ratio of the channel of the second transistor. Therefore, compared with the second transistor, The overall conduction performance of the first transistor may be poor, and during the process of emitting light of the light-emitting device, the leakage current of the first transistor in the off state may be small, which can improve the problem of bright spots in the display screen. In addition, since the aspect ratio of the channel of the at least one sub-transistor is smaller than the aspect ratio of the channel of the second transistor, the aspect ratio of the channel of the second transistor may be larger. Therefore, the conduction performance of the second transistor can be better, so that the second transistor can better initialize the light-emitting device, and can improve the problem of afterimages in the display screen of the display panel. That is, the pixel circuit provided by the embodiments of the present disclosure can improve the problem of bright spots in the display image of the display panel on the premise of improving the afterimage problem of the display image of the display panel.

It can be understood that the display panel provided in the second aspect and the display device provided in the third aspect include the above-mentioned pixel circuit, and the beneficial effects that can be achieved can refer to the beneficial effects of the pixel circuit above, which will not be repeated here.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some of the present invention. In the embodiments, for those of ordinary skill in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a top view of a display panel provided by some embodiments of the present disclosure;

FIG. 2 is a structural diagram of a display panel provided by some embodiments of the present disclosure;

FIG. 3 is an equivalent circuit diagram of a pixel circuit provided by some embodiments of the present disclosure;

4 is a structural diagram of a light emitting device in a pixel circuit provided by some embodiments of the present disclosure;

FIG. 5 is an equivalent circuit diagram of a pixel circuit provided by some embodiments of the present disclosure;

6 is a top view of a display panel provided by some embodiments of the present disclosure;

7 is a top view of a pattern layer in a display panel according to some embodiments of the present disclosure;

8 is a top view of a pattern layer in a display panel according to some embodiments of the present disclosure;

9 is a top view of a plurality of pattern layers in a display panel according to some embodiments of the present disclosure;

Fig. 10 is a partial enlarged view of region B in Fig. 9;

FIG. 11 is a structural diagram of a display panel provided by some embodiments of the present disclosure;

12 is a top view of a display panel according to some embodiments of the present disclosure;

FIG. 13 is a top view of a plurality of pattern layers of a display panel according to some embodiments of the present disclosure.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", The orientation or positional relationship indicated by "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying The device or element referred to must have a particular orientation, be constructed and operate in a particular orientation, and therefore should not be construed as limiting the invention.

Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms such as the third person singular "comprises" and the present participle "comprising" are used It is interpreted as the meaning of openness and inclusion, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" example)" or "some examples" and the like are intended to indicate that a particular feature, structure, material or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

Hereinafter, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

In describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other. As another example, the term "coupled" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact. However, the terms "coupled" or "communicatively coupled" may also mean that two or more components are not in direct contact with each other, but yet still co-operate or interact with each other. The embodiments disclosed herein are not necessarily limited by the content herein.

"At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: A only, B only, C only, A and B , A and C, B and C, and A, B, and C.

"A and/or B" includes the following three combinations: A only, B only, and a combination of A and B.

"Plurality" means at least two.

The use of "adapted to" or "configured to" herein means open and inclusive language that does not preclude devices adapted or configured to perform additional tasks or steps.

Additionally, the use of "based on" is meant to be open and inclusive, as a process, step, calculation or other action "based on" one or more of the stated conditions or values may in practice be based on additional conditions or beyond the stated values.

As used herein, "about", "approximately" or "approximately" includes the stated value as well as the average value within an acceptable range of deviation from the specified value, as described by one of ordinary skill in the art Determined taking into account the measurement in question and the errors associated with the measurement of a particular quantity (ie, limitations of the measurement system).

Exemplary embodiments are described herein with reference to cross-sectional and/or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the drawings due to, for example, manufacturing techniques and/or tolerances, are contemplated. Thus, example embodiments should not be construed as limited to the shapes of the regions shown herein, but to include deviations in shapes due, for example, to manufacturing. For example, an etched area shown as a rectangle will typically have curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of example embodiments.

The transistors herein may be N-type transistors or P-type transistors, which are not particularly limited in the embodiments of the present disclosure. Hereinafter, it will be taken as an example that the transistor is a P-type transistor. It can be understood that even if the transistor is an N-type transistor, the solution of the present disclosure can also be implemented and corresponding technical effects can be obtained.

Some embodiments of the present disclosure provide a display device. The display device is a product having the function of displaying images (including: still images or moving images, wherein the moving images may be videos). For example, the display device may be: a monitor, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a Personal Digital Assistant (PDA), a digital camera, a camcorder, a viewfinder, Any of navigators, vehicles, large-area walls, home appliances, information inquiry equipment (such as business inquiry equipment in e-government, banks, hospitals, electric power and other departments), monitors, etc.

In some embodiments, the display device may include a display panel, and may further include a driving circuit coupled to the display panel. The driving circuit is configured to provide electrical signals to the display panel. Exemplarily, the driving circuit may include: a data driving circuit (for example, it may be a source driving circuit, Source Driver IC), configured to provide data signals (also referred to as data driving signals) to the display panel; a scan driving circuit, configured To provide the scan signal to the display panel. The driving circuit may further include a timing control circuit (also referred to as a timing controller, Timer Control Register, or TCON for short), the timing control circuit may be coupled to the data driving circuit and the scan driving circuit, and configured to provide control signals to the scan driving circuit And a control signal and image data are supplied to the data driving circuit. In some possible implementations, the scan driving circuit may be integrated on the display panel. At this time, it can also be said that the display panel includes a scan drive circuit, and the scan drive circuit can be called GOA (Gate Driver on Array, a scan drive circuit disposed on an array substrate).

Some embodiments of the present disclosure also provide a display panel, which may be included in the display device provided by any of the above embodiments. The display panel may be an OLED (Organic Light Emitting Diode, organic light-emitting diode) display panel, a QLED (Quantum Dot Light Emitting Diodes, quantum dot light-emitting diode) display panel, a micro-LED (including: miniLED or microLED, LED is a light-emitting diode) display panel one of the.

FIG. 1 shows the structure of a display panel provided by some embodiments of the present disclosure. Referring to FIG. 1 , the display panel 1 may have a display area AA and a peripheral area SA located on at least one side (eg, one side; another example, all around, including upper and lower sides and left and right sides) of the display area AA. The display panel 1 includes a plurality of pixel circuits 10 arranged in the display area AA. The pixel circuit 10 may include a light emitting device 100 and a pixel driving circuit 200 that controls the light emitting device 100 to emit light. The pixel driving circuit 200 may be configured to drive the light-emitting device 100 to emit light in response to the received data signal and scan signal, and the luminance of the light-emitting device 100 may be positively correlated with the voltage of the data signal. In the display area AA, the pixel driving circuits 200 may be distributed in an array.

In some embodiments, the display panel 1 may further include various signal lines. Exemplarily, various signal lines may be located in the display area and coupled with pixel circuits in the display area. Specifically, referring to FIG. 2 , FIG. 2 is a partial enlarged view of the display panel in FIG. 1 . A pixel circuit 10 (eg, each pixel circuit 10 ) may be coupled to a variety of signal lines, each of which may be configured to write an electrical signal to the pixel circuit 10 .

In some embodiments, the various signal lines may include at least one of a data line D, a first power line EL1, a second power line EL2, a reset control signal line R, a light emission control signal line E, and a scan signal line G. The various signal lines may also include an initialization signal line Vi (not shown in FIG. 2 ). The data line D may be configured to write the data signal Da to the pixel circuit 10; the first power line EL1 may be configured to write the first power supply voltage signal ELVDD to the pixel circuit 10; the second power line EL2 may be configured to The second power supply voltage signal ELVSS is written to the pixel circuit 10; the reset control signal line R may be configured to write the reset control signal Sc1 to the pixel circuit 10; the light emission control signal line E may be configured to write the light emission control signal to the pixel circuit 10 The signal Sc2; the scan signal line G may be configured to write the scan signal Sc3 to the pixel circuit 10; the initialization signal line Vi may be configured to write the initialization signal Vinit (not shown in the figure) to the pixel circuit 10. The data signal Da, the first power supply voltage signal ELVDD, the second power supply voltage signal ELVSS, the reset control signal Sc1, the light-emitting control signal Sc2, the scanning signal Sc3, and the initialization signal Vinit may be voltage signals, or may be other types of power signal, which is not limited by the embodiments of the present disclosure. Wherein, the voltage of the first power supply voltage signal ELVDD may be greater than the voltage of the second power supply voltage signal ELVSS. In addition, it should be noted that the subscripts corresponding to the reference numerals of the signal lines in FIG. 2 are used to indicate the serial numbers of the signal lines. For example, D _M represents the M-th data line.

Some embodiments of the present disclosure also provide a pixel circuit, and the pixel circuit may be the pixel circuit in the display panel of any of the above-mentioned embodiments.

FIG. 3 is an equivalent circuit diagram of a pixel circuit. Referring to FIG. 3 , based on the above description, the pixel circuit 10 may include a light emitting device 100 and a pixel driving circuit coupled with the light emitting device 100 . The light emitting device 100 may be, for example, an organic light emitting diode OLED, a quantum dot light emitting diode QLED, or a light emitting diode LED, but is not limited thereto. The embodiment of the present disclosure does not limit the type of the light emitting device 100 , that is, the light emitting device 100 may be any other light emitting device (eg, light emitting device that emits light by discharge), as long as they can emit light in response to an electrical signal, so that the display panel can display screen. In some embodiments, the light emitting device 100 is an OLED.

In some embodiments, referring to FIG. 4 , the light emitting device 100 may be an OLED, and the light emitting device 100 may include a first electrode 110 , a second electrode 130 , and a light emitting functional layer 120 between the first electrode 110 and the second electrode 130 .

Exemplarily, the first electrode 110 may be coupled with a pixel driving circuit, and the pixel driving circuit may provide a voltage-variable electrical signal to the first electrode 110; the second electrode 130 may be coupled with a power line, and the power line may The second electrode 130 provides a fixed voltage. Exemplarily, the first electrode 110 is an anode, and correspondingly, the second electrode 130 is a cathode; the first electrode 110 is configured to communicate with the first power supply line (configured to transmit the first power supply signal in FIG. 3 through the pixel driving circuit) ELVDD) is coupled, and the second electrode 130 is coupled with a second power supply line (configured to transmit the second power supply signal ELVSS in FIG. 3 ). In another example, the first electrode 110 is a cathode, and correspondingly, the second electrode 130 is an anode; the first electrode 110 is coupled to the second power line through the pixel driving circuit, and the second electrode 130 is coupled to the first power line.

The light-emitting functional layer 120 may have a single-layer structure or a multi-layer structure. Exemplarily, the light-emitting functional layer 120 may include a light-emitting layer, and the light-emitting functional layer may further include: at least one of a hole injection layer, a hole transport layer, and an electron blocking layer located between the anode and the light-emitting layer, and may also include : at least one of a hole blocking layer, an electron transport layer, and an electron injection layer located between the light-emitting layer and the cathode. The light emitting layer in one light emitting device 100 may be a red light emitting layer, a green light emitting layer, a blue light emitting layer or a white light emitting layer.

It should be noted that the structure of other types of light-emitting devices (eg, QLED or LED) can also refer to the structure of the OLED described above, and the specific structures of other types of light-emitting devices will not be repeated.

Continuing to refer to FIG. 3 , the pixel driving circuit may include a plurality of transistors T. As shown in FIG. Specifically, the pixel driving circuit may include a driving transistor Td, a first transistor T1, and a second transistor T2.

The driving transistor Td includes a first electrode Td1, a second electrode Td2 and a control electrode Td3. The driving transistor Td is configured to control the magnitude of the current flowing through the first electrode Td1 and the second electrode Td2 in response to the voltage of the control electrode Td3. Exemplarily, in the driving transistor Td, the control electrode Td3 may be configured to write an electrical signal, and in response to the voltage of the electrical signal, the driving transistor Td may control the magnitude of the current flowing through the first electrode Td1 and the second electrode Td2, The magnitude of the voltage of the electrical signal is different, and the magnitude of the current flowing through the first pole Td1 and the second pole Td2 is different. In some possible implementations, the electrical signal written to the control electrode Td3 may be a data signal Da or a data-related signal Da' (ie, an electrical signal related to the data signal Da), so that the voltage on the control electrode Td3 may be the same as that of the control electrode Td3. The voltage Vdata of the data signal Da written in the pixel driving circuit is related, for example, the voltage magnitude of the electrical signal is positively correlated with the magnitude of the voltage Vdata of the data signal Da. Based on this, the magnitude of the current flowing through the first pole Td1 and the second pole Td2 can be controlled by providing different data signals Da to the pixel driving circuit.

The second pole Td2 is coupled to the light emitting device 100 . Exemplarily, the second electrode Td2 may be coupled with the first electrode of the light emitting device 100 such that the driving transistor Td and the light emitting device 100 are connected in series on a line between the first power line EL1 and the second power line EL2. Since the driving transistor Td and the light-emitting device 100 are connected in series, the current flowing through the first electrode Td1 and the second electrode Td2 can flow into the light-emitting device 100, and the light-emitting device 100 can be driven to emit light by the current. Specifically, light-emitting can be controlled by the current. The luminous intensity of the device 100 . That is, in the pixel circuit 10, the magnitude of the current flowing through the first electrode Td1 and the second electrode Td2 of the driving transistor is different, and the luminance of the light emitting device 100 can be changed accordingly.

In some embodiments, the first electrode Td1 of the driving transistor may be coupled to the first power supply line EL1, so that the first electrode Td1 of the driving transistor may write the first power supply voltage signal ELVDD. In some possible implementations, the second electrode Td2 of the driving transistor is coupled to the first electrode of the light emitting device 100, and the second electrode of the light emitting device 100 is coupled to the second power line EL2, so that the first electrode of the driving transistor Td1 may be coupled to the first power line EL1 , and the second electrode Td2 of the driving transistor may be coupled to the second power line EL2 through the light emitting device 100 . There may be a voltage difference between the first power supply voltage signal ELVDD on the first power supply line EL1 and the second power supply voltage signal ELVSS on the second power supply line EL2, so that the first electrode Td1 and the second electrode flowing through the driving transistor may be generated The current of Td2, and the current flowing through the light emitting device 100.

The first transistor T1 includes a first electrode T11, a second electrode T12 and a control electrode T13. In the first transistor T1, the first electrode T11 is coupled to the control electrode Td3 of the driving transistor, and the second electrode T12 is configured to write the first initialization signal Vinit1. In this way, when the first transistor T1 is in an on state, the first initialization signal Vinit1 can be written to the control electrode Td3 of the driving transistor through the first transistor T1. By writing the first initialization signal Vinit1 to the control electrode Td3 of the driving transistor, the driving transistor Td can be initialized, so that the driving transistor Td can be switched from the initialization state to other operating states in subsequent working stages. For example, in the subsequent working stage, the voltage of the control electrode Td3 of the driving transistor can be switched from the voltage corresponding to the initialization signal Vinit1 to other working voltages. In this way, the afterimage phenomenon of the display panel can be improved, and the display stability can be improved.

In some possible implementations, the initialization signal line includes a first initialization signal line, and the first initialization signal line is configured to write the first initialization signal Vinit1 to the pixel circuit 10 . The second electrode T12 of the first transistor may be coupled to the first initialization signal line, so that the first initialization signal Vinit output from the first initialization signal line may be written into the second electrode T12 of the first transistor.

In some embodiments, the control electrode T13 of the first transistor may be configured to control the turn-on and turn-off of the first transistor T1, ie, the first transistor T1 may be turned on and off in response to the voltage of the control electrode T13. Exemplarily, the control electrode T13 of the first transistor may be coupled to the reset control signal line, and the reset control signal Sc1 output by the reset control signal line may be written into the control electrode T13. In response to the voltage of the reset control signal Sc1, the first transistor T1 may be turned on and off.

The first transistor T1 includes at least two (eg, two; another example, more than three) sub-transistors connected in series, and the at least two sub-transistors include a sub-transistor T1 a and a sub-transistor T1 b. Similarly, the sub-transistor includes a first electrode, a second electrode and a control electrode. For example, the sub-transistor T1a includes a first electrode T1a1, a second electrode T1a2 and a control electrode T1a3; the sub-transistor T1b includes a first electrode T1b1, a second electrode T1b2 and a control electrode T1b3.

Control electrodes of at least two (eg, two; or more than three) sub-transistors connected in series are coupled to each other, and serve as the control electrodes T13 of the first transistor. Exemplarily, the first transistor T1 includes two sub-transistors connected in series, that is, a sub-transistor T1a and a sub-transistor T1b. The control electrode T1a3 of the sub-transistor T1a and the control electrode T1b3 of the sub-transistor T1b are coupled to each other and serve as the control electrode T13 of the first transistor. In response to the voltage of the gate electrode T13, the sub-transistor T1a and the sub-transistor T1b may be turned on and turned off at the same time.

The second transistor T2 may include a first electrode T21, a second electrode T22 and a control electrode T23. In the second transistor T2 , the first electrode T21 is coupled with the light emitting device 100 , for example, the first electrode T21 may be coupled with the first electrode of the light emitting device 100 . The second pole T22 is configured to write the second initialization signal Vinit2. In this way, when the second transistor T2 is in an on state, the second initialization signal Vinit2 can be written to the light emitting device 100 through the second transistor T2. By writing the second initialization signal Vinit2 to the light emitting device 100, the light emitting device 100 can be initialized, so that in the subsequent working stage, the light emitting device 100 can be switched from the initialization state to other working states. For example, in a subsequent working stage, the voltage on the first electrode of the light emitting device 100 may be switched from the voltage corresponding to the second initialization signal Vinit2 to other working voltages. In some possible implementations, the second initialization signal Vinit2 may be a low-voltage electrical signal, and when a low-voltage electrical signal is written to the first electrode of the light-emitting device 100, the driving current in the light-emitting device 100 may be small or no driving current , so that the light-emitting device 100 emits less light or does not emit light, that is, the pixel circuit 10 including the light-emitting device 100 can display black color blocks. In the subsequent working stage, the pixel circuit 10 switches from the state of displaying black color patches to the state of displaying other color patches. In this way, the afterimage problem of the display screen of the display panel can be improved, and the display stability can be improved.

In some possible implementations, the initialization signal line further includes a second initialization signal line, and the second initialization signal line is configured to write the second initialization signal Vinit2 to the pixel circuit 10 . The second electrode T22 of the second transistor may be coupled to the second initialization signal line, so that the second initialization signal Vinit2 output from the second initialization signal line may be written into the second electrode T22 of the second transistor.

In some embodiments, the control electrode T23 of the second transistor may be configured to control the turn-on and turn-off of the second transistor T2, ie, the second transistor T2 may be turned on and off in response to the voltage of the control electrode T23. Exemplarily, the control electrode T23 of the second transistor may be coupled to the reset control signal line, and the reset control signal Sc1 output by the reset control signal line may be written into the control electrode T23. In response to the voltage of the reset control signal Sc1, the second transistor T2 may be turned on and off.

Based on the above structure of the pixel circuit 10 , for example, the workflow of the pixel circuit 10 may include: a stage of initializing the driving transistor Td, a stage of initializing the light-emitting device 100 , a data writing stage, and a light-emitting stage.

In the stage of initializing the drive transistor Td, the first transistor T1 is turned on. Through the first transistor T1, the first initialization signal Vinit1 can be written into the control electrode Td3 of the driving transistor Td, thereby initializing the driving transistor Td.

In the stage of initializing the light-emitting device 100, the second transistor T2 is turned on, and through the second transistor T2, the second initialization signal Vinit2 can be written into the light-emitting device 100, for example, the second initialization signal Vinit2 can be written into the light-emitting device 100 an electrode, thereby initializing the light emitting device 100 .

In the data writing stage, the first transistor T1 is in an off state, and the control electrode Td3 of the driving transistor writes an electrical signal, for example, the electrical signal may be a data signal Da or a data associated signal Da'.

In the light-emitting phase, the first transistor T1 is in an off state, and the second transistor T2 is in an off state. In the driving transistor Td, in response to the voltage of the gate electrode Td3 of the driving transistor, the driving transistor Td is turned on to generate a current for driving the light emitting device 100 to emit light, and the current is output to the light emitting device 100 so that the light emitting device 100 emits light.

As described above, the driving transistor Td can control the magnitude of the current flowing through the first electrode Td1 and the second electrode Td2 in response to the voltage of the control electrode Td3, thereby controlling the light-emitting brightness of the light-emitting device 100. The voltage on the control electrode Td3 is different, and the light is emitted. The luminous intensity of the device 100 may vary. In some related technologies, the leakage current of the first transistor in the off state is relatively large, that is, when the first transistor is in the off state, the current flowing between the first electrode and the second electrode of the first transistor is relatively large. Since the first electrode of the first transistor is coupled to the control electrode Td3 of the driving transistor, in the light-emitting stage, the voltage on the control electrode Td3 of the driving transistor can be reduced due to the leakage current. Taking the driving transistor Td as a P-type transistor as an example, since the voltage of the control electrode Td3 of the driving transistor decreases, the current for driving the light-emitting device 100 to emit light in the pixel circuit of the related art is relatively large, so that the brightness of the light-emitting device 100 is too large. As a result, the color blocks displayed by the pixel circuit are too bright, so that there are bright spots in the display screen of the display panel.

In order to solve the above problem, in the pixel circuit provided by some embodiments of the present disclosure, in the first transistor T1, the width to length ratio of the channel of at least one sub-transistor is smaller than the width to length ratio of the channel of the second transistor T2. For a transistor, the smaller the aspect ratio of the channel, the worse the conduction performance of the transistor, for example, the greater the threshold voltage Vth of the transistor can be. Taking the transistor as a P-type transistor as an example, a lower voltage needs to be written on the control electrode to make the transistor turn on. In addition, the smaller the width-to-length ratio of the channel, the smaller the leakage current of the transistor in the off state can be because the on-performance of the transistor is deteriorated. Based on this, since the width-to-length ratio of the channel of at least one sub-transistor in the first transistor is smaller than the width-to-length ratio of the channel of the second transistor, the overall turn-on performance of the first transistor can be better than that of the second transistor. Poor, in the process of emitting light of the light-emitting device, the leakage current of the first transistor in the off state can be small, which can improve the above-mentioned bright spot problem.

In addition, since the aspect ratio of the channel of the at least one sub-transistor is smaller than the aspect ratio of the channel of the second transistor, the aspect ratio of the channel of the second transistor may be larger. As described above, the second transistor can be configured to initialize the light emitting device, which can improve the afterimage phenomenon of the display panel. Since the width to length ratio of the channel of the second transistor can be larger, the conduction performance of the second transistor can be better, and the initialization of the light-emitting device by the second transistor will not be affected. That is, the pixel circuit provided by the embodiment of the present disclosure can improve the problem of bright spots in the display image of the display panel on the premise of taking into account the improvement of the afterimage problem of the display image of the display panel.

In some embodiments, in the at least two sub-transistors of the first transistor T1, the width-to-length ratios of the channels of the respective sub-transistors are the same. That is, the width-to-length ratios of the channels of the respective sub-transistors are the same, and all are smaller than the width-to-length ratio of the second transistor T2. In this way, the width to length ratio of the entire channel of the first transistor T1 can be further reduced, thereby further reducing the leakage current of the first transistor T1 in the off state, so that the bright spot problem can be better improved.

In some embodiments, the pixel circuit may further include at least one of a capacitor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. Exemplarily, FIG. 5 is an equivalent circuit diagram of a pixel circuit, showing the connection relationship between the above-mentioned various elements. The above-mentioned elements will be described in detail below with reference to FIG. 5 , respectively.

The capacitor C includes a first plate S1 and a second plate S2, the first plate S1 is coupled to the control electrode Td3 of the driving transistor, and the second plate S2 is configured to write the first power supply voltage signal ELVDD. Exemplarily, the second plate S2 may be coupled to the first power line EL1, and the first power supply voltage signal ELVDD output by the first power line EL1 may be written into the second plate S2 of the capacitor. The capacitor C may be configured to store an electrical signal, which may be written to the control electrode Td3 of the driving transistor during the light-emitting stage of the light-emitting device 100, so that the driving transistor may generate a current for driving the light-emitting device 100 to emit light in response to the electrical signal.

The third transistor T3 includes a first electrode T31, a second electrode T32 and a control electrode T33. In the third transistor T3, the second electrode T32 is coupled to the first electrode Td1 of the driving transistor, and the first electrode T31 is configured to write the data signal Da. Exemplarily, the first pole T31 may be coupled to the data line D, and the data signal Da output by the data line D may be written into the first pole T31. The control electrode T33 may be configured to control the turn-on and turn-off of the third transistor T3, that is, the third transistor T3 may be turned on and turned off in response to the voltage of the control electrode T33. Exemplarily, the control electrode T33 of the third transistor may be coupled to the scan signal line, the scan signal Sc3 output by the scan signal line may be written into the control electrode T33 of the third transistor, and in response to the scan signal Sc3, the third transistor T3 may on and off.

The fourth transistor T4 includes a first electrode T41, a second electrode T42 and a control electrode T43. In the fourth transistor T4, the first electrode T41 is coupled to the second electrode Td2 of the driving transistor, and the second electrode T42 is coupled to the control electrode Td3 of the driving transistor. Due to the above structures of the third transistor T3 and the fourth transistor T4, the second electrode T32 of the third transistor T3 can be coupled to the control electrode Td3 of the driving transistor through the driving transistor Td and the fourth transistor T4. The control electrode T43 of the fourth transistor may be configured to control turn-on and turn-off of the fourth transistor T4, ie, the fourth transistor T4 may be turned on and off in response to the voltage of the control electrode T43. Exemplarily, the control electrode T43 of the fourth transistor may be coupled to the scan signal line, the scan signal Sc3 output by the scan signal line may be written into the control electrode T43 of the fourth transistor, and in response to the scan signal Sc3, the fourth transistor may conduct. On and off. In some embodiments, a scan signal line may be coupled to the control electrode T33 of the third transistor, and may also be coupled to the control electrode T43 of the fourth transistor. Therefore, the third transistor T3 and the fourth transistor T4 may be simultaneously conducted. through or at the same time. In other embodiments, the third transistor T3 may be coupled to a scan signal line, and the fourth transistor T4 may be coupled to another scan signal line. In this way, through the two scan signal lines, the third transistor T3 and the The fourth transistors T4 are respectively controlled.

The fifth transistor T5 includes a first electrode T51, a second electrode T52 and a control electrode T53. In the fifth transistor T5, the second electrode T52 is coupled to the first electrode Td1 of the driving transistor, and the first electrode T51 is configured to write the first power supply voltage signal ELVDD. Exemplarily, the first pole T51 may be coupled to the first power supply line EL1, and the first power supply signal ELVDD output by the first power supply line EL1 may be written into the first pole T51 of the fifth transistor. Therefore, when the fifth transistor T5 is turned on, the first power signal ELVDD may be written to the first electrode Td1 of the driving transistor through the fifth transistor T5. The control electrode T53 of the fifth transistor may be configured to control turn-on and turn-off of the fifth transistor T5, ie, the fifth transistor T5 may be turned on and off in response to the voltage of the control electrode T53. Exemplarily, the control electrode T53 of the fifth transistor may be coupled to the light-emitting control signal line, and the light-emitting control signal Sc2 output by the light-emitting control signal line may be written into the control electrode T53 of the fifth transistor. Five transistors can be turned on and off.

The sixth transistor T6 includes a first electrode T61, a second electrode T62 and a control electrode T63. In the sixth transistor T6 , the first electrode T61 is coupled to the second electrode Td2 of the driving transistor, and the second electrode T62 is coupled to the light emitting device 100 , eg, to the first electrode of the light emitting device 100 . In this way, when the sixth transistor T6 is turned on, the current output from the driving transistor Td can be input to the light emitting device 100, thereby driving the light emitting device 100 to emit light. The control electrode T63 of the sixth transistor may be configured to control turn-on and turn-off of the sixth transistor T6, ie, the sixth transistor T6 may be turned on and off in response to the voltage of the control electrode T63. Exemplarily, the control electrode T63 of the sixth transistor may be coupled to the light-emitting control signal line, and the light-emitting control signal Sc2 output by the light-emitting control signal line may be written to the control electrode of the sixth transistor. In response to the light-emitting control signal Sc2, the sixth The transistor T6 can be turned on and off. In some embodiments, a light-emitting control signal line can be coupled to the control electrode T51 of the fifth transistor, and can also be coupled to the control electrode T61 of the sixth transistor. Therefore, the fifth transistor T5 and the sixth transistor T6 can be simultaneously turned on or off at the same time. In other embodiments, the control electrode T53 of the fifth transistor may be coupled to a light-emitting control signal line, and the control electrode T63 of the sixth transistor may be coupled to another light-emitting control signal line. In this way, through the two light-emitting control signals line, the fifth transistor T5 and the sixth transistor T6 can be controlled respectively.

Exemplarily, based on the above structure of the pixel circuit 10, the workflow of the pixel circuit 10 may include: a stage of initializing the driving transistor Td, a stage of initializing the light-emitting device 100, a data writing stage, and a light-emitting stage.

Specifically, in the stage of initializing the driving transistor Td, the first transistor T1 can be turned on, and the first initialization signal Vinit1 is written into the control electrode Td3 of the driving transistor through the first transistor T1 to realize the initialization of the driving transistor Td. Exemplarily, in the stage of initializing the driving transistor Td, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be turned off.

In the stage of initializing the light-emitting device 100, the second transistor T2 can be turned on, and through the second transistor T2, the second initialization signal Vinit2 is written into the light-emitting device 100, for example, into the first electrode of the light-emitting device 100, so as to realize the initialization of the light-emitting device 100. 100 initialization.

In the data writing stage, the first transistor T1 and the fifth transistor T5 are turned off. The driving transistor Td, the third transistor T3, and the fourth transistor T4 are turned on. The capacitor C may be charged through the third transistor T3, the driving transistor Td, and the fourth transistor T4. Due to the characteristics of the driving transistor Td, when the voltage of the node N1 becomes Vdata+Vth, the driving transistor Td is turned off, the charging process ends, and the voltage of the electrical signal written in the first plate S1 of the capacitor C is Vdata+Vth, wherein, Vdata represents the voltage of the data signal Da, and Vth represents the threshold voltage of the driving transistor Td. The second plate S2 of the capacitor C is coupled with the first power line EL2 to write the first power voltage signal ELVDD.

In some possible implementations, the data writing phase and the phase of initializing the light emitting device 100 may be performed simultaneously. That is, the third transistor T3, the fourth transistor T4, the driving transistor Td, and the second transistor T2 can be turned on, and the fifth transistor T5, the sixth transistor T6, and the first transistor T1 can be turned off, and the capacitor C can be charged. At the same time, the light emitting device 100 is initialized.

In the light-emitting stage, the fifth transistor T5 and the sixth transistor T6 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, and the fourth transistor T4 are turned off. The driving transistor Td is turned on in response to the voltage of the electrical signal on the control electrode Td3, which can be the electrical signal written to the first plate S1 of the capacitor C in the data writing phase, so that the first electrode flowing through the driving transistor can be generated. The current of the first pole Td1 and the second pole Td2 can be output to the light emitting device 100 to drive the light emitting device 100 to emit light.

FIG. 6 is a partial enlarged view of a portion of a display panel including a pixel circuit according to some embodiments of the present disclosure. It should be noted that, in order to make the illustration clearer, FIG. 6 does not show the entire structure of the light emitting device 100 , but only the first electrode of the light emitting device 100 to show the position and connection relationship of the light emitting device 100 . Referring to FIG. 6, the display panel may have a multi-layer structure. Exemplarily, the display panel may include the active layer 300 , the first pattern layer 400 , the second pattern layer 500 , and the third pattern layer 600 disposed on the substrate S.

The active layer 300 and the first pattern layer 400 overlap each other to form transistors, such as the driving transistor Td, the first transistor T1 and the second transistor T2, and the third transistor T3, the fourth transistor T4, and the fifth transistor. T5, one or more of the sixth transistor T6. A transistor formed by overlapping the active layer 300 and the first pattern layer 400 with each other may be referred to as a thin film transistor.

The material of the active layer 300 is, for example, a semiconductor material. A part of the pattern of the active layer 300 may be conductive through a doping process. For example, in a direction perpendicular to the substrate S (eg, parallel to the z-axis direction), the source layer 300 does not face the first pattern layer. Partial conductorization of 400. The conductive portions can serve as source and drain regions of the transistor. The source region may be the first electrode of the transistor, and the drain region may be the second electrode of the transistor; or, the source region may be the second electrode of the transistor, and the drain region may be the first electrode of the transistor. The material of the first pattern layer 400 may be a conductive material, such as metal or alloy.

In order to describe the active layer and the first pattern layer in more detail, FIG. 7 is a top view of the active layer, FIG. 8 is a top view of the first pattern layer, and FIG. 9 is a stacked view of the active layer and the first pattern layer. Top view. Referring to FIGS. 8 and 9 , in a direction perpendicular to the substrate S (eg, parallel to the z-axis direction), the portion of the first conductive layer 400 opposite to the active layer 300 may include gate electrodes of one or more transistors . For example, the first conductive layer 400 may include the control electrode T13 of the first transistor (for example, including the control electrode T1a3 of the sub-transistor T1a and the control electrode T1b3 of the sub-transistor T1b), the control electrode T23 of the second transistor, and the control electrode Td3 of the driving transistor, It may also include one or more of the control electrode T33 of the third transistor, the control electrode T43 of the fourth transistor, the control electrode T53 of the fifth transistor, and the control electrode T63 of the sixth transistor.

Referring to FIGS. 7 and 9 , in a direction perpendicular to the substrate S (eg, parallel to the z-axis direction), a portion of the active layer 300 opposite to the first conductive layer 400 may include channels of one or more transistors . Specifically, in the direction perpendicular to the substrate S (for example, parallel to the z-axis direction), the part of the active layer 300 that is directly opposite to the gate electrode of the transistor can also be said to be in the active layer 300 by the gate electrode of a transistor The covered portion can act as the channel of the transistor. Based on the above, the active layer 300 may include the channel T1' of the first transistor (eg including the channel T1a' of the sub-transistor T1a and the channel T1b' of the sub-transistor T1b), the channel T2' of the second transistor, the channel T2' of the driving transistor The channel Td' may further include one or more of the channel T3' of the third transistor, the channel T4' of the fourth transistor, the channel T5' of the fifth transistor, and the channel T6' of the sixth transistor.

In order to show the structure of the transistor more clearly, FIG. 10 is a partial enlarged view of the region B in FIG. 9 , showing the structure of a sub-transistor (eg, the sub-transistor T1a). It can be understood that the structures of other transistors may be similar to the structures of the sub-transistors shown in FIG. 10 , so the structures of other transistors will not be repeated here. Referring to FIG. 10, the sub-transistor T1a may include a first electrode T1a1 and a second electrode T1a2, and a channel T1a' between the first electrode T1a1 and the second electrode T1a2. The length l1 of the channel T1a' may be the distance between the first electrode T1a1 and the second electrode T1a2, and the length l1 of the channel T1a' may also be the same as the width h1 of the control electrode T1a3 of the transistor located in the first pattern layer 400 equal. The width w1 of the channel may be the width of the portion of the active layer 300 opposite to the gate electrode T1a3. The width w1 of the channel may also be equal to the width d1 of the active pattern in the active layer 300 .

Continuing to refer to FIG. 9 , as described above, in the pixel circuit provided by some embodiments of the present disclosure, in the first transistor T1 , the width to length ratio of the channel of at least one sub-transistor is smaller than the width of the channel of the second transistor T2 Aspect ratio. That is, the width and length of the channel of at least one of the sub-transistors are relatively small, so that the leakage current of the sub-transistor in the off state can be reduced. In order to reduce the aspect ratio of the channel of the sub-transistor, the length l1 of the channel of the sub-transistor may be increased, or the width w1 of the channel of the sub-transistor may be decreased. In some embodiments, the width w1 of the channel of each sub-transistor is equal to the width w2 of the channel of the second transistor T2. That is, by setting the width w1 of the channel of each sub-transistor equal to the width w2 of the channel of the second transistor T2, and changing the length of the channel of at least one (eg, one; another example, a plurality) of the sub-transistors l1 is set to be greater than the length l2 of the channel of the second transistor T2, so as to realize that the width to length ratio of the channel of at least one (eg, one; another example, each) sub-transistor is smaller than the width to length of the channel of the second transistor T2 Compare. Due to the smaller size of the transistor, it is easier to process the length of the channel of the transistor than to reduce the width of the channel of the transistor, for example, compared to the reduction of the width of the active pattern in the active layer 300 d1, increasing the width h1 of the control electrode of the sub-transistor is easier to implement in the process, which is beneficial to improve the yield of the product.

In some embodiments, in the first transistor T1, the length l1 of the channel of at least one (eg, one; another example, each) sub-transistor is greater than the length l2 of the channel of the second transistor T2 by 0.8˜1.2 μm , so as to achieve the purpose that the width-to-length ratio of the channel of at least one (eg, one; another example, each) sub-transistor is smaller than the width-to-length ratio of the channel of the second transistor T2 . For example, the length l1 of the channel of at least one (eg, one; another example, each) sub-transistor is 0.8 μm, 0.9 μm, 1.0 μm, 1.1 μm, 1,2 μm greater than the length l2 of the channel of the second transistor T2 . In some possible implementations, as described above, the width w1 of the channel of each sub-transistor is equal to the width w2 of the channel of the second transistor, and in this case, the length l1 of the channel of each sub-transistor may be greater than The length l2 of the second transistor T2 is larger by 0.8˜1.2 μm.

In some embodiments, considering the difficulty of the process and the effect of the product, in the first transistor T1, the width w1 of the channel of at least one (eg, one; another example, each) sub-transistor is 2.0˜3.0 μm, and the length l1 is 2.7 to 4.0 μm. Illustratively, the width w1 of the channel of at least one (eg, one; another example, each) sub-transistor is 2.3±0.2 μm and the length l1 is 3.5±0.2 μm. For example, the width w1 of the channel of at least one (eg, one; another example, each) sub-transistor is 2.0 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm , 2.9 μm, or 3.0 μm; the length l1 of the channel of at least one (eg, one; another example, each) sub-transistor is 2.7 μm, 2.8 μm, 2.9 μm, 3.0 μm, 3.1 μm, 3.2 μm, 3.3 μm , 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm, or 4.0 μm.

In some embodiments, the width wd of the channel of the driving transistor Td is larger than the width w2 of the channel of the second transistor T2. In this way, the dimensional uniformity of the channel of the driving transistor Td can be improved, and the performance of the driving transistor Td can be improved. Exemplarily, the width w2 of the channel of the driving transistor Td is 3.0±0.2 μm, eg, 2.8 μm, 2.9 μm, 3.0 μm, 3.1 μm, or 3.2 μm.

Based on the above, in some embodiments, the channel of at least one (eg, one; another example, each) sub-transistor in the first transistor has a width of 2.3±0.2 μm and a length of 3.5±0.2 μm. The channel of at least one (eg, one; another example, each) of the second, third, fourth, fifth, and sixth transistors has a width of 2.3±0.2 μm and a length of 2.5±0.2 μm. The channel of the drive transistor has a width of 3.0±0.2 μm and a length of 20.7±0.2 μm. In this way, the afterimage problem and the bright spot problem of the display image of the display panel can be better improved.

As described above, the display panel includes a plurality of pixel circuits, and in each pixel circuit, the pixel driving circuits may be distributed in an array. The position of the pixel circuit can be used to represent the position of the pixel circuit. Based on this, it can also be said that the pixel circuits are distributed in an array, as shown in FIG. 2 . FIG. 11 shows the structure of two pixel circuits and signal lines located in two rows and one column (eg, the N-1th row and the Nth row, and the Mth column) in FIG. 2 . Referring to FIG. 11, in some embodiments, the display panel may include a first pixel circuit 10a located in the N-1th (N is an integer greater than 1) row and a second pixel circuit 10a located in the Nth (N is an integer greater than 1) row circuit 10b. The first pixel circuit 10a and the second pixel circuit 10b may be the pixel circuits provided in any of the above embodiments. The display panel may also include a reset control signal line R _N-1 located in the N-1th row (or N-1th row), the function of the reset signal line R N-1 and the connection relationship between the reset signal line R _N-1 and the pixel circuit may be as above described in the text, and will not be repeated here. The reset signal line _RN-1 may be coupled to the first pixel circuit 10a, and may also be coupled to the second pixel circuit 10b. Specifically, referring to FIG. 12, the control electrodes T13-10b of the first transistors in the second pixel circuit 10b located in the Nth row and the control electrodes T23-10b of the second transistors in the first pixel circuit 10a located in the N-1th row 10a are all coupled to the reset control signal line _RN-1 of the N-1th row. In this way, the second transistor in the first pixel circuit 10a and the first transistor in the second pixel circuit 10b can be controlled by one reset control signal line _RN-1 , which can make the structure of the display panel more compact and reduce the size of the display panel. Displays the size of the panel.

In some embodiments, in the first transistor of the second pixel circuit 10b, the gate electrodes of each sub-transistor are coupled to each other and form an integrated pattern U. Exemplarily, the first transistor includes two mutually coupled sub-transistors, the two sub-transistors respectively include a control electrode T1a3-10b and a control electrode T1b3-10b, the control electrode T1a3-10b and the control electrode T1b3-10b are coupled to each other, and An integrated pattern U is formed. And, the integrated pattern U is coupled to the reset control signal line _RN-1 .

Further, the reset control signal line R _N-1 , the integrated pattern U, and the control electrode T23 - 10 a of the second transistor in the first pixel circuit 10 a are located in the same pattern layer, for example, in the first pattern layer 400 . Also, the width k of the integrated pattern U is greater than the width l2 of the gate electrode T23-10a of the second transistor, and greater than the width f of the reset control signal line RN _-1 . As such, the length of the channel of at least one (eg, one; another example, each) of the first transistors in the second subpixel 10b may be greater than the length of the channel of the second transistor in the first subpixel 10a. Further, it can be implemented that in a pixel circuit (eg, each pixel circuit), the length of the channel of at least one (eg, one; another example, each) sub-transistor of the first transistor is greater than the length of the channel of the second transistor. The length of the sub-transistor of the first transistor can be achieved, so that the aspect ratio of the channel of at least one (eg, one; another example, each) sub-transistor in the first transistor is smaller than the aspect ratio of the channel of the second transistor. In addition, on the basis that the length of the channel of the sub-transistor is greater than that of the second transistor, the width f of the reset control signal line _RN-1 can also be narrower, which can make the structure of the pixel circuit more compact.

Continuing to refer to FIG. 11 , in some embodiments, the display panel further includes a first light emission control signal line EN _-1 and a second light emission control signal line E _N . The first light-emitting control signal line E _N-1 may be located in the N-1th row (that is, the first light-emitting control signal line E _N-1 is the N-1th light-emitting control signal line), and is connected with the N-1th line of the light-emitting control signal line. A pixel circuit 10a is coupled. The second light-emitting control signal line EN may be located in the _Nth row (ie, the second light-emitting control signal line EN is the _Nth light-emitting control signal line), and is coupled to the second pixel circuit 10b. For the connection relationship between a pixel circuit and the light-emitting control signal line, reference may be made to the above description, which will not be repeated here. Based on the connection relationship between one pixel circuit and the light-emitting control signal line described above, referring to FIG. 12 , the second light _- emitting control signal line EN may be connected with the control electrode of the fifth transistor T5 and the sixth transistor T6 in the second pixel circuit 10b control pole coupling. Similarly, the first light emission control signal line may be coupled to the control electrode of the fifth transistor and the control electrode of the sixth transistor in the first pixel circuit 10a.

Continuing to refer to FIG. 11 , the display panel may further include a first scan signal line GN _-1 and a second scan signal line _GN . The first scan signal line G _N-1 may be located in the N-1th row (that is, the first scan signal line G _N-1 is the N-1th scan signal line), and is connected to the first pixel circuit in the N-1th row. 10a is coupled. The second scan signal line GN may be located in the _Nth row (ie, the second scan signal line GN is the _Nth scan signal line), and is coupled to the second pixel circuit 10b. For the connection relationship between a pixel circuit and the scan signal line, reference may be made to the above description, which will not be repeated here. Based on the connection relationship between one pixel circuit and the scanning signal line described above, referring to FIG. 12 , the second scanning signal line _GN can be connected with the control electrode of the third transistor T3 and the control electrode of the fourth transistor T4 in the second pixel circuit 10b extremely coupled. Similarly, the first scan signal line may be coupled to the control electrode of the third transistor and the control electrode of the fourth transistor in the first pixel circuit 10a.

In some embodiments, the reset signal line R (eg, including the reset signal line R _N-1 ), the scan signal line G (eg, including the first scan signal line GN _-1 and the second scan signal line _GN ), and the light emission control The signal line E (for example, including the first light emission control signal line E _N-1 and the second light emission control signal line E _N ) and the integrated pattern U may be located in the same pattern layer, for example, in the first pattern layer 400 .

In some embodiments, referring to FIG. 8 , the first pattern layer 400 may further include the first plate S1 of the capacitor. That is, the first electrode plate S1, the reset signal line R, the scan signal line G, the light emission control signal line E, and the integrated pattern U may be located in the same pattern layer.

Continuing to refer to FIG. 12 , in some embodiments, the second pattern layer 500 may further include an initialization signal line Vi. The function of the initialization signal line Vi and the connection relationship with the pixel circuit can be referred to the above description, which will not be repeated here. In some possible implementations, the second pole of the second transistor in the first pixel circuit 10a located in the N-1th row and the second pole of the first transistor in the second pixel circuit 10b located in the Nth row may be the same as Initialize the signal line coupling, as shown in FIG. 12 . In some other possible implementations, referring to FIG. 13 , in the display panel, the second pole T22-10a of the second transistor in the first pixel circuit 10a in the N-1th row may be coupled to an initialization signal line, The second electrodes T12-10b of the first transistors in the second pixel circuit 10b in the Nth row may be coupled to another initialization signal line.

Continuing to refer to FIG. 12 , in some embodiments, the second pattern layer 500 may further include the second electrode of the capacitor C. As shown in FIG.

In some embodiments, the third pattern layer 600 may further include a data line D and a first power line EL1. For the functions of the data line D and the first power line EL1 and the connection relationship with the pixel circuit, reference may be made to the above description, which will not be repeated here. The third pattern layer 600 may further include the first electrode of the light emitting device 100 .

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, but not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that it can still be The technical solutions described in the foregoing embodiments are modified, or some technical features thereof are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (15)

1. A pixel circuit, comprising:

a light emitting device;

a driving transistor including a first electrode, a second electrode, and a control electrode, in the driving transistor, the second electrode is coupled to the light emitting device, the driving transistor is configured to control a magnitude of a current flowing through the first electrode and the second electrode in response to a voltage of the control electrode;

a first transistor including a first pole, a second pole, and a control pole, in the first transistor, the first pole is coupled to the control pole of the driving transistor, and the second pole is configured to write a first initialization signal;

a second transistor including a first pole, a second pole, and a control pole, in which the first pole is coupled to the light emitting device and the second pole is configured to write a second initialization signal;

the first transistor comprises at least two sub-transistors connected in series, control electrodes of the at least two sub-transistors are mutually coupled to form a control electrode of the first transistor, and the width-to-length ratio of a channel of at least one sub-transistor is smaller than that of a channel of the second transistor.

2. The pixel circuit according to claim 1,

in the at least two sub-transistors, the width-to-length ratio of the channel of each sub-transistor is the same.

3. The pixel circuit according to any one of claims 1 to 2,

the width of the channel of each sub-transistor is equal to the width of the channel of the second transistor.

4. The pixel circuit according to claim 3,

the length of the channel of at least one sub-transistor is 0.8 to 1.2 μm greater than the length of the channel of the second transistor.

5. The pixel circuit according to claim 1,

the width of the channel of at least one sub-transistor is 2.0-3.0 μm, and the length is 2.7-4.0 μm.

6. The pixel circuit of claim 5,

the width of the channel of at least one sub-transistor is 2.3 + -0.2 μm and the length is 3.5 + -0.2 μm.

7. The pixel circuit according to claim 1,

the width of the channel of the driving transistor is larger than the width of the channel of the second transistor.

8. The pixel circuit according to claim 7,

the width of the channel of the driving transistor is 3.0 +/-0.2 mu m.

9. The pixel circuit according to claim 1, further comprising:

at least one of a capacitor, a fourth transistor, a third transistor, a fifth transistor, and a sixth transistor;

wherein the capacitor comprises a first plate coupled to the control electrode of the drive transistor and a second plate configured to write a supply voltage signal;

the third transistor includes a first pole, a second pole, and a control pole, in which the second pole is coupled to the first pole of the driving transistor, and the first pole is configured to write a data signal;

the fourth transistor includes a first pole, a second pole, and a control pole, and in the fourth transistor, the first pole is coupled to the second pole of the driving transistor, and the second pole is coupled to the control pole of the driving transistor;

the fifth transistor includes a first pole, a second pole, and a control pole, in the fifth transistor, the second pole is coupled to the first pole of the driving transistor, and the first pole is configured to write the power supply voltage signal;

the sixth transistor includes a first electrode, a second electrode, and a control electrode, and in the sixth transistor, the first electrode is coupled to the second electrode of the driving transistor, and the second electrode is coupled to the light emitting device.

10. A display panel, comprising: a plurality of pixel circuits, each pixel circuit being a pixel circuit as claimed in any one of claims 1 to 9.

11. The display panel according to claim 10,

the plurality of pixel circuits includes: a first pixel circuit located at the N-1 th row and a second pixel circuit located at the N-th row;

the display panel further includes:

a reset control signal line to which a control electrode of a first transistor in the second pixel circuit and a control electrode of a second transistor in the first pixel circuit are both coupled;

wherein N is an integer greater than 1.

12. The display panel according to claim 11,

in the first transistor of the second pixel circuit, control electrodes of the respective sub-transistors are coupled to each other and form an integral pattern, the integral pattern being coupled to the reset control signal line;

the reset control signal line, the integral pattern, and a control electrode of a second transistor in the first pixel circuit are located in the same pattern layer, and a width of the integral pattern is greater than a width of the control electrode of the second transistor and greater than a width of the reset control signal line.

13. The display panel according to claim 12,

the pixel circuit includes a fourth transistor, a third transistor, a fifth transistor, and a sixth transistor;

the display panel further includes:

a first light emission control signal line and a second light emission control signal line, a control electrode of a fifth transistor and a control electrode of a sixth transistor in the first pixel circuit being coupled to the first light emission control signal line, a control electrode of a fifth transistor and a control electrode of a sixth transistor in the second pixel circuit being coupled to the second light emission control signal line;

a first scanning signal line to which a control electrode of a fourth transistor and a control electrode of a third transistor in the first pixel circuit are coupled, and a second scanning signal line to which a control electrode of a fourth transistor and a control electrode of a third transistor in the second pixel circuit are coupled;

wherein the first light emission control signal line, the second light emission control signal line, the first scanning signal line, the second scanning signal line, and the integrated pattern are located in the same pattern layer.

14. The display panel according to claim 12,

the pixel circuit includes a capacitor;

the first plate of the capacitor is in the same pattern layer as the integral pattern.

15. A display device comprising the display panel according to any one of claims 10 to 14.

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