CN113744703B - Pixel driving method, driving circuit and display panel - Google Patents
Pixel driving method, driving circuit and display panel Download PDFInfo
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- CN113744703B CN113744703B CN202111312384.7A CN202111312384A CN113744703B CN 113744703 B CN113744703 B CN 113744703B CN 202111312384 A CN202111312384 A CN 202111312384A CN 113744703 B CN113744703 B CN 113744703B
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- 238000000034 method Methods 0.000 title claims abstract description 33
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
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Abstract
The application belongs to the technical field of display panels, and particularly relates to a pixel driving method, a driving circuit and a display panel; the pixel driving method of the present application includes: acquiring target data voltage corresponding to each row of data lines; calculating a reference data voltage based on the target data voltage corresponding to each row of data lines; applying a reference data voltage to each column data line before applying a target data voltage corresponding thereto to each column data line; prior to scanning, the voltage on each column of data lines is adjusted from a reference data voltage to a corresponding target data voltage. By using the pixel driving method, the total power generated by the parasitic capacitors on the data lines of each row corresponding to the display panel is less than the total power generated by adjusting the voltage on the data lines of each row from the remnant voltage of the previous frame to the corresponding target data voltage, so that the power consumption generated by the parasitic capacitors on the data lines can be effectively reduced, and the problem of energy waste caused by large power consumption of the display panel is solved.
Description
Technical Field
The application belongs to the technical field of display panels, and particularly relates to a pixel driving method, a driving circuit and a display panel.
Background
At present, when driving a liquid crystal panel, progressive scanning is often adopted, for example: when the scanning signal corresponding to each row of pixel units of the liquid crystal panel is a high-level signal, the Thin Film Transistor (TFT) of the pixel unit in the row is correspondingly turned on, and at this time, the data signal in the column direction can be written into the pixel unit.
However, in the process of writing the data signal into the pixel unit, a parasitic capacitance is easily generated between the data line for transmitting the data signal and other structures (e.g., the pixel electrode), so that in the charging process, the power consumption of the liquid crystal panel is greatly increased, and how to reduce the power consumption of the liquid crystal panel caused by the parasitic capacitance is a problem which needs to be solved urgently.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present application and therefore may include information that does not constitute prior art known to a person of ordinary skill in the art.
Disclosure of Invention
The present application aims to provide a pixel driving method, a driving circuit and a display panel, which at least overcome the technical problems of large power consumption of the display panel in the related art to a certain extent.
Other features and advantages of the present application will be apparent from the following detailed description, or may be learned by practice of the application.
According to a first aspect of embodiments of the present application, there is provided a pixel driving method, the method including:
acquiring target data voltage corresponding to each row of data lines;
calculating a reference data voltage based on a target data voltage corresponding to each column of the data lines;
applying the reference data voltage to the data line of each column before applying a target data voltage corresponding thereto to the data line of each column;
before scanning, adjusting the voltage on the data line of each column from the reference data voltage to the corresponding target data voltage.
In some embodiments of the present application, based on the above technical solution, a method for calculating a reference data voltage based on target data voltages corresponding to the data lines in each column includes:
the reference data voltage is calculated using the following equation:
Vjz=（V1+V2+V3+…+Vn）/n
wherein, VjzIs a reference data voltage, V1、V2、V3、…VnIs the target data voltage on the corresponding column data line, and n is the total column number of the data lines.
According to a second aspect of the embodiments of the present application, there is provided a pixel driving circuit, including a plurality of pixel units arranged in an array and a plurality of columns of data lines, where the data lines are connected to the pixel units, the pixel driving circuit further including:
the central control board is used for acquiring target data voltage corresponding to each row of data lines and calculating reference data voltage based on the target data voltage corresponding to each row of data lines;
a source drive circuit connected to the central control board and the data lines of each column, for applying the acquired reference data voltage to the data lines of each column before applying a target data voltage corresponding thereto to the data lines of each column; and is further configured to adjust the voltage on the data line of each column from the reference data voltage to a corresponding target data voltage prior to scanning.
In some embodiments of the present application, based on the above technical solution, the source driving circuit includes a first signal unit, and an output end of the first signal unit is connected to each column of the data lines;
the pixel driving circuit further comprises a pre-stored voltage unit, the pre-stored voltage unit comprises a pre-stored voltage output end and a plurality of pre-stored voltage branch circuits which are arranged in parallel and connected with the pre-stored voltage output end, the pre-stored voltage output end is connected with the input end of the first signal unit, and pre-stored voltages on the pre-stored voltage branch circuits are different;
the central control board is connected with the pre-stored voltage unit and used for controlling the conduction of a pre-stored voltage branch circuit with the pre-stored voltage equal to the reference data voltage according to the reference data voltage.
In some embodiments of the present application, based on the above technical solution, the pre-stored voltage branch includes a pre-stored voltage input terminal and a switch transistor, a first end of the switch transistor is connected to the pre-stored voltage input terminal, a second end of the switch transistor is connected to the pre-stored voltage output terminal, and a control terminal is connected to the central control board;
the pre-stored voltage input ends of the pre-stored voltage branches are different in pre-stored voltage.
In some embodiments of the present application, based on the above technical solution, an intermediate transistor is disposed between any two adjacent columns of data lines, and a first end and a second end of the intermediate transistor are respectively connected to the two adjacent columns of data lines;
the output end of the first signal unit is connected with the first end of the starting transistor, and the second end of the starting transistor is connected with the first column of data lines or the last column of data lines;
the source driving circuit further comprises a second signal unit arranged in parallel with the first signal unit, an input end of the second signal unit is connected with the central control board, an output end of the second signal unit is connected with control ends of the initial transistor and the intermediate transistors, and the second signal unit is used for transmitting control signals of the central control board to the control ends of the initial transistor and the intermediate transistors so as to control the initial transistor and the intermediate transistors to be turned on.
In some embodiments of the present application, based on the above technical solution, the source driving circuit further includes a second signal unit disposed in parallel with the first signal unit, and an input end of the second signal unit is connected to the central control board;
the pixel driving circuit further comprises a plurality of shared transistors; the first ends of the shared transistors are connected with the data lines in a one-to-one correspondence manner; the second ends of the shared transistors are connected with the output end of the first signal unit; the control ends of the shared transistors are connected with the output end of the second signal unit;
the second signal unit is used for transmitting the control signal of the central control board to the control end of each shared transistor so as to control each shared transistor to be turned on.
In some embodiments of the application, based on the above technical solution, the pixel driving circuit further includes an analyzing unit connected to the central control board and the source driving circuit, and the analyzing unit is configured to analyze target data voltages corresponding to the data lines in each column according to a received target signal, and transmit the target data voltages corresponding to the data lines in each column to the central control board and the source driving circuit, respectively.
In some embodiments of the present application, based on the above technical solution, each column of the data lines is connected with each column of the pixel units in a one-to-one correspondence.
According to a third aspect of the embodiments of the present application, there is provided a display panel including a substrate and a pixel driving circuit, the pixel driving circuit including a pixel unit and a data line connected to the pixel unit, the pixel unit and the data line being provided on the substrate, the pixel driving circuit further including:
the central control board is used for acquiring target data voltage corresponding to each row of data lines and calculating reference data voltage based on the target data voltage corresponding to each row of data lines;
a source drive circuit connected to the central control board and the data lines of each column, for applying the acquired reference data voltage to the data lines of each column before applying a target data voltage corresponding thereto to the data lines of each column; and is further configured to adjust the voltage on the data line of each column from the reference data voltage to a corresponding target data voltage prior to scanning.
In the technical scheme provided by the embodiment of the application, the reference data voltage is calculated by acquiring the target data voltage corresponding to each row of data lines and based on the target data voltage corresponding to each row of data lines; applying the reference data voltage to the data line of each column before applying a target data voltage corresponding thereto to the data line of each column; before scanning, the voltage on the data line of each column is a reference data voltage, and the reference data voltage is calculated from the target data voltage corresponding to the data line of each column, so when the voltage on the data line of each column is adjusted from the reference data voltage to the corresponding target data voltage, the total power generated by the parasitic capacitance on the data line of each column corresponding to the display panel is less than the total power generated by adjusting the voltage on the data line of each column from the remnant voltage of the previous frame to the corresponding target data voltage, therefore, the power consumption generated by the parasitic capacitance on the data line can be effectively reduced by the above method, and the problem of energy waste caused by large power consumption of the display panel is solved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 schematically shows a flow chart of a pixel driving method in a first embodiment of the present application.
Fig. 2 schematically illustrates a schematic diagram of parasitic capacitances on data lines according to an embodiment of the present application.
Fig. 3 schematically shows a structural diagram of the pixel driving circuit described in embodiment two of the present application.
Fig. 4 schematically shows a structural diagram of a source driver circuit in a second embodiment of the present application.
Fig. 5 schematically illustrates a structural diagram of a pre-stored voltage unit in the second embodiment of the present application.
Fig. 6 schematically shows a schematic structural diagram of a second embodiment of the present application after the parsing unit is connected to the central control board and the source driving circuit.
Fig. 7 schematically illustrates a structure diagram of a pixel unit after being connected to a data line in an embodiment of the present application.
Fig. 8 schematically shows a structural diagram of a pixel driving circuit described in embodiment three of the present application.
Fig. 9 schematically shows a structural diagram of a display panel in a fourth embodiment of the present application.
300-a pixel drive circuit; 310-a central control panel; 320-source drive circuit; 410-a first signal unit; 412 — output of the first signal unit; 330-pre-storing a voltage unit; 510-pre-stored voltage output terminal; 520-pre-stored voltage branch; 411 — input of first signal unit; 521-a pre-stored voltage input terminal; 522-a switching transistor; 340-intermediate transistor; 350-start transistor; 420-a second signal unit; 421-input of a second signal unit; 422-output of the second signal unit; 360-an analysis unit; 430-a third signal unit; 431-an input of a third signal unit; 432-an output of the third signal unit; 710-pixel cells; 720-a display unit; 730-thin film transistor; 810-shared transistor; 900-a display panel; 910-a first substrate; 920-a second substrate; 930-common electrode; 940-pixel electrodes.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.
The following detailed description of the pixel driving method, the driving circuit and the display panel provided in the present application will be made with reference to the embodiments.
Example one
As shown in fig. 1, fig. 1 schematically shows a flowchart of a pixel driving method in a first embodiment of the present application.
According to a first aspect of the present application, there is provided a pixel driving method, which can be applied to a display panel, the method including steps S110 to S140.
Step S110: and acquiring a target data voltage corresponding to each row of data lines.
The target data voltage is a data signal written into the pixel unit and drives the pixel unit to display. When the scanning signal corresponding to each row of pixel units of the liquid crystal panel is a high-level signal, the Thin Film Transistor (TFT) of the pixel unit in the row is correspondingly turned on, and at this time, the data signal on the data line in the column direction can be written into the pixel unit.
For any target frame picture developed by the liquid crystal panel, the target data voltage corresponding to each row of data lines is required to drive the pixel units on the row to develop so as to realize the development of the target frame picture. According to the method for acquiring the target data voltage corresponding to each row of data lines, the target frame picture to be displayed can be acquired, and then the target data voltage corresponding to each row of data lines can be acquired based on the target frame picture.
Step S120: the reference data voltage is calculated based on the target data voltage corresponding to each column data line.
Before describing a specific calculation method of the reference data voltage, the present application first describes a calculation process of the lower parasitic capacitance and the power generated by the corresponding parasitic capacitance.
The parasitic capacitance means that the capacitance is not designed at the place originally, but since mutual capacitance always exists between the wirings, the mutual capacitance is called as if the capacitance is parasitic between the wirings. The parasitic capacitance generally refers to the capacitance characteristics of the inductor, the resistor, the chip pin and the like under high frequency conditions.
On the display panel, since a plurality of data lines are required to provide target data voltages for different pixel units, parasitic capacitance is easily generated between the data lines and other structures (e.g., pixel electrodes).
As shown in fig. 2, fig. 2 schematically shows a schematic diagram of parasitic capacitance on a data line in a first embodiment of the present application. Assuming that there are four columns of data lines corresponding to S1, S2, S3, and S4, respectively, the parasitic capacitances C1, C2, C3, and C4 cannot be avoided.
And the above calculation formula of the power consumption of the single parasitic capacitance is as follows:
W=fCV2/2
wherein, W is the power generated by a single parasitic capacitor, f is the frequency of voltage change, C is the capacitance value of the parasitic capacitor on the data line, and V refers to the voltage change value on the data line before the scanning occurs. Where f and C are relatively fixed values, i.e., when the wiring of the data line is determined, the corresponding values of f and C are fixed and unchanged, and thus the power of a single parasitic capacitance is actually positively correlated with the voltage variation value V on the data line.
For a display panel, the sum of the total power generated by the parasitic capacitance and the power generated by the single parasitic capacitance on each column data line is positive correlated with the sum of the squares of the voltage variation values of each parasitic capacitance because the frequency f and the capacitance value C of the voltage variation of each parasitic capacitance are fixed. For example, continuing with the example of FIG. 2, there are four rows of data lines corresponding to S1, S2, S3, S4, respectively, and corresponding target data voltages V1，V2，V3，V4. The parasitic capacitances C1, C2, C3 and C4 on the four rows of data lines all have a parasitic capacitance C1. Before scanning, the voltage left behind in the last frame of picture on the data line is V1’，V2’，V3’，V4'. The corresponding calculation formula of the total power generated by its parasitic capacitance is as follows:
Wz=f×c1×[ (V1- V1’)2+ (V2- V2’)2+ (V3- V3’)2+ (V4- V4’)2]
where Wz represents the total power generated by the parasitic capacitance, it can be seen from the above equation that the value of Wz is related to [ (V) with f and c1 fixed1- V1’)2+ (V2- V2’)2+ (V3- V3’)2+ (V4- V4’)2]Positively correlated, therefore, when [ (V)1- V1’)2+ (V2- V2’)2+ (V3- V3’)2+ (V4- V4’)2]When decreasing, the corresponding Wz also decreases.
For the liquid crystal molecules of the liquid crystal panel, there is a characteristic that the liquid crystal molecules cannot be fixed with a certain voltage all the time, or else for a long time, even if the voltage is cancelled, the liquid crystal molecules cannot rotate due to the change of the electric field because of the damage of the characteristic, so as to form different gray scales. The gray scale is formed by adjusting the pressure difference between the pixel electrodes at the two ends of the pixel molecules and the common electrode, so as to adjust the rotation angle of the liquid crystal, and further form the brightness difference. Therefore, in order to avoid the liquid crystal molecules from forming inertia, it is necessary to provide dynamic voltage control to the liquid crystal molecules, and the dynamic voltage control is based on the voltage on the common electrode, i.e. the voltage on the common signal terminal for comparison, and the dynamic voltage control is positive and negative voltage alternation, wherein the positive and negative alternation is not based on 0 but based on the voltage on the common electrode.
The voltage of the pixel electrode is derived from the target data voltage, so that the target data voltage is positive and negative with respect to the voltage on the common electrode, for example, when the target data voltages V on four rows of data lines are positive and negative with respect to the target data voltage corresponding to two frames apart1Is 8V, V2Is 8V, V3Is 5V, V45V, corresponding to a voltage V left over in the previous frame1' is-2V, V2' is-3V, V3' is-5V, V4' is-7V. Then corresponding [ (V)1- V1’)2+ (V2- V2’)2+ (V3- V3’)2+ (V4- V4’)2]Has a value of 465, which is very large.
Therefore, the present application applies the reference data voltage to each column data line before applying the target data voltage corresponding thereto to each column data line. The corresponding calculation formula of the total power generated by its parasitic capacitance is as follows:
Wz= f×c1×[ (V1-Vjz)2+ (V2-Vjz)2+ (V3-Vjz)2+ (V4-Vjz)2]
wherein Wz represents the total power generated by parasitic capacitance, VjzThe reference data voltage value. Reference data voltage V of the present applicationjzCalculated from the target data voltages corresponding to the data lines of each column, and the difference will be described below.
For one frame, the corresponding target data voltage is fixed, therefore, the present application modifies the above VjzTo achieve a total power reduction of the parasitic capacitance. For example, when the target data voltage V is on four columns of data lines1Is 8V, V2Is 8V, V3Is 5V, V4Is 5V, reference data voltage V with any valuejzIs 8V. Corresponding [ (V)1-Vjz)2+ (V2-Vjz)2+ (V3-Vjz)2+ (V4-Vjz)2]Has a value of 18. When the reference data voltage V of the application takes any valuejzNegative number, corresponding to (V1-V)jz)2+ (V2-Vjz)2+ (V3-Vjz)2+ (V4-Vjz)2The value of (a) will be larger, resulting in more power being generated by the parasitic capacitance. Thus, for the reference data voltage VjzThe value cannot be arbitrarily taken. And the reference data voltage V of the present applicationjzCalculated based on the target data voltages for each column of data lines.
Specifically, the method for calculating the reference data voltage based on the target data voltage corresponding to each row of data lines includes: the reference data voltage is calculated using the following equation:
Vjz=（V1+V2+V3+…+Vn）/n
wherein, VjzIs a reference data voltage, V1、V2、V3、…VnIs the target data voltage on the corresponding column data line, and n is the total column number of the data lines. The above formula is to calculate the voltage average value of the target data voltage corresponding to each column data line as the voltage value of the reference data voltage.
Continuing with the example of the four corresponding rows of data lines in FIG. 2, the target data voltages V on the four rows of data lines1Is 8V, V2Is 8V, V3Is 5V, V4Is 5V, corresponding to the reference data voltage VjzIs 6.5V, then corresponding [ (V)1-Vjz)2+ (V2-Vjz)2+ (V3-Vjz)2+ (V4-Vjz)2]Is 9, and thus, the reference data voltage is calculated by the above formula, the value of the total power Wz generated by the corresponding parasitic capacitance is minimized.
Of course, the reference data voltage V may be calculated by other formulasjzBy calculating the median, standard deviation or variance of the target data voltage corresponding to each column data line as the reference data voltage V, for examplejz. And the reference data voltage V calculated by other formulasjzThe total power Wz generated by the corresponding parasitic capacitance is much smaller than the power generated by adjusting the voltage on the data line of each column from the remnant voltage of the previous frame to the corresponding target data voltage.
When the reference data voltage V is calculatedjzThereafter, step S130 may be performed.
Step S130: before a target data voltage corresponding to each column data line is applied to each column data line, a reference data voltage is applied to each column data line.
The voltage on the data line of each column is converted from the voltage remaining in the previous frame into the reference data voltage by step S130, and then step S140 is continued.
Step S140: prior to scanning, the voltage on each column of data lines is adjusted from a reference data voltage to a corresponding target data voltage.
Before the next frame starts to scan, the voltage on each column of data lines is adjusted from the reference data voltage to the corresponding target data voltage, and the power generated by the parasitic capacitor is lower after the scanning occurs through the step.
The reference data voltage is calculated by using the target data voltage on each row of data lines, and is applied to each row of data lines before the target data voltage corresponding to the reference data voltage is applied to each row of data lines. By the method, the power generated by the parasitic capacitance on each row of data lines corresponding to the display panel is smaller than the power generated by the parasitic capacitance on the existing display panel, so that the problem of energy waste caused by large power consumption of the display panel can be solved by the method.
The above section describes the content of the pixel driving of the present application, and the content of the second aspect of the present application regarding the pixel driving circuit will be continued by other embodiments.
Example two
As shown in fig. 3, fig. 3 schematically shows a structural schematic diagram of the pixel driving circuit described in the second embodiment of the present application.
The application discloses a pixel driving circuit 300, which comprises a plurality of pixel units arranged in an array and a plurality of columns of data lines, wherein fig. 3 schematically shows the case of four columns of data lines, which correspond to S1, S2, S3 and S4 respectively, and parasitic capacitances C1, C2, C3 and C4 exist on the four columns of data lines. The data lines are connected to the pixel units, wherein the pixel driving circuit 300 further includes a central control board 310 and a source driving circuit 320.
The central control board 310 is configured to obtain a target data voltage corresponding to each row of data lines, and calculate a reference data voltage based on the target data voltage corresponding to each row of data lines. The specific method for obtaining the target data voltage corresponding to each row of data lines and calculating the reference data voltage based on the target data voltage corresponding to each row of data lines may use corresponding steps in the pixel driving method, and details are not repeated here.
The source driving circuit 320 of the present application is connected to the central control board 310 and each column data line, and is configured to apply the acquired reference data voltage to each column data line before applying the target data voltage corresponding to each column data line; and is also used to adjust the voltage on each column data line from the reference data voltage to the corresponding target data voltage prior to scanning.
The pixel driving circuit 300 according to the present application calculates a reference data voltage using the target data voltage on each column data line of the central control board 310, and applies the reference data voltage to each column data line through the source driving circuit 320 before applying the target data voltage corresponding thereto to each column data line. With the pixel driving circuit 300 of the present application, the power generated by the parasitic capacitor on each column data line corresponding to the display panel 900 is smaller than the power generated by the parasitic capacitor on the existing display panel 900, so that the problem of energy waste caused by large power consumption of the display panel 900 can be solved.
The central control board 310, the source driving circuit 320 and the pixel driving circuit 300 will be described in detail below.
As shown in fig. 4, fig. 4 schematically illustrates a structural schematic diagram of a source driving circuit 320 in a second embodiment of the present application.
The source driving circuit 320 of the present application includes a first signal unit 410, an output end 412 of the first signal unit is connected to each column data line, and the first signal unit 410 is configured to apply the acquired reference data voltage to each column data line.
The pixel driving circuit 300 of the present application further includes a pre-stored voltage unit 330, as shown in fig. 5, fig. 5 schematically illustrates a structural diagram of the pre-stored voltage unit 330 in the second embodiment of the present application.
The pre-stored voltage unit 330 of this application is including pre-storing the voltage output end 510 and a plurality of parallelly connected setting and with pre-storing the voltage branch road 520 that voltage output end 510 is connected, pre-storing the effect of voltage branch road 520 and be for pre-storing the different pre-stored voltage of voltage output end 510 output, the pre-stored voltage on each pre-stored voltage branch road 520 is different.
The pre-stored voltage output terminal 510 is connected to the input terminal 411 of the first signal unit, and is used for providing the pre-stored voltage for the first signal unit 410. Of course, in the present application, the pre-stored voltage output terminal 510 may be directly connected to each column data line, so that the corresponding source driving circuit 320 may omit the first signal unit 410 and the pre-stored voltage output terminal 510 may provide the pre-stored voltage for the data line.
The central control board 310 of the present application is connected to the pre-stored voltage unit 330, and is used for controlling the pre-stored voltage branch 520 with the same voltage as the reference data voltage to be conducted according to the reference data voltage. After the central control board 310 calculates the reference data voltage, the central control board 310 controls the pre-stored voltage branch 520 corresponding to the pre-stored voltage that is the same as the reference data voltage to be turned on, so as to provide the pre-stored voltage for the data line.
Further, with continued reference to fig. 5, the pre-stored voltage branch 520 of the present application includes a pre-stored voltage input terminal 521 and a switch transistor 522, wherein a first terminal of the switch transistor 522 is connected to the pre-stored voltage input terminal 521, a second terminal of the switch transistor 522 is connected to the pre-stored voltage output terminal 510, a control terminal of the switch transistor 522 is connected to the central control board 310, and pre-stored voltages at the pre-stored voltage input terminals 521 of the pre-stored voltage branch 520 are different. The switching transistor 522 functions to interface a control signal of the central control board 310 to turn on the pre-stored voltage branch 520 corresponding to the pre-stored voltage identical to the reference data voltage, and to provide the pre-stored voltage identical to the reference data voltage to the pre-stored voltage output terminal 510.
The pre-stored voltage unit 330 of the present application can be an independent unit, for example, referring to fig. 3, the pre-stored voltage unit 330 is connected to the source driving circuit 320 and the central control board 310 as an independent unit. Of course, the pre-stored voltage unit 330 of the present application can also integrate the pre-stored voltage unit 330 in the source driving circuit 320 or the central control board 310, which is not limited in the present application.
The pre-stored voltage branch 520 corresponding to this application utilizes pre-stored voltage input end 521 to provide the pre-charging voltage for pre-stored voltage branch 520, receives the control signal of center control board 310 through switch transistor 522, and the corresponding pre-stored voltage branch 520 of control switches on, utilizes this circuit design, can simplify the structure of circuit, improves the overall arrangement efficiency of circuit, realizes simultaneously that the voltage that will prestore transmits source drive circuit 320 or transmits to each row data line through pre-stored voltage unit 330.
The content of the pre-stored voltage unit 330 is described in the above section, and the detailed connection structure between the source driving circuit 320 and each column data line is described in the following.
The source driving circuit 320 of the present application includes a first signal unit 410, and the output end 412 of the first signal unit is connected to each column data line.
With reference to fig. 3, an intermediate transistor 340 is disposed between any two adjacent columns of data lines, and a first end and a second end of the intermediate transistor 340 are respectively connected to the two adjacent columns of data lines, and corresponding to fig. 3, because there are only four columns of data lines, the number of the intermediate transistors 340 is three, and the intermediate transistors are respectively located between any two adjacent columns of data lines, where the intermediate transistors 340 are used to transmit voltages between the data lines of each column.
The output 412 of the first signal unit is connected to the first end of the start transistor 350, and the second end of the start transistor 350 is connected to the first column data line or the last column data line, wherein the second end of the start transistor 350 in fig. 3 is connected to the last column data line. The start transistor 350 may be used as a switch for pre-stored voltage of the first column data line or the last column data line, when the start transistor 350 is turned on, the output 412 of the corresponding first signal unit transmits the reference data voltage to the first column data line or the last column data line, and then the first column data line or the last column data line is transmitted to other column data lines through the middle transistor 340.
The intermediate transistor 340 and the start transistor 350 can be controlled by the source driving circuit 320, and specifically, with reference to fig. 4, the source driving circuit 320 further includes a second signal unit 420 disposed in parallel with the first signal unit 410, an input end 421 of the second signal unit is connected to the central control board 310, an output end 422 of the second signal unit is connected to the control ends of the start transistor 350 and the intermediate transistors 340, and the second signal unit 420 is configured to transmit a control signal of the central control board 310 to the control ends of the start transistor 350 and the intermediate transistors 340 to control the start transistor 350 and the intermediate transistors 340 to be turned on. After the central control board 310 calculates the reference data voltage, it transmits a control signal to the second signal unit input end 421 of the source driving circuit 320, and the source driving circuit 320 controls the control ends of the initial transistor 350 and each intermediate transistor 340 to be turned on through the second signal unit output end 422, so as to implement that the output end 412 of the first signal unit transmits the reference data voltage to the first column of data lines or the last column of data lines, and simultaneously implement that the first column of data lines or the last column of data lines transmits the reference data voltage to each column of data lines.
The above scheme corresponds to the case where the output end 412 of the first signal unit in fig. 3 is connected to the data line of each column. Of course, the pre-stored voltage output terminal 510 of the pre-stored voltage unit 330 of the present application may also be directly connected to each column data line, and the specific connection method may be the same as the above connection method, and when the pre-stored voltage output terminal 510 is directly connected to each column data line, the corresponding source driving circuit 320 may omit the first signal unit 410.
The circuit design is utilized, the structure of the circuit can be simplified, and the layout efficiency of the circuit is improved. And simultaneously, the reference data voltage is applied to each column data line before the target data voltage corresponding to each column data line is applied to each column data line.
The above section describes the specific connection structure between the source driver circuit 320 and each column of data lines, and the following description continues with the description of the other contents of the pixel driver circuit 300.
As shown in fig. 6, fig. 6 schematically shows a schematic structural diagram of a second embodiment of the present application after a parsing unit is connected to a central control board and a source driving circuit.
The pixel driving circuit 300 of the present application further includes an analyzing unit 360, the analyzing unit 360 is connected to the central control board 310 and the source driving circuit 320, and the analyzing unit 360 is configured to analyze target data voltages corresponding to each column of data lines according to the received target signals, and transmit the target data voltages corresponding to each column of data lines to the central control board 310 and the source driving circuit 320, respectively. The analyzing unit 360 is a data source of the target data voltage, and when the analyzing unit 360 obtains the target signal corresponding to the target frame picture, the target data voltage corresponding to each row of data lines is analyzed and transmitted to the central control board 310, and the central control board 310 calculates the reference data voltage according to the target data voltage corresponding to each row of data lines, and then transmits the reference data voltage to the source driving circuit 320 through the pre-stored voltage unit 330, and finally transmits the reference data voltage to each row of data lines through the source driving circuit 320.
The parsing unit 360 of the present application may further transmit the target data voltage to the source driving circuit 320, wherein a signal converter is disposed in the source driving circuit 320, and the signal converter is used to convert a digital signal of the target data voltage into an analog signal and transmit the analog signal to the central control board 310, and at this time, the corresponding parsing unit 360 may be connected to only the source driving circuit 320 without being connected to the central control board 310.
With reference to fig. 4, the source driving circuit 320 of the present application is further provided with a third signal unit 430, wherein an input end 431 of the third signal unit is used for being connected to the above-mentioned parsing unit 360 and is used for inputting a target data voltage required by each column of data lines, an output end 432 of the third signal unit is connected to each column of data lines, and the third signal unit 430 is used for adjusting a voltage on each column of the data lines from the reference data voltage to a corresponding target data voltage before scanning.
The above section describes the content of the parsing unit 360 of the present application, and the following description continues to describe other contents of the pixel driving circuit 300 of the present application.
As shown in fig. 7, fig. 7 schematically shows a structural diagram of a pixel unit and a data line in a second embodiment of the present application after connection.
Each row of data lines is connected with each row of pixel units in a one-to-one correspondence mode. Referring to fig. 7, three rows of data lines, S1, S2 and S3, are schematically illustrated in fig. 7, where three pixel units 710 are disposed in each row, and each row of data lines is connected to each row of pixel units 710 in a one-to-one correspondence. The pixel unit 710 includes a thin film transistor 730 (TFT) for controlling the development and a development unit 720 for performing the development. The control terminal of the tft 730 is connected to the scan lines arranged in the transverse direction for controlling the tft 730 to be turned on, and when the tft 730 is turned on, each row of the data lines provides a target data voltage for the display unit 720, so that each display unit 720 performs display.
The application discloses a pixel driving circuit 300 through the second embodiment. Through the pixel driving circuit 300 of the present application, the power generated by the parasitic capacitance on each column of data lines corresponding to the display panel 900 is less than the power generated by the parasitic capacitance on the existing display panel 900, thereby reducing the temperature generated by the power consumption of the display panel 900 and improving the product competitiveness, and therefore, the problem of energy waste caused by the large power consumption of the display panel 900 can be solved.
The above section describes the second embodiment of the pixel driving circuit 300, and the third embodiment of the present application.
EXAMPLE III
As shown in fig. 8, fig. 8 schematically shows a structural schematic diagram of a pixel driving circuit in a third embodiment of the present application.
The source driving circuit 320 of the pixel driving circuit described in the third embodiment of the present application and the specific connection structure of each column of data lines are different from those of the second embodiment.
The pixel driving circuit 300 according to the third embodiment further includes a plurality of shared transistors 810; the first ends of the shared transistors 810 are connected with the data lines in a one-to-one correspondence; second terminals of the plurality of shared transistors 810 are all connected to the output terminal 412 of the first signal unit; the control terminals of the plurality of shared transistors 810 are all connected with the output terminal 422 of the second signal unit; the second signal unit 420 is used for transmitting a control signal of the central control board 310 to the control terminal of each shared transistor 810 to control each shared transistor 810 to be turned on.
That is, in the third embodiment of the present application, the precharge voltage on the data line of the present application can be transmitted through the output terminal 412 of the first signal unit alone, without performing voltage transmission between the data lines.
Based on the above scheme, the pre-stored voltage unit 330 corresponding to the present application can correspondingly set a plurality of pre-stored voltage output terminals 510 and a plurality of pre-stored voltage branches 520 connected in parallel and connected to the pre-stored voltage output terminals 510. The corresponding pre-stored voltage branch 520 transmits the target data voltage of the line of data lines as the reference data voltage, so that for each line of data lines, before the target data voltage corresponding to the line of data lines is applied to each line of data lines, the reference data voltage identical to the target data voltage of each line of data lines is applied to each line of data lines, before scanning, no voltage change exists in each corresponding line of data lines, the power generated by the corresponding parasitic capacitor is small, and the power can be further reduced by the arrangement, so that the problem of low power consumption of the display panel 900 is solved.
Other structures of the pixel driving circuit described in the third embodiment of the present application may be the same as those of the second embodiment, and are not described herein again.
The above section describes the content of the pixel driving circuit 300 of the present application, and the content of the display panel 900 of the present application is continued.
Example four
As shown in fig. 9, fig. 9 schematically shows a structural diagram of a display panel 900 in a fourth embodiment of the present application.
Refer to fig. 3 and 9. According to a third aspect of the present application, the present application discloses a display panel 900, which includes a substrate and a pixel driving circuit 300, the pixel driving circuit 300 may include a pixel unit 710 and a data line connected to the pixel unit 710, and the pixel unit 710 and the data line may be disposed on the substrate.
For example, the substrates may include a first substrate 910 and a second substrate 920, and the first substrate 910 and the second substrate 920 are disposed opposite to each other, wherein the first substrate 910 and the second substrate 920 may be glass substrates, and liquid crystal (not shown) is disposed between the first substrate 910 and the second substrate 920. The pixel unit 710 may include a thin film transistor 730 (TFT) for controlling development, a pixel electrode 940, and a common electrode 930, the thin film transistor 730 and the pixel electrode 940 may be disposed on the second substrate 920, and the common electrode 930 may be disposed on the first substrate 910, but is not limited thereto, and the common electrode 930 may also be disposed on the second substrate 920.
The pixel driving circuit 300 of the present application further includes a central control board 310 and a source driving circuit 320. The central control board 310 is configured to obtain a target data voltage corresponding to each row of data lines, and calculate a reference data voltage based on the target data voltage corresponding to each row of data lines; the source driving circuit 320 is connected to the central control board 310 and each column data line, and is configured to apply the acquired reference data voltage to each column data line before applying the target data voltage corresponding to each column data line; and is also used to adjust the voltage on each column data line from the reference data voltage to the corresponding target data voltage prior to scanning.
The central control board 310 and the source driving circuit 320 may be integrated on the first substrate 910 or the second substrate 920, or may be separately disposed and connected to the data lines and the pixel units 710 on the first substrate 910 or the second substrate 920.
The structures of the central control board 310 and the source driving circuit 320 may use the corresponding structures of the pixel driving circuit 300, and are not described herein again.
In the display panel corresponding to the application, because the central control board and the source driving circuit are added, the reference data voltage is calculated by utilizing the target data voltage on each line of data lines of the central control board, and the reference data voltage is applied to each line of data lines through the source driving circuit before the target data voltage corresponding to each line of data lines is applied to each line of data lines. The power generated by the parasitic capacitor on each row of data lines corresponding to the display panel is smaller than the power generated by the parasitic capacitor on the existing display panel, so that the problem of energy waste caused by large power consumption of the display panel can be solved.
It is noted that references herein to "on … …", "formed on … …" and "disposed on … …" can mean that one layer is formed or disposed directly on another layer or that one layer is formed or disposed indirectly on another layer, i.e., there is another layer between the two layers.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
It should be noted that, although the terms "first", "second", etc. may be used herein to describe various elements, components, elements, regions, layers and/or sections, these elements, components, elements, regions, layers and/or sections should not be limited by these terms. Rather, these terms are used to distinguish one element, component, element, region, layer or section from another.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims. Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (10)
1. A pixel driving method, the method comprising:
acquiring a target data voltage corresponding to each row of data lines, wherein the data lines comprise parasitic capacitors;
calculating a reference data voltage based on a target data voltage corresponding to each column of the data lines;
applying the reference data voltage to the data line of each column before applying a target data voltage corresponding thereto to the data line of each column;
before scanning, the voltage on the data line of each column is adjusted from the reference data voltage to the corresponding target data voltage, so that the power generated by the parasitic capacitance before scanning is reduced.
2. The pixel driving method according to claim 1, wherein the method of calculating the reference data voltage based on the target data voltage corresponding to each column of the data lines comprises:
the reference data voltage is calculated using the following equation:
Vjz=（V1+V2+V3+…+Vn）/n
wherein, VjzIs a reference data voltage, V1、V2、V3、…VnIs the target data voltage on the corresponding column data line, and n is the total column number of the data lines.
3. A pixel driving circuit comprises a plurality of pixel units arranged in an array and a plurality of columns of data lines, wherein the data lines are connected with the pixel units, and the pixel driving circuit is characterized by further comprising:
the central control board is used for acquiring target data voltage corresponding to each row of data lines and calculating reference data voltage based on the target data voltage corresponding to each row of data lines, wherein the data lines comprise parasitic capacitors;
a source drive circuit connected to the central control board and the data lines of each column, for applying the acquired reference data voltage to the data lines of each column before applying a target data voltage corresponding thereto to the data lines of each column; and the data line driving circuit is further used for adjusting the voltage on the data line of each column from the reference data voltage to the corresponding target data voltage before scanning so as to reduce the power generated by the parasitic capacitance before scanning.
4. The pixel driving circuit according to claim 3,
the source driving circuit comprises a first signal unit, and the output end of the first signal unit is connected with the data lines of each column;
the pixel driving circuit further comprises a pre-stored voltage unit, the pre-stored voltage unit comprises a pre-stored voltage output end and a plurality of pre-stored voltage branch circuits which are arranged in parallel and connected with the pre-stored voltage output end, the pre-stored voltage output end is connected with the input end of the first signal unit, and pre-stored voltages on the pre-stored voltage branch circuits are different;
the central control board is connected with the pre-stored voltage unit and used for controlling the conduction of a pre-stored voltage branch circuit with the pre-stored voltage equal to the reference data voltage according to the reference data voltage.
5. The pixel driving circuit according to claim 4, wherein the pre-stored voltage branch comprises a pre-stored voltage input terminal and a switching transistor, a first terminal of the switching transistor is connected to the pre-stored voltage input terminal, a second terminal of the switching transistor is connected to the pre-stored voltage output terminal, and a control terminal of the switching transistor is connected to the central control board;
the pre-stored voltage input ends of the pre-stored voltage branches are different in pre-stored voltage.
6. The pixel driving circuit according to claim 4,
a middle transistor is arranged between any two adjacent rows of data lines, and a first end and a second end of the middle transistor are respectively connected with the data lines of the two adjacent rows;
the output end of the first signal unit is connected with the first end of the starting transistor, and the second end of the starting transistor is connected with the first column of data lines or the last column of data lines;
the source driving circuit further comprises a second signal unit arranged in parallel with the first signal unit, an input end of the second signal unit is connected with the central control board, an output end of the second signal unit is connected with control ends of the initial transistor and the intermediate transistors, and the second signal unit is used for transmitting control signals of the central control board to the control ends of the initial transistor and the intermediate transistors so as to control the initial transistor and the intermediate transistors to be turned on.
7. The pixel driving circuit according to claim 4,
the source driving circuit also comprises a second signal unit arranged in parallel with the first signal unit, and the input end of the second signal unit is connected with the central control board;
the pixel driving circuit further comprises a plurality of shared transistors; the first ends of the shared transistors are connected with the data lines in a one-to-one correspondence manner; the second ends of the shared transistors are connected with the output end of the first signal unit; the control ends of the shared transistors are connected with the output end of the second signal unit;
the second signal unit is used for transmitting the control signal of the central control board to the control end of each shared transistor so as to control each shared transistor to be turned on.
8. The pixel driving circuit according to claim 3, further comprising an analyzing unit connected to the central control board and the source driving circuit, wherein the analyzing unit is configured to analyze a target data voltage corresponding to each column of the data lines according to a received target signal, and transmit the target data voltage corresponding to each column of the data lines to the central control board and the source driving circuit, respectively.
9. The pixel driving circuit according to claim 3, wherein each column of the data lines is connected to each column of pixel cells in a one-to-one correspondence.
10. A display panel comprises a substrate and a pixel driving circuit, wherein the pixel driving circuit comprises a pixel unit and a data line connected with the pixel unit, the pixel unit and the data line are arranged on the substrate, and the pixel driving circuit further comprises:
the central control board is used for acquiring target data voltage corresponding to each row of data lines and calculating reference data voltage based on the target data voltage corresponding to each row of data lines, wherein the data lines comprise parasitic capacitors;
a source drive circuit connected to the central control board and the data lines of each column, for applying the acquired reference data voltage to the data lines of each column before applying a target data voltage corresponding thereto to the data lines of each column; and the data line driving circuit is further used for adjusting the voltage on the data line of each column from the reference data voltage to the corresponding target data voltage before scanning so as to reduce the power generated by the parasitic capacitance before scanning.
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| CN1811874A (en) * | 2005-01-27 | 2006-08-02 | 三菱电机株式会社 | Display apparatus |
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