CN113745191A - Integrated circuit, consumable chip and MCU chip - Google Patents
Integrated circuit, consumable chip and MCU chip Download PDFInfo
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- CN113745191A CN113745191A CN202111136265.0A CN202111136265A CN113745191A CN 113745191 A CN113745191 A CN 113745191A CN 202111136265 A CN202111136265 A CN 202111136265A CN 113745191 A CN113745191 A CN 113745191A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
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Abstract
The embodiment of the application provides an integrated circuit, a consumable chip and an MCU chip, which comprise a semiconductor substrate, wherein the semiconductor substrate comprises a first area, a second area and a deep well; a deep well is disposed in the semiconductor substrate and extends to a surface of the semiconductor substrate, the deep well surrounding the first region. The first region comprises a first doped region and the second region comprises a second doped region; the first doped region is electrically connected with one of the signal ground and the power ground, and the second doped region is electrically connected with the other of the signal ground and the power ground. In the present application, the signal ground and the power ground are provided in different regions of the semiconductor substrate isolated by the deep well, not only isolating the potentials of the signal ground and the power ground, but also avoiding signal crosstalk between the signal ground and the power ground.
Description
[ technical field ] A method for producing a semiconductor device
The application relates to the technical field of electronics, especially, relate to an integrated circuit, consumptive material chip and MCU chip.
[ background of the invention ]
In an integrated circuit, a current flowing through a power supply is generally large, and a current flowing through a signal ground is generally small. Grounding points with different functions are directly connected together by a ground wire, and a high-power circuit can influence a zero potential reference point of a low-power circuit through the ground wire, so that crosstalk among signals of different circuits is caused.
[ application contents ]
In view of this, the present application provides an integrated circuit, a consumable chip and an MCU chip to solve the above problems.
In a first aspect, an embodiment of the present application provides an integrated circuit, including a semiconductor substrate, the semiconductor substrate including a first region, a second region, and a deep well; a deep well is disposed in the semiconductor substrate and extends to a surface of the semiconductor substrate, the deep well surrounding the first region. The first region comprises a first doped region and the second region comprises a second doped region; the first doped region is electrically connected with one of the signal ground and the power ground, and the second doped region is electrically connected with the other of the signal ground and the power ground.
In one implementation manner of the first aspect, the semiconductor substrate includes a first slit and a second slit, and the first slit and the second slit are both provided with an insulating structure therein; the first notch is located between the deep well and the first doping region, and the second notch is located between the deep well and the second doping region.
In one implementation form of the first aspect, the semiconductor substrate is a P-type substrate, and the deep well is an N-well.
In one implementation form of the first aspect, the semiconductor substrate is an N-type substrate and the deep well is a P-well.
In one implementation of the first aspect, the signal ground is at least one of analog ground and digital ground.
In one implementation form of the first aspect, the integrated circuit further comprises a common ground control circuit, the common ground control circuit comprising a first input terminal; the first input end is electrically connected with the system ground, and the first doped region and the second doped region are electrically connected with the system ground through the common ground control circuit.
In one implementation manner of the first aspect, the common ground control circuit includes a first output terminal and a second output terminal, the first output terminal is electrically connected with the first doped region, and the second output terminal is electrically connected with the second doped region; when the first input end is electrically conducted with the first output end and the second output end, the first doped region and the second doped region are electrically connected with the system ground.
In one implementation form of the first aspect, the common ground control circuit includes a first transistor and a second transistor, a source of the first transistor is electrically connected to the first output terminal, and a source of the second transistor is electrically connected to the second output terminal; the drain of the first transistor is electrically connected to the first input terminal, and the drain of the second transistor is electrically connected to the first input terminal.
In one implementation manner of the first aspect, the common ground control circuit further includes a first resistor, one end of the first resistor is electrically connected to the analog signal power supply, and the other end of the first resistor is electrically connected to the gate of the first transistor and the gate of the second transistor; the first doped region is electrically connected with one of an analog ground and a power ground, and the second doped region is electrically connected with the other of the analog ground and the power ground; when the analog signal power supply outputs the analog signal, the first input end is electrically communicated with the first output end and the second output end.
In a second aspect, an embodiment of the present application provides a consumable chip including an integrated circuit as provided in the first aspect.
In a third aspect, an embodiment of the present application provides an MCU chip, including the integrated circuit provided in the first aspect.
In the present application, the signal ground and the power ground are provided in different regions of the semiconductor substrate isolated by the deep well, and are electrically connected to the system ground GND through the common ground control circuit. When the integrated circuit or the chip does not need a uniform ground signal in operation, the common ground control circuit is closed, the signal ground is separated from the power ground by the deep well, and therefore not only are the potentials of the signal ground and the power ground isolated, but also signal crosstalk between the signal ground and the power ground is avoided. When the integrated circuit or the chip needs a uniform ground signal in operation, the common ground control circuit is conducted, and the signal ground, the power ground and the system ground are in common ground, so that the problem of program operation errors caused by non-uniform ground signals in the operation of the integrated circuit or the chip is solved.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a semiconductor structure of an integrated circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a semiconductor structure of another integrated circuit according to an embodiment of the present disclosure;
fig. 3 is a flowchart illustrating a deep well fabrication process according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a semiconductor structure of yet another integrated circuit according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a semiconductor structure of yet another integrated circuit according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a semiconductor structure of yet another integrated circuit according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a common ground control circuit according to an embodiment of the present disclosure;
fig. 8 is an equivalent circuit schematic diagram of a common ground control circuit according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of an equivalent circuit of another common ground control circuit according to an embodiment of the present application;
FIG. 10 is a schematic diagram of a consumable chip according to an embodiment of the present disclosure;
FIG. 11 is a schematic view of an integrated circuit board in a consumable chip according to an embodiment of the present disclosure
Fig. 12 is a schematic diagram of an MCU chip provided in an embodiment of the present application.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present application, the following detailed descriptions of the embodiments of the present application are provided with reference to the accompanying drawings.
It should be understood that the embodiments described are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terminology used in the embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the examples of this application and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
In the description herein, it is to be understood that the terms "substantially", "approximately", "about", "substantially", and the like, as used in the claims and the examples herein, are intended to be generally accepted as not being precise, within the scope of reasonable process operation or tolerance.
It should be understood that although the terms first, second, etc. may be used in the embodiments of the present application to describe regions, doped regions, etc., these regions, doped regions, etc. should not be limited by these terms. These terms are only used to distinguish one region, doped region, etc. from another. For example, a first region may also be referred to as a second region, and similarly, a second region may also be referred to as a first region without departing from the scope of embodiments of the present application.
The applicant provides a solution to the problems of the prior art through intensive research.
Fig. 1 is a schematic view of a semiconductor structure of an integrated circuit according to an embodiment of the present disclosure, and fig. 2 is a schematic view of a semiconductor structure of another integrated circuit according to an embodiment of the present disclosure.
As shown in fig. 1 and fig. 2, an integrated circuit 001 according to an embodiment of the present invention includes a semiconductor substrate 01, the semiconductor substrate 01 includes a first area AA, a second area BB and a deep well 10, the first area AA includes a first doped region 11, and the second area BB includes a second doped region 12. The first region AA and the second region BB include a plurality of doped regions doped with the same ion. The first doped region 11 is specifically one of a plurality of doped regions in the first area AA, and the second doped region 12 is specifically one of a plurality of doped regions in the second area BB. The deep well 10 is disposed in the semiconductor substrate 01 and extends to the surface of the semiconductor substrate 01. The deep well 10 surrounds the first area AA. The deep well 10 is located between the first area AA and the second area BB, and the deep well 10 surrounds the first area AA and is surrounded by the second area BB.
The first doped region 11 is electrically connected to one of a signal ground SGND and a power ground PGND, and the second doped region 12 is electrically connected to the other of the signal ground SGND and the power ground PGND. That is, the signal ground SGND and the power ground PGND are located in different regions of the semiconductor substrate 01 and are isolated by the deep well 10.
It is understood that, in addition to isolating the potentials inside and outside the deep well 10, the deep well 10 can also avoid the influence of the modules inside the deep well 10 on the electrical signals of the modules outside the deep well 10, and avoid the influence of the modules outside the deep well 10 on the electrical signals of the modules inside the deep well 10.
Generally, a current flowing through the power ground is large, and a current flowing through the signal ground is small. Grounding points with different functions are directly connected together, and a high-power circuit influences a zero potential reference point of a low-power circuit through the grounding line, so that crosstalk between signals of different circuits is caused. In the present application, the signal ground SGND and the power ground PGND are disposed in different regions of the semiconductor substrate 01 isolated by the deep well 10, and not only the potentials of the signal ground SGND and the power ground PGND are isolated, but also signal crosstalk between the signal ground SGND and the power ground PGND, that is, crosstalk between different circuit signals is avoided. Such as interference of a high-power circuit with a zero potential reference point of a low-power circuit through a ground line, signal crosstalk between a high-frequency circuit and a low-frequency circuit, and the like. In addition, in the semiconductor process, a deep well process is used for preparing different doped regions, and the signal ground SGND and the power supply ground PGND are isolated through the deep well, so that an additional process is not needed, the process is simplified, and the cost is saved.
In one implementation manner of the embodiment of the present application, as shown in fig. 1, the first doped region 11 is electrically connected to the signal ground SGND, and the second doped region 12 is electrically connected to the power ground PGND. That is, the signal ground SGND is located in the first region 11 of the semiconductor substrate 01, the power ground PGND is located in the second region 12 of the semiconductor substrate 01, and signal crosstalk between the signal ground SGND and the power ground PGND is avoided while isolating the potentials of the signal ground SGND and the power ground PGND.
In yet another implementation manner of the embodiment of the present application, as shown in fig. 2, the first doped region 11 is electrically connected to a power ground PGND, and the second doped region 12 is electrically connected to a signal ground SGND. That is, the power ground PGND is located in the first region 11 of the semiconductor substrate 01, and the signal ground SGND is located in the second region 12 of the semiconductor substrate 01. It will be appreciated that changes in the signal ground SGND potential can affect the operation of other modules in the second region 12 of the semiconductor substrate 01. The present embodiment avoids the problem of the influence of the power ground PGND on the signal ground SGND potential, thereby avoiding the problem of the influence on the operation of other modules in the second region 12 caused by the change of the signal ground SGND potential.
Fig. 3 is a flowchart illustrating a deep well fabrication process according to an embodiment of the present disclosure.
Referring to fig. 1, in an implementation manner of the embodiment of the present application, the semiconductor substrate 01 is a P-type substrate, and the deep well 10 is a deep N-well. The process for manufacturing the deep N well is briefly described as follows:
as shown in fig. 3, a silicon substrate 30 is provided, and a layer of pad oxide 31 is formed on the surface of the silicon substrate 30 by a wet method; then, using the deep N well mask plate, using the photoresist 32 to expose the region where the deep N well is located; then, high-energy low-concentration N ions are implanted into the exposed region, impurities are implanted to form P-type ions, a deep N well is formed, photoresist 32 is used to expose the region on the two sides of the deep N well, the high-energy low-concentration N ions are implanted into the exposed region, the impurities are implanted to form P-type ions, and the deep N well extends to the surface of the silicon substrate 30. After the deep N well is formed, the fabrication of other portions such as the doped region and the isolation shallow layer is required to be continued, which is not described in detail herein.
It is understood that the P-type semiconductor substrate is isolated from the first region AA and the second region BB by the deep N-well in the present application. The first doped region 11 electrically connected to one of the signal ground SGND and the power ground PGND is located in the first region AA, and the second doped region 12 electrically connected to the other of the signal ground SGND and the power ground PGND is located in the second region BB, that is, the deep N-well isolates the signal ground SGND from the power ground PGND, thereby preventing signal crosstalk between the signal ground SGND and the power ground PGND while isolating potentials of the signal ground SGND and the power ground PGND.
In the present application, the semiconductor substrate 01 may be an N-type substrate, and the deep well may be a deep P-well. That is, the N-type semiconductor substrate is isolated into the first region AA and the second region BB by the deep P-well. Thereby isolating the signal ground SGND from the power ground PGND, and avoiding signal crosstalk between the signal ground SGND and the power ground PGND while isolating the potentials of the signal ground SGND and the power ground PGND.
Referring to fig. 1, the semiconductor substrate 01 further includes a first slit 13 and a second slit 14, and the first slit 13 and the second slit 14 are both provided with an insulating structure therein. In particular, the insulating structure may be a silicon oxide material.
The first slit 13 is located between the deep well 10 and the first doped region 11, and the second slit 14 is located between the deep well 10 and the second doped region 12. That is, the deep well 10 is not electrically connected to the first doping region 11 and is not electrically connected to the second doping region 12.
In the present application, the first slit 13 is provided to avoid the problem of electrical conduction between the first doped region 11 and the deep well 10. The second slits 14 are provided to avoid the problem of electrical conduction between the second doped region 12 and the deep well 10. Therefore, the problem that the normal operation of the integrated circuit 001 is affected by the conduction of the first doped region 11 and the second doped region 12 with the deep well 10 is avoided.
Fig. 4 is a schematic view of a semiconductor structure of another integrated circuit provided in this embodiment, fig. 5 is a schematic view of a semiconductor structure of another integrated circuit provided in this embodiment, and fig. 6 is a schematic view of a semiconductor structure of another integrated circuit provided in this embodiment.
In one embodiment of the present application, the signal ground SGND is at least one of analog ground, digital DGND. That is, the signal ground SGND may be analog AGND, may be digital DGND, or may include analog AGND and digital DGND.
When the signal ground SGND is the analog ground AGND, it can be understood that the first doped region 11 is electrically connected to one of the analog ground AGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the analog ground AGND and the power ground PGND. Note that, in the semiconductor substrate 01, an isolation shallow layer STI is further provided, and the isolation shallow layer STI is filled with an insulating material. The isolation shallow STI is used to isolate different doped regions.
Alternatively, as shown in fig. 4, the first doped region 11 is electrically connected to the power ground PGND, and the second doped region 12 is electrically connected to the analog ground AGND. Since the first doped region 11 is located in the first area AA and the second doped region 12 is located in the second area BB, that is, the power ground PGND is located in the first area AA and the analog ground AGND is located in the second area BB. The signal crosstalk between the power supply ground PGND and the analog ground AGND is avoided, and the problem that the normal operation of other modules in the integrated circuit 001 is affected by the potential change of the analog ground AGND is further avoided.
Alternatively, as shown in fig. 5, the first doped region 11 is electrically connected to the analog ground AGND, and the second doped region 12 is electrically connected to the power ground PGND. That is, the analog ground AGND is located in the first area AA, the power ground PGND is located in the second area BB, and the deep well 10 isolates the analog ground AGND from the power ground PGND, thereby avoiding signal crosstalk between the analog ground AGND and the power ground PGND.
When the signal ground SGND is the digital ground DGND, it can be understood that the first doped region 11 is electrically connected to one of the digital ground DGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the digital ground DGND and the power ground PGND.
Alternatively, as shown in fig. 6, the first doped region 11 is electrically connected to the power ground PGND, and the second doped region 12 is electrically connected to the digital ground DGND. Since the first doped region 11 is located in the first area AA and the second doped region 12 is located in the second area BB, the power ground PGND is located in the first area AA and the digital ground DGND is located in the second area BB. It can be understood that, the power ground PGND is isolated in the first area AA, so that signal crosstalk between the power ground PGND and the digital ground DGND is avoided, and the problem that the power ground PGND affects the zero potential reference point of the digital ground DGND is avoided.
Fig. 7 is a schematic diagram of a common ground control circuit according to an embodiment of the present disclosure.
IN one embodiment of the present application, referring to fig. 4-7, the integrated circuit 001 further includes a common ground control circuit 02, and the common ground control circuit 02 includes a first input terminal IN 1.
The first input terminal IN1 is electrically connected to the system ground GND, and the first doped region 11 and the second doped region 12 can be electrically connected to the system ground GND through the common ground control circuit 02. That is, the signal ground SGND and the power ground PGND are electrically connected to the system ground GND through the common ground control circuit 02. It is understood that the system ground GND is a uniform ground point for the integrated circuit 001.
When the common ground control circuit 02 is turned off, the signal ground SGND and the power ground PGND are located in different regions of the semiconductor substrate 01 and are isolated by the deep well 10, and the signal ground SGND and the power ground PGND do not interfere with each other as independent ground points.
When the common ground control circuit 02 is turned on, the signal ground SGND and the power ground PGND are both electrically connected to the system ground GND. That is, signal ground SGND, power ground PGND, and system ground GND are common.
It is understood that there are some operations that require a uniform ground signal during the operation of the integrated circuit 001, and the non-uniform ground signal may cause a program to run incorrectly. When a uniform ground signal is required during the operation of the integrated circuit 001, the common ground control circuit 02 is turned on, so that the signal ground SGND, the power ground PGND, and the system ground GND are connected to the ground, thereby avoiding a program operation error.
With continued reference to fig. 4-7, in an embodiment of the present application, the common ground control circuit 02 includes a first output terminal OUT1 and a second output terminal OUT2, the first output terminal OUT1 is electrically connected to the first doped region 11, and the second output terminal OUT2 is electrically connected to the second doped region 12. When the first input terminal IN1 is electrically conducted to the first output terminal OUT1 and the second output terminal OUT2, the first doped region 11 and the second doped region 12 are electrically connected to the system ground GND.
It should be noted that, while the first input terminal IN1 is turned on with the first output terminal OUT1, the first input terminal IN1 is turned on with the second output terminal OUT 2. The first doped region 11 and the second doped region 12 are electrically connected to the system ground GND at the same time. That is, the signal ground SGND, the power ground PGND, and the system ground GND are common. When a uniform ground signal is required during the operation of the integrated circuit 001, the signal ground SGND, the power ground PGND, and the system ground GND are connected to the same ground, so that a program operation error can be avoided.
Fig. 8 is an equivalent circuit schematic diagram of a common ground control circuit according to an embodiment of the present disclosure.
As shown IN fig. 8, IN one embodiment of the present application, the common ground control circuit 02 includes a first transistor 21 and a second transistor 22, a source of the first transistor 21 is electrically connected to the first output terminal OUT1, a source of the second transistor 22 is electrically connected to the second output terminal OUT2, a drain of the first transistor 21 is electrically connected to the first input terminal IN1, and a drain of the second transistor 22 is electrically connected to the first input terminal IN 1.
It is understood that the source of the first transistor 21 is electrically connected to the first doped region 11, the source of the second transistor 22 is electrically connected to the second doped region 12, the drain of the first transistor 21 is electrically connected to the system ground GND, and the drain of the second transistor 22 is electrically connected to the system ground GND. That is, the signal ground SGND and the power ground PGND are electrically connected to the system ground GND through the first transistor 21 and the second transistor 22. When the first transistor 21 is turned on, one of the signal ground SGND and the power ground PGND is turned on with the system ground GND. When the second transistor 22 is turned on, the other one of the signal ground SGND and the power supply ground PGND is turned on with the system ground GND.
Note that the first transistor 21 and the second transistor 22 are turned on and off at the same time. When the first transistor 21 and the second transistor 22 are turned on simultaneously, the signal ground SGND, the power ground PGND, and the system ground GND are grounded, so that the integrated circuit 001 does not have a program operation error when a uniform ground signal is required to operate. When the first transistor 21 and the second transistor 22 are turned off simultaneously, the signal ground SGND and the power ground PGND are located in different regions of the semiconductor substrate 01 and are isolated by the deep well 10, and the signal ground SGND and the power ground PGND do not interfere with each other as independent ground points.
Fig. 9 is an equivalent circuit schematic diagram of another common ground control circuit provided in the embodiment of the present application.
In an embodiment of the present application, please refer to fig. 4, fig. 5, and fig. 9, the common ground control circuit 02 further includes a first resistor 23, one end of the first resistor 23 is electrically connected to the analog signal power source VCC, and the other end of the first resistor 23 is electrically connected to the gate of the first transistor 21 and the gate of the second transistor 22. That is, the gate of the first transistor 21 and the gate of the second transistor 22 are both electrically connected to the same end of the first resistor 23. It is understood that the on-off control signals of the first transistor 21 and the second transistor 22 are the same, that is, the first transistor 21 and the second transistor 22 are turned on and off simultaneously.
The first doped region 11 is electrically connected to one of the analog ground AGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the analog ground AGND and the power ground PGND. It can be understood that since the first doped region 11 is located in the first area AA of the semiconductor substrate 01, the second doped region 12 is located in the second area BB of the semiconductor substrate 01, and the first area AA is surrounded by the deep well 10. The analog ground AGND and the power ground PGND are located in different regions of the semiconductor substrate 01 and are isolated by the deep well 10.
In one implementation manner of the embodiment of the present application, the first doped region 11 is electrically connected to the power ground PGND, and the second doped region 12 is electrically connected to the analog ground AGND. That is, the power ground PGND is located in the first area AA, and the analog ground AGND is located in the second area BB.
In another implementation manner of the embodiment of the present application, the first doped region 11 is electrically connected to the analog ground AGND, and the second doped region 12 is electrically connected to the power ground PGND. That is, the analog ground AGND is located in the first area AA, and the power ground PGND is located in the second area BB.
When the analog signal power VCC outputs an analog signal, the first input terminal IN1 is electrically conducted to the first output terminal OUT1 and the second output terminal OUT 2. It is understood that the analog signal output by the analog signal power supply is a control signal of the first transistor 21 and the second transistor 22. Since the first output terminal IN1 is electrically connected to the system ground GND, the first output terminal OUT1 is electrically connected to the first doped region 11, and the second output terminal OUT2 is electrically connected to the second doped region 12. When the analog signal power source outputs the analog signal, the first doped region 11 and the second doped region 12 are electrically connected to the system ground GND, i.e., the analog ground AGND, the power ground PGND, and the system ground GND are common.
In the embodiment of the present application, when the analog signal power supply VCC outputs an analog signal, the gate of the first transistor 21 and the gate of the second transistor 22 receive the analog signal through the first resistor 23, that is, the first transistor 21 and the second transistor 22 receive a control signal. The source and drain of the first transistor 21 are turned on and the source and drain of the second transistor 22 are turned on. Since the source of the first transistor 21 is electrically connected to the first doped region 11, the drain of the first transistor 21 is electrically connected to the system ground GND; the source of the second transistor 22 is electrically connected to the second doped region 12, and the drain of the second transistor 22 is electrically connected to the system ground GND. The first doped region 11 and the second doped region 12 are electrically connected to the system ground GND. Since the first doped region 11 is electrically connected to one of the analog ground AGND and the power ground PGND, and the second doped region 12 is electrically connected to the other of the analog ground AGND and the power ground PGND, the analog ground AGND, the power ground PGND, and the system ground GND are common. That is, when the analog signal power supply outputs the analog signal, the analog ground AGND, the power ground PGND, and the system ground GND are grounded, so as to avoid a program operation error when the integrated circuit 001 needs a uniform ground signal to operate.
In addition, referring to fig. 6 and 8, when the signal module circuit is a digital circuit, one end of the first resistor 23 is electrically connected to the digital signal power source VSS, and the other end of the first resistor 23 is electrically connected to the gate of the first transistor 21 and the gate of the second transistor 22. The first doped region 11 is electrically connected to one of a digital ground DGND and a power ground PGND, and the second doped region 12 is electrically connected to the other of the digital ground AGND and the power ground PGND. When the digital signal power supply VSS outputs a digital signal, the first input terminal IN1 is electrically conducted to the first output terminal OUT1 and the second output terminal OUT 2.
In the integrated circuit 001 provided by the present application, the signal ground SGND and the power supply ground PGND are provided in different regions of the semiconductor substrate 01 isolated by the deep well 10, and are electrically connected to the system ground GND through the common ground control circuit 02. When the integrated circuit 001 does not need a uniform ground signal during operation, the common ground control circuit 02 is turned off, and the signal ground SGND is isolated from the power ground PGND by the deep well 10, so that not only the potentials of the signal ground SGND and the power ground PGND are isolated, but also signal crosstalk between the signal ground SGND and the power ground PGND is avoided. When the integrated circuit 001 needs a uniform ground signal during operation, the common ground control circuit 02 is turned on, and the signal ground SGND, the power ground PGND and the system ground GND are connected to the ground, so that the problem of program operation errors caused by non-uniform ground signals during operation of the integrated circuit 001 is solved.
Fig. 10 is a schematic view of a consumable chip provided in an embodiment of the present application, and fig. 11 is a schematic view of an integrated circuit board in a consumable chip provided in an embodiment of the present application.
The present embodiment provides a consumable chip 002, as shown in fig. 10, including an integrated circuit 001 according to any one of the above embodiments. The consumable chip 002 includes a printer consumable chip.
In one embodiment of the present application, as shown in fig. 11, the consumable chip 002 includes an integrated circuit board 2A, the integrated circuit board 2A includes a first interface C1, a second interface C2, a third interface C3, a fourth interface C4 and a fifth interface C5 for communicating with a host, and the first interface C1, the second interface C2, the third interface C3, the fourth interface C4 and the fifth interface C5 have an electrical connection relationship therebetween.
Wherein, the first interface C1 provides a ground signal for the consumable chip 002; it is understood that the first interface C1 is the system ground GND of the consumable chip 002. The second interface C2 provides the supply voltage signal VDD for the consumable chip 002; the third interface C3 provides a chip select signal CS for the consumable chip 002; the fourth interface C4 provides the control signal SCL for the consumable chip 002; the fifth interface C5 provides the data signal SDA to the consumable chip 002. It should be noted that the integrated circuit board 2A may further include a first sensor contact point H1, a second sensor contact point H2, a first short detection pin S1 and a second short detection pin S2.
It is understood that the consumable chip 002 includes digital signals, power signals, and analog signals. If the digital DGND, the power supply ground PGND and the analog ground AGND are all directly connected to the first interface C1, crosstalk of different signals occurs, the accuracy of the analog circuit is affected, and the difficulty of EMC experiment processing of the circuit is increased.
In the consumable chip 002 provided in the present application, the signal ground SGND and the power supply ground PGND are provided in different regions of the semiconductor substrate 01 isolated by the deep well 10, and can be electrically connected to the system ground GND through the common ground control circuit 02. When the consumable chip 002 does not need a uniform ground signal during operation, the common ground control circuit 02 is turned off, and the signal ground SGND and the power ground PGND are isolated by the deep well 10, so that not only the potentials of the signal ground SGND and the power ground PGND are isolated, but also the signal crosstalk between the signal ground SGND and the power ground PGND is avoided. When the consumable chip 002 needs a uniform ground signal during operation, the common ground control circuit 02 is turned on, and the signal ground SGND, the power ground PGND and the system ground GND are connected to the ground, so that the problem of program operation errors caused by non-uniform ground signals during operation of the consumable chip 002 is solved. Wherein signal ground SGND includes at least one of digitally DGND and analog ground AGND.
Fig. 12 is a schematic diagram of an MCU chip provided in an embodiment of the present application.
An embodiment of the present application provides a Micro Controller Unit (MCU) chip 003, as shown in fig. 12, including an integrated circuit 001 as provided in any of the above embodiments. The MCU chip comprises at least one of a controller for a remote controller, a controller for a motor, a controller for a cassette recorder core and a controller for a robot arm.
In the MCU chip 003 provided in the present application, the signal ground SGND and the power supply ground PGND are provided in different regions of the semiconductor substrate 01 isolated by the deep well 10, and are electrically connected to the system ground GND through the common ground control circuit 02. When the MCU chip 003 does not need a uniform ground signal during operation, the common ground control circuit 02 is turned off, and the signal ground SGND and the power ground PGND are isolated by the deep well 10, thereby not only isolating the potentials of the signal ground SGND and the power ground PGND, but also avoiding signal crosstalk between the signal ground SGND and the power ground PGND. When the MCU chip 003 needs a uniform ground signal during operation, the common ground control circuit 02 is turned on, and the signal ground SGND, the power ground PGND, and the system ground GND are connected to ground, thereby avoiding a problem of program operation error due to non-uniform ground signals during operation of the MCU chip 003.
It will be appreciated that when a measuring device has a plurality of measured values to be output by the current signal, then the measuring device includes a plurality of current signal output circuits, and the plurality of current signal output circuits are common to ground. In one embodiment of the present application, the MCU chip 003 is applied to a measurement apparatus including a multi-path current signal output circuit.
The MCU chip 003 includes a sampling module, a control module, and a Pulse Width Modulation (PWM) module.
The sampling module is used for filtering the input voltage signal and transmitting the filtered input voltage signal to the control module; the input voltage signal may be a signal received from an analog signal supply VCC.
The control module is used for calculating the input signal transmitted from the sampling module and obtaining a control value; and converts the received measurement value into a control value of the PWM module. The control module may vary the PWM duty cycle.
The PWM module is used for generating a PWM voltage signal corresponding to the control value of the MCU chip 003, and then converting the voltage signal into a current signal for output.
In the embodiment of the present application, the MCU chip can realize N current signal outputs, and the output principles of the 1 st current signal output to the nth current signal output are the same, where N may be any value greater than or equal to 2, for example, N is 2 or N is 6.
Wherein the PWM module includes a PWM generator. In this embodiment, a Timer _ B may be used as the PWM generator. It can be understood that one pin of the single chip microcomputer can output one path of PWM signals. In this embodiment, one pin of the single chip outputs a first PWM signal PWM1, the other pin of the single chip outputs a second PWM signal PWM2, and the output principles of the first PWM signal PWM1 and the second PWM signal PWM2 are the same. Taking the first PWM signal PWM1 as an example, the PWM1 is filtered by a two-stage capacitor-resistor circuit (RC circuit), and the filtered PWM1 is converted into a dc voltage signal and then converted into a current signal for output.
In the present application, the power ground port of the MCU chip 003 is the power ground PGND, and the ground port of the PWM module is the analog ground AGND. The analog ground AGND and the power supply ground PGND are disposed in different regions of the semiconductor substrate 01 isolated by the deep well 10, and are electrically connected through the common ground control circuit 02. When the MCU chip 003 does not need a uniform ground signal during operation, the common ground control circuit 02 is turned off, and the analog ground AGND and the power ground PGND are isolated by the deep well 10, thereby not only isolating the potentials of the analog ground AGND and the power ground PGND, but also avoiding signal crosstalk between the analog ground AGND and the power ground PGND. When the MCU chip 003 needs a uniform ground signal during operation, the common ground control circuit 02 is turned on, and the analog ground AGND and the power supply ground PGND are in common ground, so that the problem of program operation errors caused by non-uniform ground signals during the operation of the MCU chip 003 is avoided.
The above description is only exemplary of the present application and should not be taken as limiting the present application, as any modification, equivalent replacement, or improvement made within the spirit and principle of the present application should be included in the scope of protection of the present application.
Claims (11)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111136265.0A CN113745191A (en) | 2021-09-27 | 2021-09-27 | Integrated circuit, consumable chip and MCU chip |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111136265.0A CN113745191A (en) | 2021-09-27 | 2021-09-27 | Integrated circuit, consumable chip and MCU chip |
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| CN113745191A true CN113745191A (en) | 2021-12-03 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221952A (en) * | 2007-05-11 | 2008-07-16 | 崇贸科技股份有限公司 | Semiconductor structure for protecting an internal integrated circuit and its manufacturing method |
| US20120002821A1 (en) * | 2010-07-01 | 2012-01-05 | Conexant Systems, Inc. | Grounding switch method and apparatus |
| CN216213430U (en) * | 2021-09-27 | 2022-04-05 | 珠海极海半导体有限公司 | Integrated circuit, consumable chip and MCU chip |
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2021
- 2021-09-27 CN CN202111136265.0A patent/CN113745191A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101221952A (en) * | 2007-05-11 | 2008-07-16 | 崇贸科技股份有限公司 | Semiconductor structure for protecting an internal integrated circuit and its manufacturing method |
| US20120002821A1 (en) * | 2010-07-01 | 2012-01-05 | Conexant Systems, Inc. | Grounding switch method and apparatus |
| CN216213430U (en) * | 2021-09-27 | 2022-04-05 | 珠海极海半导体有限公司 | Integrated circuit, consumable chip and MCU chip |
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