CN113740717B - A method and circuit for measuring the holding time of a timing unit - Google Patents
A method and circuit for measuring the holding time of a timing unit Download PDFInfo
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- CN113740717B CN113740717B CN202010476276.2A CN202010476276A CN113740717B CN 113740717 B CN113740717 B CN 113740717B CN 202010476276 A CN202010476276 A CN 202010476276A CN 113740717 B CN113740717 B CN 113740717B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31702—Testing digital circuits including elements other than semiconductor transistors, e.g. biochips, nanofabrics, mems, chips with magnetic elements
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31725—Timing aspects, e.g. clock distribution, skew, propagation delay
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
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Abstract
The application provides a method and a circuit for measuring the retention time of a time sequence unit. The method is suitable for a measuring circuit of the holding time of a time sequence unit, the circuit comprises a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a first clock phase controller, a second clock phase controller, a data signal transmitting module, a clock signal transmitting module, a time sequence unit to be measured and a control module, the method comprises the steps of respectively determining a first period value, a second period value and a third period value of a clock signal, wherein the first period value is a critical period when the time sequence unit to be measured correctly receives the clock signal in a first test path, the second period value is a critical period when the delay detecting module correctly receives the clock signal in a second test path, the third period value is a critical period when the delay detecting module correctly receives the clock signal in a third test path, and the holding time of the time sequence unit is determined according to the first period value, the second period value and the third period value.
Description
Technical Field
The present application relates to the field of digital integrated circuit measurement technology, and for example, to a method and a circuit for measuring retention time of a sequential unit.
Background
The retention time of the time sequence unit is one of important factors influencing stable transmission of signal data, and when the design of the time sequence unit library is carried out, the accurate measurement of the retention time of the time sequence unit directly influences the performance, production and manufacture of the chip. The prior art generally uses a clock phase fine adjustment method or equivalently measures the hold time as a minimum measurement scale by means of a plurality of buffers. However, these methods suffer from a number of disadvantages, such as limited by small clock phase adjustment range and buffer delay, variability in the measured clock and data paths, and more pronounced behavior at different test voltages, which can result in very large measurement errors in the timing cell hold time.
Disclosure of Invention
In view of this, the embodiment of the application provides a method and a circuit for measuring the retention time of a time sequence unit, so as to improve the measurement accuracy of the retention time of the time sequence unit and meet the performance requirement of a chip.
The embodiment of the application provides a measuring circuit for time sequence unit holding time, which comprises a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a first clock phase controller, a second clock phase controller, a data signal transmission module, a clock signal transmission module, a time sequence unit to be measured and a control module;
The clock signal generation module is respectively and electrically connected with the first selection module, the delay detection module and the control module, the delay detection module is respectively and electrically connected with the first selection module, the second selection module and the control module, the first selection module is respectively and electrically connected with the control module, the first clock phase controller and the second clock phase controller, the second selection module is respectively and electrically connected with the control module, the data signal transmission module and the clock signal transmission module, the first clock phase controller is respectively and electrically connected with the control module and the data signal transmission module, the second clock phase controller is respectively and electrically connected with the control module and the clock signal transmission module, the data signal transmission module is respectively and electrically connected with the time sequence unit to be tested and the control module, the clock signal transmission module is respectively and electrically connected with the time sequence unit to be tested and the control module, and the time sequence unit to be tested is electrically connected with the control module;
the first clock phase controller is used for outputting a first pulse signal and providing a clock signal for the data signal transmission module, and the second clock phase controller is used for outputting a second pulse signal and providing a clock signal for the clock signal transmission module;
The control module is configured to control the first selection module and the second selection module to form a first test path, a second test path and a third test path, so as to determine a holding time of a timing unit based on the first test path, the second test path and the third test path, where the first test path is composed of the clock signal generating module, the first clock phase controller, the second clock phase controller, the data signal transmitting module, the clock signal transmitting module, a timing unit to be tested and the control module, the second test path is composed of the clock signal generating module, the delay detecting module, the first clock phase controller, the data signal transmitting module and the control module, and the third test path is composed of the clock signal generating module, the delay detecting module, the second clock phase controller, the clock signal transmitting module and the control module.
The embodiment of the application also provides a method for measuring the holding time of the time sequence unit, which is suitable for the measuring circuit for the holding time of the time sequence unit, wherein the measuring circuit comprises a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a first clock phase controller, a second clock phase controller, a data signal transmitting module, a clock signal transmitting module, a time sequence unit to be measured and a control module, the control module controls the first selecting module and the second selecting module to form a first test path, a second test path and a third test path, the first test path consists of the clock signal generating module, the first clock phase controller, the second clock phase controller, the data signal transmitting module, the time sequence unit to be measured and the control module, the second test path consists of the clock signal generating module, the delay detecting module, the first clock phase controller, the data signal transmitting module and the control module, and the third test path consists of the clock signal generating module, the delay detecting module, the second clock phase controller and the clock signal transmitting module;
the method comprises the following steps:
respectively determining a first period value, a second period value and a third period value of a clock signal, wherein the first period value is a critical period for the time sequence unit to be tested to correctly receive the clock signal under the first test path, the second period value is a critical period for the delay detection module to correctly receive the clock signal under the second test path, and the third period value is a critical period for the delay detection module to correctly receive the clock signal under the third test path;
And determining the holding time of the time sequence unit according to the first period value, the second period value and the third period value.
With respect to the above embodiments and other aspects of the application and implementations thereof, further description is provided in the accompanying drawings, detailed description and claims.
Drawings
FIG. 1 is a schematic diagram of a prior art timing cell retention time;
FIG. 2 is a schematic diagram of a timing unit hold time measurement circuit according to an embodiment of the present application;
FIG. 3 is a timing diagram of a timing unit hold time measurement signal according to an embodiment of the present application;
FIG. 4 is a schematic diagram of another embodiment of a timing unit hold time measurement circuit;
FIG. 5 is a flowchart of a method for measuring retention time of a timing unit according to an embodiment of the present application;
FIG. 6 is a flowchart of a method for determining a period value of a clock signal according to an embodiment of the present application;
fig. 7 is a schematic diagram of measurement of a period value of a clock signal according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will be described below with reference to the accompanying drawings. Embodiments of the application and features of the embodiments may be combined with one another arbitrarily without conflict.
Fig. 1 is a schematic diagram of a prior art timing cell retention time. Referring to fig. 1, a hold time (Th: hold time) of a timing unit (e.g., a flip-flop) refers to a time required for a data signal to remain stable after a rising edge of a clock signal of the timing unit. If the hold time Th, which is the minimum settling time, is insufficient, the data will not be read efficiently and converted to output.
In the prior art, the retention time of the time sequence unit is obtained by simulation by a spice tool when designing a unit library, but the retention time is only a theoretical calculation value, if the theoretical calculation value is larger than the actual value in a chip, unnecessary difficulties are aggravated for the back-end time sequence convergence, and if the theoretical calculation value is smaller, the time sequence problem can occur after the chip is produced, the chip cannot reach the actual working frequency, so that the value retention consistency between the theory and the actual retention time is very important after the design of the time sequence unit library is completed. In order to ensure that the actual value of the hold time remains consistent with the theoretical value, measurement verification of the hold time is often required.
In one prior art scheme, a method for measuring hold time based on fine adjustment of clock phase is proposed, for example, by fine adjustment of clock phase, two clocks with phase deviation after fine adjustment are respectively used as clocks and data to be sent to a time sequence unit to be measured to identify hold violation (hold time timing violation), so as to judge the hold time of the time sequence unit, but the measurement accuracy is limited by the minimum step of adjustable clock phase, and the clocks have different transmission paths, and under different test voltages, the different performances are different, and the hold time error is very large.
In another prior art scheme, a buffer with smaller delay is used as the minimum measurement scale, and different numbers of buffers are constructed for clocks and data paths of a time sequence unit, so that the number of the buffers with different numbers of buffers is judged to be equivalent to the number of the minimum measurement scale buffers, the accuracy of the method is also limited by the delay of the buffers as the minimum measurement scale, and the measured clocks and the data paths have different differences, and the difference is obviously increased under different voltages, so that the error of the measurement result is very large.
In the prior art, the timing unit hold time is typically measured independent of the period or frequency of the clock signal.
In view of this, the present application provides a measurement circuit and a measurement method for a time sequence unit hold time, wherein a control module controls a first clock phase controller to output a first pulse signal and provide a clock signal for a data signal transmission module, and controls a second clock phase controller to output a second pulse signal and provide a clock signal for the clock signal transmission module, so that the measurement of the time sequence unit hold time is related to the period or frequency of the clock signal. And then the first selection module and the second selection module are controlled by the control module to form a first test path, a second test path and a third test path, the critical period (marked as a first period value) of the clock signal, which is correctly received by the time sequence unit to be tested, under the first test path, is respectively determined, the critical period (marked as a second period value) of the clock signal, which is correctly received by the delay detection module, under the second test path, is respectively determined, the critical period (marked as a third period value) of the clock signal, which is correctly received by the delay detection module, under the third test path, and finally the holding time of the time sequence unit is determined according to the first period value, the second period value and the third period value. Therefore, the first clock phase controller and the second clock phase controller enable the hold time violation test under the first test path to be related to the period or the frequency of the clock signal (namely, related to the first period value), so that the determination of the hold time of the time sequence unit is only related to the first period value, the second period value and the third period value, the problems that the hold time is limited by the clock phase adjustment range and the buffer delay are avoided, and the measurement error is large due to the fact that different test voltage differences are large are avoided, and the measurement precision is improved.
In an implementation manner, fig. 2 is a schematic structural diagram of a measurement circuit for a retention time of a timing unit according to an embodiment of the present application, and referring to fig. 2, the measurement circuit includes a clock signal generating module 110, a first selecting module 120, a second selecting module 130, a delay detecting module 140, a first clock phase controller 10, a second clock phase controller 20, a data signal transmitting module 150, a clock signal transmitting module 160, a timing unit to be tested 170, and a control module 180;
The clock signal generating module 110 is electrically connected with the first selecting module 120, the delay detecting module 140 and the control module 180 respectively, the delay detecting module 140 is electrically connected with the first selecting module 120, the second selecting module 130 and the control module 180 respectively, the first selecting module 120 is electrically connected with the control module 180, the first clock phase controller 10 and the second clock phase controller 20 respectively, the second selecting module 130 is electrically connected with the control module 180, the data signal transmission module 150 and the clock signal transmission module 160 respectively, the first clock phase controller 10 is electrically connected with the control module 180 and the data signal transmission module 150 respectively, the second clock phase controller 20 is electrically connected with the control module 180 and the clock signal transmission module 160 respectively, the data signal transmission module 150 is electrically connected with the timing unit to be tested 170 and the control module 180 respectively, the clock signal transmission module 160 is electrically connected with the timing unit to be tested 170 and the control module 180 respectively, and the timing unit to be tested 170 is electrically connected with the control module 180;
The first clock phase controller 10 is configured to output a first pulse signal and provide a clock signal to the data signal transmission module 150, and the second clock phase controller 20 is configured to output a second pulse signal and provide a clock signal to the clock signal transmission module 160;
The control module 180 is configured to control the first selection module 120 and the second selection module 130 to form a first test path, a second test path, and a third test path, so as to determine a hold time of the timing unit based on the first test path, the second test path, and the third test path, wherein the first test path is composed of the clock signal generation module 110, the first clock phase controller 10, the second clock phase controller 20, the data signal transmission module 150, the clock signal transmission module 160, the timing unit under test 170, and the control module 180, the second test path is composed of the clock signal generation module 110, the delay detection module 140, the first clock phase controller 10, the data signal transmission module 150, and the control module 180, and the third test path is composed of the clock signal generation module 110, the delay detection module 140, the second clock phase controller 20, the clock signal transmission module 160, and the control module 180.
In an embodiment, fig. 3 is a timing chart of a timing unit hold time measurement signal according to the embodiment of the present application, referring to fig. 3, the clock signal sent by the clock signal generating module 110 is a pulse signal having two rising edges, such as a p1 curve in fig. 3, having one rising edge at time T0 and T2, and having one falling edge at time T1 and T3, respectively, the pulse signal having two rising edges is input to the first clock phase controller 10 and the second clock phase controller 20, respectively, and is output as a first rising edge truncated by the first clock phase controller 10, and only a first pulse signal having a second rising edge that can pass, such as a p2 curve in fig. 3, is output as a second rising edge truncated by the second clock phase controller 20, and only the first rising edge can pass, such as a p3 curve in fig. 3, and the second pulse signal has a rising edge at time T0. In fig. 3, a curve p4 is a timing chart of the data signal output from the output end of the second transmitting register 151, and a curve p5 is a timing chart of the signal output from the output end of the timing unit to be tested. The first pulse signal may provide a clock signal to the data signal transmission module 150, and the second pulse signal may provide a clock signal to the clock signal transmission module 160.
In an embodiment, the first selection module 120 is configured to control one of the clock signal generation module 110 and the delay detection module 140 to be respectively connected to the first clock phase controller 10 and the second clock phase controller 20. The second selection module 130 is used to control one of the data signal transmission module 150 and the clock signal transmission module 160 to be turned on with the delay detection module 140. For example, when the control module 180 controls the first selection module 120 to control the clock signal generation module 110 to be respectively connected to the first clock phase controller 10 and the second clock phase controller 20, the test circuit enters a critical point test mode of the retention time of the timing unit under test, that is, a first test path is formed by the clock signal generation module 110, the first clock phase controller 10, the data signal transmission module 150, the clock signal transmission module 160, the second clock phase controller 20, the timing unit under test 170 and the control module 180.
When the control module 180 controls the first selection module 120 to control the delay detection module 140 to be respectively connected to the first clock phase controller 10 and the second clock phase controller 20, controls the second selection module 130 to control one of the data signal transmission module 150 and the clock signal transmission module 160 to be connected to the delay detection module 140, so that the test circuit enters a delay comparison mode of a clock signal transmission path and a data signal transmission path, wherein the data signal transmission path is a second test path formed by the clock signal generation module 110, the delay detection module 140, the first clock phase controller 10, the data signal transmission module 150 and the control module 180, and the clock signal transmission path is a third test path formed by the clock signal generation module 110, the delay detection module 140, the second clock phase controller 20, the clock signal transmission module 160 and the control module 180.
In an embodiment, fig. 4 is a schematic diagram of a structure of another timing unit hold time measurement circuit provided in an embodiment of the present application, referring to fig. 4, a clock signal generating module 110 includes a clock modulating unit 111 and a clock pulse control unit 112, the clock modulating unit 111 is electrically connected to the clock pulse control unit 112, the clock pulse control unit 112 is electrically connected to the delay detecting module 140 and the first input terminal A1 of the first selecting module 120, and the control module 180 is electrically connected to the clock modulating unit 111 and the clock pulse control unit 112.
In an embodiment, the clock frequency modulation unit 111 may be a PLL (Phase Locked Loop ) used as a clock source, and has high clock frequency accuracy and stability, small jitter, and fine frequency adjustment. The clock control unit 112 may be an OCC circuit (on-chip-clock) for outputting a clock signal.
In an embodiment, referring to fig. 4, the delay detection module 140 includes a first transmitting register 141 and a receiving register 142, wherein a first input end of the first transmitting register 141 is electrically connected to the clock signal generating module 110, a second input end of the first transmitting register 141 inputs the external data signal data1, an output end of the first transmitting register 141 is electrically connected to the second input end A2 of the first selecting module 120, a first input end of the receiving register 142 is electrically connected to the clock signal generating module 110, a second input end of the receiving register 142 is electrically connected to the output end of the second selecting module 130, and an output end of the receiving register 142 is electrically connected to the control module 180.
In an embodiment, the first transmitting register 141 is used for testing the start point of data signal transmission of the circuit under the second test path and the third test path, and the receiving register 142 is used for testing the end point of data signal transmission of the circuit under the second test path and the third test path. For example, under the second test path, the control module 180 controls the second input terminal A2 of the first selection module 120 to be turned on, i.e., the output terminal of the first transmitting register 141 of the delay detection module is respectively turned on with the first clock phase controller 10 and the second clock phase controller 20, while the control module 180 also controls the second input terminal B2 of the second selection module 130 to be turned on with the receiving register 142 of the delay detection module 140, i.e., the second test path composed of the clock signal generating module 110, the first transmitting register 141, the first clock phase controller 10, the data signal transmitting module 150, the receiving register 142 and the control module 180 is formed. When testing in the second test path, the first input end of the first transmitting register 141 inputs the clock signal output by the clock signal generating module 110, the second input end of the first transmitting register 141 inputs the external data signal data1, the external data signal data1 is output by the first transmitting register 141, and finally, the external data signal data1 is transmitted to the receiving register 142 through the data signal transmitting module 150.
Under the third test path, the control module 180 controls the second input terminal A2 of the first selection module 120 to be turned on, i.e., the output terminal of the first transmitting register 141 of the delay detection module 140 is respectively turned on with the first clock phase controller 10 and the second clock phase controller 20, while the control module 180 also controls the first input terminal B1 of the second selection module 130 to be turned on with the receiving register 142 of the delay detection module 140, i.e., a third test path composed of the clock signal generating module 110, the first transmitting register 141, the second clock phase controller 20, the clock signal transmitting module 160, the receiving register 142 and the control module 180 is formed. When testing in the third test path, the first input end of the first transmitting register 141 inputs the clock signal output by the clock signal generating module 110, the second input end of the first transmitting register 141 inputs the external data signal data1, the external data signal data1 is output by the first transmitting register 141, and finally, the external data signal data1 is transmitted to the receiving register 142 through the clock signal transmitting module 160.
In an embodiment, referring to fig. 4, the data signal transmission module 150 includes a second transmission register 151, a first input terminal of the second transmission register 151 is electrically connected to the first clock phase controller 10, a second input terminal of the second transmission register 151 inputs the external data signal data1, and an output terminal of the second transmission register 151 is electrically connected to the second input terminal of the second selection module 130 and the second input terminal of the timing unit under test 170, respectively.
In an embodiment, the second input terminal of the second transmitting register 151 inputs the external data signal data1 for providing the data signal for the first test path. For example, under the first test path, the control module 180 controls the first input terminal A1 of the first selection module 120 to be turned on, that is, the output terminal of the signal generating module 110 is respectively turned on with the first clock phase controller 10 and the second clock phase controller 20, so as to form a first test path composed of the clock signal generating module 110, the first clock phase controller 10, the data signal transmission module 150, the second clock phase controller 20, the clock signal transmission module 160, the timing unit under test 170 and the control module 180. When testing in the first test path, the first input end of the second transmitting register 151 inputs the first pulse signal output by the first clock phase controller 10, the first pulse signal provides a clock signal for the first test path, the second input end of the second transmitting register 151 inputs the external data signal data1, and the external data signal data1 is output by the second transmitting register 151 and then is transmitted to the timing unit to be tested 170.
In an embodiment, referring to fig. 4, the reset terminal of the second transmitting register 151, the reset terminal of the first transmitting register 141, the reset terminal of the receiving register 142, and the reset terminal of the timing unit under test 170 are electrically connected to the control module 180, and the reset and clear functions of the second transmitting register 151, the first transmitting register 141, the receiving register 142, and the timing unit under test 170 can be controlled by the control module 180.
In an embodiment, referring to fig. 4, the clock signal transmission module 160 includes at least one first buffer module b1, an input terminal of the first buffer module b1 is electrically connected to the second clock phase controller 20, and an output terminal of the first buffer module b1 is electrically connected to a first input terminal of the second selection module 130 and a first input terminal of the timing unit under test 170, respectively.
In an embodiment, the first buffer module b1 forms a clock signal transmission path, and the first buffer module b1 is used to adjust the delay time of the clock signal transmission module 160. It should be noted that, the data signal transmission module 150 may also include a first buffer module b1, a data signal transmission path may be formed by the second sending register 151 and the first buffer module b1, the number of the first buffer modules b1 in the data signal transmission path may include a plurality of the data signal transmission paths, the number of the first buffer modules b1 in the clock signal transmission path may also include a plurality of the data signal transmission paths, the specific number of the data signal transmission modules may be set according to the actual test requirement, and the specific number is not limited herein.
In an embodiment, the first test path is formed when the control module 180 controls the first input terminal A1 of the first selection module 120 to be closed and the second input terminal A2 to be opened, and the first input terminal B1 and the second input terminal B2 of the second selection module 130 to be opened, the second test path is formed when the control module 180 controls the first input terminal A1 of the first selection module 120 to be opened and the second input terminal A2 to be closed and the first input terminal B1 of the second selection module 130 to be opened and the second input terminal B2 to be closed, and the third test path is formed when the control module 180 controls the first input terminal A1 of the first selection module 120 to be opened and the second input terminal A2 to be closed and the first input terminal B1 of the second selection module 130 to be opened.
In an embodiment, when the control module 180 controls the first input terminal A1 of the first selection module 120 to be closed and the second input terminal A2 to be opened, and the first input terminal B1 and the second input terminal B2 of the second selection module 130 to be both opened, that is, the delay detection module is disconnected from the first clock phase controller 10 and the second clock phase controller 20, the output terminal of the signal generation module 110 is respectively connected to the first clock phase controller 10 and the second clock phase controller 20, so as to form a first test path composed of the clock signal generation module 110, the first clock phase controller 10, the data signal transmission module 150 (including the data signal transmission path formed by the second transmission register 151), the second clock phase controller 20, the clock signal transmission module 160 (including the clock signal transmission path formed by the first buffer module B1), the timing unit under test 170 and the control module 180. In the first test path, the data signal transmission path has a fixed delay, the delay value is denoted as t_data, and the clock signal transmission path also has a fixed delay, the delay value is denoted as t_c_lkk. When testing in the first test path, the signal generating module 110 outputs pulse signals with two rising edges, the pulse signals are respectively input to the first clock phase controller 10 and the second clock phase controller 20, the first pulse signal is output through the first clock phase controller 10, the second pulse signal is output through the second clock phase controller 20, the first pulse signal is used as the clock signal of the second transmitting register 151, the first pulse signal input at the first input end of the second transmitting register 151 is shown as a p2 curve in fig. 3, the second pulse signal is output to the first input end (i.e. the clock end) of the timing unit under test 170 through the first buffer module b1, the second pulse signal input to the first input end of the timing unit under test is shown as a p3 curve in fig. 3, and the signal output at the output end of the timing unit under test is shown as a p5 curve in fig. 3. The first input end of the second transmitting register 151 inputs the first pulse signal, the second input end of the second transmitting register 151 inputs the external data signal data1 (as a curve p4 in fig. 3), the clock signal generating module 110 can adjust the frequency of the clock signal, normally, when the clock signal frequency is relatively slow, the external data signal data1 can be captured by the timing unit 170 to be detected after being output by the second transmitting register 151, but when the clock signal frequency reaches a certain threshold value, a hold violation occurs, the timing unit 170 to be detected cannot capture the data signal sent by the second transmitting register 151, at this time, the critical Period of the clock signal with the hold violation is recorded as period_hd, and the critical Period satisfies the following conditions:
Tclk-Tdata=Period_hd-Th
Wherein Th is the retention time of the timing unit to be tested.
When the control module 180 controls the first input terminal A1 of the first selection module 120 to be opened and the second input terminal A2 to be closed, the first input terminal B1 of the second selection module 130 to be opened and the second input terminal B2 to be closed, that is, the first transmission register 141 is turned on with the first clock phase controller 10, the first clock phase controller 10 is turned on with the data signal transmission module 150, the data signal transmission module 150 is turned on with the reception register 142, and a second test path consisting of the clock signal generation module 110, the first transmission register 141, the first clock phase controller 10, the second transmission register 151, the reception register 142 and the control module 180 is formed. The first clock phase controller 10 may be controlled by the control module 180 to be in a pass-through state, i.e. the signal output by the first transmitting register 141 is not turned off. When the test is performed under the second test path, the first input end of the first transmitting register 141 inputs the clock signal output by the clock signal generating module 110, the second input end of the first transmitting register 141 inputs the external data signal data1, the clock signal generating module 110 can adjust the frequency of the clock signal, in general, when the clock signal frequency is relatively slow, the external data signal data1 is sent out by the first transmitting register 141 and can be captured by the receiving register 142 after being output by the first clock phase controller 10 and the second transmitting register 151, and when the clock signal frequency is relatively fast, the transmission rate of the data signal can be increased, but when the clock signal frequency is too fast, the receiving register 142 cannot normally receive the data signal sent out by the first transmitting register 141. Then when the clock signal frequency reaches a certain threshold, the period of the clock signal when the receive register 142 is just able to receive the data signal is a critical period, which is noted Per iod _data.
When the control module 180 controls the first input terminal A1 of the first selection module 120 to be opened and the second input terminal A2 to be closed, the first input terminal B1 of the second selection module 130 to be closed and the second input terminal B2 to be opened, that is, the first transmission register 141 is turned on with the second clock phase controller 20, the second clock phase controller 20 is turned on with the clock signal transmission module 160, the clock signal transmission module 160 is turned on with the reception register 142, and a third test path consisting of the clock signal generation module 110, the first transmission register 141, the second clock phase controller 20, the first buffer module B1, the reception register 142 and the control module 180 is formed. The second clock phase controller 20 may be controlled by the control module 180 to be in a pass-through state, i.e. the signal output by the first transmitting register 141 is not turned off. When the test is performed under the third test path, the first input end of the first transmitting register 141 inputs the clock signal output by the clock signal generating module 110, the second input end of the first transmitting register 141 inputs the external data signal data1, the clock signal generating module 110 can adjust the frequency of the clock signal, in general, when the clock signal frequency is relatively slow, the external data signal data1 is sent out by the first transmitting register 141 and can be captured by the receiving register 142 after being output by the second clock phase controller 20 and the first buffer module b1, and when the clock signal frequency is relatively fast, the transmission rate of the data signal can be increased, but when the clock signal frequency is too fast, the receiving register 142 cannot normally receive the data signal sent out by the first transmitting register 141. Then when the clock signal frequency reaches a certain threshold, the Period of the clock signal when the receive register 142 is just able to receive the data signal is a critical Period, which is noted as period_clk. Then, the critical Period period_data under the second test path and period_clk under the third test path satisfy the following conditions:
Tdata-Tclk=Period_data-Period_clk
The critical Period of the clock signal with the hold violation occurring in the first test path is recorded as the condition satisfied by period_hd, and the following can be obtained:
Th=Period_hd-Period_clk+Period_data
Therefore, the time sequence unit holding time Th is only related to the critical Period of the clock signal when the time sequence unit to be tested under the first test path correctly receives data, namely period_hd, the critical Period period_data of the clock signal when the delay detection module under the second test path can just normally receive the data signal, and the critical Period period_clk of the clock signal when the delay detection module under the third test path can just normally receive the data signal, and is irrelevant to the difference between the data signal transmission path and the clock signal transmission path, the delay of the buffer, the test voltage, and the like, so that the problem that in the prior art, the measurement result error is larger due to the difference between the data signal transmission path and the clock signal transmission path, the delay of the buffer, the difference of the test voltage, and the like can be avoided, and the measurement accuracy of the time sequence unit to be tested can be improved.
In an implementation manner, fig. 5 is a flowchart of a method for measuring a retention time of a time sequence unit according to an embodiment of the present application, where the method for measuring a retention time of a time sequence unit according to the present application is applicable to a circuit for measuring a retention time of a time sequence unit according to any embodiment of the present application, where the circuit includes a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a first clock phase controller, a second clock phase controller, a data signal transmitting module, a clock signal transmitting module, a timing unit to be tested, and a control module, where the control module controls the first selecting module and the second selecting module to form a first test path, a second test path, and a third test path, where the first test path is composed of the clock signal generating module, the first clock phase controller, the second clock phase controller, the data signal transmitting module, the clock signal transmitting module, the timing unit to be tested, and the control module, and the third test path is composed of the clock signal generating module, the delay detecting module, the second clock phase controller, the clock signal transmitting module, and the control module;
referring to fig. 5, the measuring method includes the steps of:
s210, respectively determining a first period value, a second period value and a third period value of the clock signal, wherein the first period value is a critical period for the time sequence unit to be tested to correctly receive the clock signal under the first test path, the second period value is a critical period for the delay detection module to correctly receive the clock signal under the second test path, and the third period value is a critical period for the delay detection module to correctly receive the clock signal under the third test path;
S220, determining the holding time of the time sequence unit according to the first period value, the second period value and the third period value.
In an embodiment, the retention time of the timing unit=the first period value-the second period value+the third period value.
In an embodiment, the period or frequency of the clock signal output by the clock signal generation module 110 may be controlled by the control module 180 to enable adjustment of the clock signal frequency under the first, second and third test paths.
In an embodiment, the first clock phase controller 10 may control the number of pulses and the phase of the clock signal output by the clock signal generating module 110, output a first pulse signal, and the second clock phase controller 20 may control the number of pulses and the phase of the clock signal output by the clock signal generating module 110, and output a second pulse signal, so as to implement a violation of the retention time of the timing unit under test by changing the period of the clock signal output by the clock signal generating module 110 in the first test path.
In an embodiment, referring to fig. 5, it is measured that, under the first test path, when the timing unit under test breaks down, the timing unit under test just captures the Period value of the clock signal, i.e., the first Period value period_hd, when the timing unit under test just captures the data signal sent by the second sending register 151 of the data signal transmission module 150, under the second test path, the receiving register 142 just captures the Period value of the clock signal, i.e., the second Period value period_data, when the receiving register 142 just captures the data signal sent by the first sending register 141 of the delay detection module 140 and output by the clock signal transmission module 160, i.e., the third Period value period_clk, respectively. The first period value, the second period value, the third period value and the retention time of the time sequence unit to be tested meet the following relation:
Th=Period_hd-Period_clk+Period_data
thereby, the holding time Th of the timing unit to be measured can be determined.
In an implementation manner, fig. 6 is a flowchart of a method for determining a period value of a clock signal according to an embodiment of the present application, where the period value may be any one of a first period value, a second period value, and a third period value according to the method described in fig. 6. The method for determining the period value of the clock signal comprises the following steps:
s310, determining a critical period estimated range and a period step length of the clock signal.
In an embodiment, the method for determining the estimated range of the critical period of the clock signal may be that firstly, the expected value of the critical period of the clock signal may be obtained by simulation by the spice tool. And determining a period step length, which can be a variable step length, and finally testing sequentially according to the period step length from small to large, wherein when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time, the difference between the test value of the critical period of the clock signal and the period step length when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time is taken as the left interval value of the estimated range of the critical period, the left interval value is marked as P_min, and the sum of the clock signal period value and the period step length when the test value of the critical period of the clock signal is inconsistent with the expected value of the critical period for the first time is taken as the right interval value of the estimated range of the critical period, and the right interval value is marked as P_max. The critical period range F of the clock signal can thus be determined and is denoted < p_min, p_max >.
In an embodiment, the period step may be a fixed period step s, for example, the period step s may be 1ps, 5ps, 10ps, and the like. In addition, the smaller the period step length is, the higher the accuracy of adjustment is, and the better the effect of reducing the influence of clock jitter is.
S320, dividing the critical period prediction range into N parts according to the period step length to obtain N+1 test period values.
In an embodiment, for example, the critical period range F may be divided into N parts according to the period step s, and two interval end points of F are added to obtain n+1 test period values. The n+1 test period values may be p_max, p_min+ (N-1) s, p_min+ (N-2) s,..p_min+ 4*s, p_min+3*s, p_min+2*s, p_min+1*s, and p_min.
S330, testing the N+1 test period values to obtain N+1 test results.
S340, finding out M test period values from the N+1 test period values, wherein the test results of the M test period values are that the time sequence unit to be tested or the delay detection module can correctly receive the clock signal, and M is smaller than or equal to N+1.
S350, determining the period value of the clock signal according to the M test period values.
In an embodiment, fig. 7 is a schematic measurement diagram of a period value of a clock signal according to an embodiment of the present application, referring to fig. 7, according to a timing analysis theory, it may be estimated that, in a first test path, when a period of the clock signal is smaller than a certain specific value (for example, p_min), a period area where a period unit to be tested of the test circuit can be sampled to a holding time of the timing unit and a violation occurs is called as an estimated stable occurrence timing violation area, such as an I area in fig. 7, and when a period of the clock signal is larger than a certain specific value (for example, p_max), a period area where a period unit to be tested of the test circuit can be stably sampled to a normal output result is called as an estimated stable non-occurrence timing violation area, such as an II area in fig. 7. Similarly, in the second test path and the third test path, when the period of the clock signal is smaller than a certain value (for example, p_min), the receiving register of the delay detecting module of the test circuit must be able to sample the result that the receiving register cannot correctly receive the data signal, the period area smaller than p_min is referred to as an area where the data signal cannot be correctly received due to the estimated stable occurrence, and when the period of the clock signal is larger than a certain value (for example, p_max), the receiving register of the delay detecting module of the test circuit must be able to stably sample the correct data signal, and the period area larger than p_max is referred to as an area where the data signal cannot be correctly received due to the estimated stable occurrence.
In the embodiment, taking the first test path test as an example, first, n+1 test period values are tested respectively, and n+1 test results are obtained and recorded. The n+1 test results may include occurrence of a hold time timing violation transition, a non-timing violation transition, occurrence of a violation and non-occurrence of a violation, i.e., occurrence of the timing violation transitions k1 and k2, non-timing violation transitions k3 and k4 shown in fig. 7, and an estimated stable occurrence timing violation region I and an estimated stable non-occurrence timing violation region II. Then find out its test result from N+1 test results as the result that the timing violation is not happened any more, and record its corresponding Period value as period_trigger_1, as in the timing trip point k 1in FIG. 7, find out its test result from N+1 test results as the result that the timing violation is not happened any more, and record its corresponding Period value as period_trigger_M, as in the timing trip point k4 in FIG. 7, finally, take the average value of Period value period_trigger_1, period value period_trigger_M and test Period value (assuming M-2) between Period value period_trigger_trigger_1 and Period value period_trigger_M, get the first Period value of the clock signal, can be calculated by the following formula:
wherein period_avg is a Period value of the clock signal. Wherein M is less than or equal to N+1.
In the embodiment, taking the second test path test as an example, first, n+1 test period values are tested respectively, and n+1 test results are obtained and recorded. The n+1 test results may include failure to properly receive the data signal, stable occurrence of transitions that fail to properly receive the data signal, and stable failure to properly receive the data signal. The method comprises the steps of obtaining a first Period value of a clock signal, finding out a result of which the data signal can not be received correctly when the test result is just unstable from N+1 test results, recording a Period value corresponding to the result as period_trigger_1, finding out a result of which the data signal can not be received correctly when the test result is just unstable from N+1 test results, recording a Period value corresponding to the result as period_trigger_M, and finally averaging the Period value period_trigger_1, the Period value period_trigger_M and the test Period value (assuming M-2 test Period values are arranged between the Period value period_trigger_1 and the Period value period_trigger_M) to obtain a second Period value of the clock signal. Similarly, a third period value may also be determined in accordance with this method.
The foregoing description is only exemplary embodiments of the application and is not intended to limit the scope of the application. In general, the various embodiments of the application may be implemented in hardware or special purpose circuits, software, logic or any combination thereof. For example, some aspects may be implemented in hardware, while other aspects may be implemented in firmware or software which may be executed by a controller, microprocessor or other computing device, although the application is not limited thereto.
The foregoing detailed description of exemplary embodiments of the application has been provided by way of exemplary and non-limiting examples. Various modifications and adaptations to the above embodiments may become apparent to those skilled in the art without departing from the scope of the application, which is defined in the accompanying drawings and claims. Accordingly, the proper scope of the application is to be determined according to the claims.
Claims (10)
1. The measuring method is suitable for a measuring circuit of the time sequence unit holding time, and the measuring circuit comprises a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a first clock phase controller, a second clock phase controller, a data signal transmission module, a clock signal transmission module, a time sequence unit to be measured and a control module, wherein the control module controls the first selecting module and the second selecting module to form a first test path, a second test path and a third test path, the first test path consists of the clock signal generating module, the first clock phase controller, the second clock phase controller, the data signal transmission module, the clock signal transmission module, the time sequence unit to be measured and the control module, the second test path consists of the clock signal generating module, the delay detecting module, the first clock phase controller, the data signal transmission module and the control module, and the third test path consists of the clock signal generating module, the delay detecting module, the second clock phase controller, the clock signal transmission module and the clock signal transmission module;
the method comprises the following steps:
Respectively determining a first period value, a second period value and a third period value of a clock signal, wherein the first period value is a critical period of the clock signal when the time sequence unit to be tested is correctly received under the first test path, the second period value is a critical period of the clock signal when the delay detection module is correctly received under the second test path, and the third period value is a critical period of the clock signal when the delay detection module is correctly received under the third test path;
And determining the holding time of the time sequence unit according to the first period value, the second period value and the third period value.
2. The method according to claim 1, wherein the holding time of the timing unit is equal to a sum of the first period value and the second period value minus the third period value.
3. The method according to claim 1, wherein determining the period value of the clock signal, the period value being any one of the first period value, the second period value, and the third period value, comprises:
determining a critical period estimated range and a period step length of a clock signal;
dividing the critical period prediction range into N parts according to the period step length to obtain N+1 test period values;
testing the N+1 test period values to obtain N+1 test results;
M test period values are found out from the N+1 test period values, and the test results of the M test period values are that the clock signal can be correctly received by the time sequence unit to be tested or the delay detection module, wherein M is smaller than or equal to N+1;
and determining the period value of the clock signal according to the M test period values.
4. The method for measuring a retention time of a sequential cell according to claim 2, wherein the cycle step is a fixed cycle step.
5. The measuring circuit for the time sequence unit holding time is characterized by comprising a clock signal generating module, a first selecting module, a second selecting module, a delay detecting module, a first clock phase controller, a second clock phase controller, a data signal transmission module, a clock signal transmission module, a time sequence unit to be measured and a control module;
The clock signal generation module is respectively and electrically connected with the first selection module, the delay detection module and the control module, the delay detection module is respectively and electrically connected with the first selection module, the second selection module and the control module, the first selection module is respectively and electrically connected with the control module, the first clock phase controller and the second clock phase controller, the second selection module is respectively and electrically connected with the control module, the data signal transmission module and the clock signal transmission module, the first clock phase controller is respectively and electrically connected with the control module and the data signal transmission module, the second clock phase controller is respectively and electrically connected with the control module and the clock signal transmission module, the data signal transmission module is respectively and electrically connected with the time sequence unit to be tested and the control module, the clock signal transmission module is respectively and electrically connected with the time sequence unit to be tested and the control module, and the time sequence unit to be tested is electrically connected with the control module;
the first clock phase controller is used for outputting a first pulse signal and providing a clock signal for the data signal transmission module, and the second clock phase controller is used for outputting a second pulse signal and providing a clock signal for the clock signal transmission module;
The control module is configured to control the first selection module and the second selection module to form a first test path, a second test path and a third test path, so as to determine a holding time of a timing unit based on the first test path, the second test path and the third test path, where the first test path is composed of the clock signal generating module, the first clock phase controller, the second clock phase controller, the data signal transmitting module, the clock signal transmitting module, the timing unit to be tested and the control module, the second test path is composed of the clock signal generating module, the delay detecting module, the first clock phase controller, the data signal transmitting module and the control module, and the third test path is composed of the clock signal generating module, the delay detecting module, the second clock phase controller, the clock signal transmitting module and the control module.
6. The timing unit hold time measurement circuit of claim 5, wherein the clock signal generation module comprises a clock tuning unit and a clock pulse control unit, the clock tuning unit is electrically connected to the clock pulse control unit, the clock pulse control unit is electrically connected to the delay detection module and the first input terminal of the first selection module, respectively, and the control module is electrically connected to the clock tuning unit and the clock pulse control unit, respectively.
7. The timing unit hold time measurement circuit of claim 5, wherein the delay detection module comprises a first transmit register and a receive register, wherein a first input terminal of the first transmit register is electrically connected to the clock signal generation module, a second input terminal of the first transmit register inputs an external data signal, and an output terminal of the first transmit register is electrically connected to a second input terminal of the first selection module;
The first input end of the receiving register is electrically connected with the clock signal generating module, the second input end of the receiving register is electrically connected with the output end of the second selecting module, and the output end of the receiving register is electrically connected with the control module.
8. The timing unit hold time measurement circuit of claim 5, wherein the data signal transmission module comprises a second transmit register, a first input terminal of the second transmit register is electrically connected to the first clock phase controller, a second input terminal of the second transmit register inputs an external data signal, and an output terminal of the second transmit register is electrically connected to the second input terminal of the second selection module and the second input terminal of the timing unit under test, respectively.
9. The timing unit hold time measurement circuit of claim 5, wherein the clock signal transmission module comprises at least one first buffer module, an input terminal of the first buffer module is electrically connected to the second clock phase controller, and an output terminal of the first buffer module is electrically connected to the first input terminal of the second selection module and the first input terminal of the timing unit under test, respectively.
10. The timing unit hold time measurement circuit of claim 5, wherein the first test path is formed when the control module controls the first input of the first selection module to be closed and the second input to be open, the first input and the second input of the second selection module to be both open;
When the control module controls the first input end of the first selection module to be opened and the second input end of the first selection module to be closed, and the first input end of the second selection module to be opened and the second input end of the second selection module to be closed, the second test path is formed;
And when the control module controls the first input end of the first selection module to be opened and the second input end of the first selection module to be closed, and the first input end of the second selection module to be closed and the second input end of the second selection module to be opened, the third test path is formed.
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| CN202010476276.2A CN113740717B (en) | 2020-05-29 | 2020-05-29 | A method and circuit for measuring the holding time of a timing unit |
| PCT/CN2021/095441 WO2021238838A1 (en) | 2020-05-29 | 2021-05-24 | Method and circuit for measuring retention time of time sequence unit |
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| CN202010476276.2A CN113740717B (en) | 2020-05-29 | 2020-05-29 | A method and circuit for measuring the holding time of a timing unit |
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| CN114167264B (en) * | 2021-12-03 | 2024-03-15 | 中国人民解放军国防科技大学 | Device for detecting digital circuit hold time violations in nuclear radiation environment |
| CN114460345B (en) * | 2022-01-06 | 2025-06-06 | 上海华虹宏力半导体制造有限公司 | Circuit and test system for measuring device OCV parameters |
| CN114924180B (en) * | 2022-05-18 | 2025-10-03 | 深圳市一博科技股份有限公司 | A circuit for generating a reference clock in a PCIE fixture |
| CN115425952B (en) * | 2022-09-06 | 2025-09-26 | 厦门紫光展锐科技有限公司 | Holding time detection sensor, method, chip, chip module and electronic device |
| CN115981209A (en) * | 2023-01-06 | 2023-04-18 | 上海科技大学 | Automatic overclocking controller based on circuit delay measurement |
| CN116449177B (en) * | 2023-03-28 | 2025-08-05 | 成都华微电子科技股份有限公司 | Chip signal connection intelligent detection system and detection method |
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| CN101467115A (en) * | 2006-04-07 | 2009-06-24 | 阿尔特拉公司 | Memory interface circuitry with phase detection |
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| DE10035169A1 (en) * | 2000-07-19 | 2002-02-07 | Infineon Technologies Ag | Method and device for testing the setup time and hold time of signals of a circuit with clocked data transmission |
| JP3630092B2 (en) * | 2000-10-19 | 2005-03-16 | 日本電気株式会社 | Phase frequency comparison circuit |
| JP2003058273A (en) * | 2001-08-13 | 2003-02-28 | Oki Electric Ind Co Ltd | Hold time measuring circuit |
| US20080071489A1 (en) * | 2006-09-15 | 2008-03-20 | International Business Machines Corporation | Integrated circuit for measuring set-up and hold times for a latch element |
| US7596772B2 (en) * | 2006-12-08 | 2009-09-29 | Faraday Technology Corp. | Methodology and system for setup/hold time characterization of analog IP |
| KR100950483B1 (en) * | 2008-06-27 | 2010-03-31 | 주식회사 하이닉스반도체 | Setup / hold time measuring device |
| KR100956782B1 (en) * | 2008-09-24 | 2010-05-12 | 주식회사 하이닉스반도체 | Setup / hold time test device and method |
| US7795939B2 (en) * | 2008-12-29 | 2010-09-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system for setup/hold characterization in sequential cells |
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