CN113764292B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113764292B CN113764292B CN202111312674.1A CN202111312674A CN113764292B CN 113764292 B CN113764292 B CN 113764292B CN 202111312674 A CN202111312674 A CN 202111312674A CN 113764292 B CN113764292 B CN 113764292B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/18—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
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Abstract
本发明提供了一种半导体装置的制作方法及半导体装置，其中，所述方法包括：将第一半导体芯片焊接至基板的第一表面上；将平衡片安装在与所述第一表面相对的所述基板的第二表面上，以消减所述焊接导致的形变；将第二半导体芯片焊接至第一半导体芯片背离所述基板的一侧上。本发明所公开的方法和装置有利于提高第二半导体芯片焊接的可靠性。
The present invention provides a method for fabricating a semiconductor device and a semiconductor device, wherein the method includes: soldering a first semiconductor chip to a first surface of a substrate; installing a balance sheet on all surfaces opposite to the first surface soldering the second semiconductor chip to the side of the first semiconductor chip away from the substrate. The method and device disclosed in the present invention are beneficial to improve the reliability of the bonding of the second semiconductor chip.
Description
Technical Field
The present invention relates to the field of semiconductor packaging, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
With the increasing development of semiconductor technology, a package structure having a high integration density is more and more important. For example, the 3D package structure may realize mutual stacking between chips. However, the above-described prior art has the following problems: since the upper chip needs to be soldered to the lower chip and the lower chip needs to be soldered to the substrate, the substrate is deformed by the temperature rise generated in the process of soldering the lower chip to the substrate, resulting in an uneven soldering area when the upper chip is subsequently soldered to the lower chip.
Illustratively, in a chip approach for photonic computing, an electronic integrated circuit chip and a photonic integrated circuit chip are typically stacked on a substrate. Because the electronic integrated circuit chip and the photonic integrated circuit chip are both made of silicon substrate materials, and the substrate is generally made of glass or organic materials, the lower chip can deform after being welded on the substrate (the assembly body after being welded deforms due to the temperature rise in the welding process, and then the welding area of the upper chip is uneven). However, to meet the requirements of 3D chip packaging, the thickness of chips generally adopted in the industry is relatively thin, and the solder joints used in the soldering process of electronic integrated circuit chips are usually very thin solders, which are only tens of micrometers. Therefore, the solder joint between the electronic integrated circuit chip and the photonic integrated circuit chip is difficult to tolerate the deformation of the basic assembly, and the problem of solder joint fracture or debonding on the electronic integrated circuit chip often occurs, so that the whole semiconductor device is short-circuited or broken.
Disclosure of Invention
In order to overcome the disadvantages of the prior art, the present invention provides a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problems of the prior art that a substrate is easily deformed during the manufacturing of the semiconductor device and the reliability of a multilayer chip assembly by stack bonding is poor.
The purpose of the invention is realized by adopting the following technical scheme:
according to an aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite; providing a first semiconductor chip, and welding the first semiconductor chip to the first surface of the substrate; providing a balance sheet, and mounting the balance sheet on the second surface of the substrate to absorb deformation caused by the welding; providing a second semiconductor chip, and welding the second semiconductor chip to the first semiconductor chip on the side opposite to the substrate.
According to another aspect of the present invention, there is also provided a semiconductor device including: a substrate having opposing first and second surfaces; a first semiconductor chip disposed on the first surface of the substrate by a first bonding structure; a second semiconductor chip disposed on a side of the first semiconductor chip facing away from the substrate by a second solder structure; a balance sheet disposed on the second surface of the substrate to absorb deformation caused by soldering between the first semiconductor chip and the substrate.
According to still another aspect of the present invention, there is also provided a method of manufacturing a semiconductor device, wherein the semiconductor device includes a substrate and a first semiconductor chip; the manufacturing method comprises the following steps: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite; providing a first semiconductor chip, and welding the first semiconductor chip to the first surface of the substrate; providing a deformation control device, wherein the deformation control device comprises a first part and a second part, and during at least one time period in the process of welding the first semiconductor chip to the substrate, the first surface of the substrate is contacted with the first part of the deformation control device, the second surface of the substrate is contacted with the second part of the deformation control device, and the first part and the second part simultaneously generate acting force to the substrate so as to reduce the deformation of the substrate.
Compared with the prior art, the manufacturing method of the semiconductor device and the semiconductor device provided by the embodiment of the invention are beneficial to improving the reliability of the second semiconductor chip welding.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other embodiments based on these drawings without creative efforts.
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device provided according to an embodiment of the present invention;
FIGS. 2A-2E are schematic illustrations of a process for fabricating a semiconductor device according to an embodiment of the present invention;
FIGS. 3A-3D are schematic illustrations of a process for fabricating a semiconductor device according to another embodiment of the present invention;
FIG. 4 is a schematic diagram illustrating a process for fabricating a semiconductor device according to yet another embodiment of the present invention;
fig. 5 is a schematic partial structure diagram of a semiconductor device according to an embodiment of the present invention;
FIGS. 6A-6B are schematic illustrations of a process for fabricating a semiconductor device according to another embodiment of the present invention;
FIG. 7A is a schematic diagram illustrating a process for fabricating a semiconductor device according to another embodiment of the present invention;
fig. 7B is a schematic top view of the structure of fig. 7A.
Detailed Description
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical means of the present invention more clearly understood, the present invention may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present invention more clearly understood, the following preferred embodiments are described in detail with reference to the accompanying drawings.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The present invention will be described in further detail with reference to the accompanying drawings and detailed description, in order to make the objects, features and advantages thereof more comprehensible.
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device provided according to an embodiment of the present invention. The method for manufacturing the semiconductor device comprises the following steps:
s101, providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite;
s102, providing a first semiconductor chip, and welding the first semiconductor chip to the first surface of the substrate;
s103, providing a balance sheet, and mounting the balance sheet on the second surface of the substrate to reduce deformation caused by welding;
and S104, providing a second semiconductor chip, and welding the second semiconductor chip to the side, away from the substrate, of the first semiconductor chip.
Fig. 2A-2D are schematic diagrams illustrating a manufacturing process of a method for manufacturing a semiconductor device according to an embodiment of the invention. Referring to fig. 2A-2D, first, a substrate 100 is provided, the substrate 100 having a first surface 100a and a second surface 100b opposite to each other, and then a first semiconductor chip 200 is provided, and the first semiconductor chip 200 is bonded to the first surface 100a of the substrate 100; next, inverting the substrate 100 to provide a balance sheet 400, and mounting the balance sheet 400 on the second surface 100b of the substrate 100 to reduce deformation of the substrate 100 caused by the soldering; finally, a second semiconductor chip 300 is provided, and the second semiconductor chip 300 is soldered to the first semiconductor chip 200 on the side facing away from the substrate 100.
As shown in fig. 2B, since the thermal expansion coefficients of the substrate 100 and the first semiconductor chip 200 are different, the substrate 100 is deformed upward after being subjected to a high temperature soldering process. As shown in fig. 2C, in the embodiment of the invention, before the second semiconductor chip 300 is mounted, the substrate 100 is inverted, and the balance sheet 400 is mounted on the second surface 100b of the substrate 100, so as to reduce the deformation caused by the soldering of the first semiconductor chip 200, that is, the deformed substrate 100 becomes flat, so as to provide a relatively flat soldering area for the subsequent mounting of the second semiconductor chip 300, which is beneficial to improving the reliability of the soldering of the second semiconductor chip 300.
In the prior art, a technical solution for soldering the second semiconductor chip 300 and the first semiconductor chip 200 first and then soldering the second semiconductor chip 300 and the first semiconductor chip 200 as a whole on the substrate 100 has been proposed, but this solution can reduce the problem of deformation caused by the difference in thermal expansion coefficients between different materials during soldering between the second semiconductor chip 300 and the first semiconductor chip 200, thereby ensuring the strength of the solder joint of the second semiconductor chip 300; however, if the second semiconductor chip 300 and the first semiconductor chip 200 are first soldered together, the second semiconductor chip 300 and the first semiconductor chip 200 need to be entirely encapsulated by a plastic encapsulating material, because the thicknesses of the second semiconductor chip 300 and the first semiconductor chip 100 are very thin and the sizes of the second semiconductor chip 300 and the first semiconductor chip 200 are not the same, if the second semiconductor chip 300 and the first semiconductor chip 200 are not encapsulated, the second semiconductor chip is difficult to be sucked and grabbed, and the problem of difficulty in grabbing still exists, so that the process manufacturing still has great difficulty.
In view of the above, an object of the present invention is to enable improvement of reliability of electrical connection between semiconductor chips stacked up and down in a semiconductor device having a 3D package.
Further, the step of mounting the balance sheet 400 on the second surface 100b of the substrate 100 includes: the balance tab 400 is mounted on the second surface 100b of the substrate 100 by means of soldering. Specifically, in an embodiment, as shown in fig. 2D, the balance sheet 400 is soldered to the second surface 100B of the substrate 100 by solder balls 401, and since the substrate 100 and the balance sheet 400 have the same difference in thermal expansion coefficient, the substrate 100 is also deformed upwards after being subjected to a high-temperature soldering process, that is, the deformation problem generated in fig. 2B before can be eliminated, so that the resulting whole assembly can form a structure with bilateral symmetry of the substrate 100, so as to offset or reduce the deformation, and even flatten the substrate 100, so as to facilitate the subsequent mounting of the second semiconductor chip 300, thereby improving the soldering reliability of the second semiconductor chip 300 and the first semiconductor chip 200.
In another embodiment, as shown in fig. 2E, the balance sheet 400 is bonded to the second surface 100B of the substrate 100 by the glue 402, and then a heating process is performed to cure the balance sheet 400 and the substrate 100, since the substrate 100 is deformed again in a direction opposite to the previous deformation after the glue 402 is subjected to the heating process, the deformation problem generated in fig. 2B before can be offset or weakened, so that the resulting assembly can form a structure with bilateral symmetry of the substrate 100, thereby reducing the deformation, and even flattening the substrate 100, so as to facilitate the subsequent mounting of the second semiconductor chip 300, and further improve the bonding reliability between the second semiconductor chip 300 and the first semiconductor chip 200.
Further, in order to achieve the thinning of the entire semiconductor device, the balance sheet 400 is bonded to the second surface 100b of the substrate 100 using a removable glue 402. That is, after the second semiconductor chip 300 is bonded to the first semiconductor chip 200, the balance sheet 400 may be removed by removing the glue 402.
Further, the balance tab 400 is made of a material having a thermal expansion coefficient equal to or similar to that of the first semiconductor chip 100 to offset deformation caused by the soldering.
Further, the balance tab 400 is a ceramic tab. Since the ceramic sheet has a smaller thermal expansion coefficient and a thermal expansion coefficient similar to that of the first semiconductor chip 100, and the ceramic sheet is made of a harder material, it is advantageous to mount the balance tab 400 on the second surface 100b of the substrate 100 by soldering or by bonding. The cost of the ceramic wafer is lower than if a dummy chip is used to balance the deformation on the back of the substrate 100.
Alternatively, in order to balance the deformation of both sides of the substrate 100, the size of the balance sheet 400 is set to be identical to that of the first semiconductor chip 200.
Alternatively, when the size of the first semiconductor chip 200 is larger, the first semiconductor chip 200 may have a larger number of external leads on the second surface 100b side of the substrate 100, and if the size of the balance sheet 400 is set to be consistent with the size of the first semiconductor chip 200, a part of the area for the lower external leads of the first semiconductor chip 200 may be occupied, in order to solve the above problem, in an embodiment of the present invention, the size of the balance sheet 400 is set to be smaller than the size of the first semiconductor chip 200, and the thickness of the balance sheet 400 in the thickness direction is set to be thicker, that is, by adopting a manner that the balance sheet 400 is thickened, so as to solve the problem of insufficient counteracting strength for counteracting the deformation of the substrate 100 due to the smaller size of the balance sheet 400. Further, it is understood that when the size of the balance sheet 400 is set to be smaller than that of the first semiconductor chip 200, the amount of solder used in the soldering process or the amount of glue used in the bonding process can also be saved.
Further, after the size of the balance sheet 400 or the thickness thereof is determined, the balance sheet 400 is mounted on the second surface 100b of the substrate 100 by means of alignment welding or bonding, and the geometric center of the balance sheet 400 is made coaxial with the geometric center of the first semiconductor chip 200 in a direction perpendicular to the substrate 100 after the mounting is completed, so as to balance the deformation of both sides of the substrate 100.
Illustratively, the first semiconductor chip 200 is a silicon-based optical chip (photonic integrated circuit chip, PIC), and the second semiconductor chip 300 is a silicon-based electrical chip (electronic integrated circuit chip, EIC), and the optical chip may be formed by stacking the first semiconductor chip 200 and the second semiconductor chip 300. Illustratively, the step of soldering the first semiconductor chip 200 onto the first surface 100a of the substrate 100 includes: the first semiconductor chip 200 is soldered onto the first surface of the substrate via a first solder structure 201, wherein the first solder structure 201 is a sphere of solder. Such as solder balls, the material of which may be tin-silver.
Exemplarily, the step of soldering the second semiconductor chip 300 to the first semiconductor chip 200 on the side facing away from the substrate 100 comprises: soldering the second semiconductor chip 300 to a side surface of the first semiconductor chip 200 facing away from the substrate 100 via a second soldering structure 303, wherein the second soldering structure 303 comprises a conductive bump 301 and a solder layer 302 on the conductive bump 301, wherein the conductive bump 301 is arranged in a front side electrical coupling region of the second semiconductor chip 300. In this embodiment, the second semiconductor chip 300 is soldered to a surface of the first semiconductor chip 200 facing away from the substrate 100 by flip chip (flip chip) packaging. Specifically, a second pad (not shown) is formed on the front side electrical coupling region of the second semiconductor chip 300, and the second pad is electrically connected to a first pad (not shown) on the front side electrical coupling region of the first semiconductor chip 200 through a conductive bump 301 formed on the second pad and a solder layer 302 on the conductive bump, so as to electrically connect the first semiconductor chip 200 and the second semiconductor chip 300. The second soldering structure 303 formed by the conductive bump 301 and the solder layer 302 can improve the reliability of the electrical connection between the second semiconductor chip 300 and the first semiconductor chip 200, and can ensure higher soldering strength by using the solder layer 302, and meanwhile, because the conductive bump 301 has a larger cross-sectional area, better current passing capability can be obtained under the condition of introducing large current. The conductive bump 301 may be a copper pillar bump (copper pillar bump) or a bump formed in a top metal pad opening (pad opening), which is not limited in the present invention.
In addition, vertical Through holes are formed in the first semiconductor chip 200 and/or the second semiconductor chip 300 by a TSV (Through Silicon Via) packaging technology, which implements vertical electrical interconnection of the Through Silicon vias by filling conductive substances such as copper, tungsten, and polysilicon, thereby implementing electrical interconnection between the first semiconductor chip 200 and the substrate 100, and/or implementing electrical interconnection between the second semiconductor chip 300 and the first semiconductor chip 200, and since a wire-bond (wire-bond) process is not required, the influence of electromagnetic interference on the bandwidth can be reduced, the signal integrity of the first semiconductor chip 200 and the second semiconductor chip 300 can be ensured, and a higher chip stacking density can be allowed.
Fig. 3A-3D are schematic views illustrating the manufacturing process of a method for manufacturing a semiconductor device according to another embodiment of the present invention. Referring to fig. 3A-3D, the second surface 100b of the substrate 100 has a plurality of conductive pads 120 thereon and the substrate 100 has via conductive structures 130 corresponding to the conductive pads 120 one by one, after the mounting is completed, the conductive pads 120 are electrically connected to pins (not shown) of the first semiconductor chip 100 through the corresponding via conductive structures 130 to form external terminals. The packaged semiconductor device can be electrically connected to an external Circuit Board through the external connection terminal to achieve conduction of related electrical functions, and the external Circuit Board may be a Flexible Circuit Board (FPC) or a rigid Circuit Board (PCB), for example.
Further, as shown in fig. 3B, before the balance sheet 400 is mounted on the second surface 100B of the substrate 100, the balance sheet 400 is subjected to a patterning process, such as stamping or laser cutting, to form a plurality of hollow areas 80 on the balance sheet 400, so as to obtain a balance sheet 480 having the hollow areas 80. As shown in fig. 3C, after the mounting is completed, partial areas of the plurality of conductive pads 120 are exposed at the plurality of hollowed-out areas 80 of the balance sheet 400. In some embodiments, the balance sheet is a ceramic sheet, which can facilitate the patterning process to form the hollow area. In addition, a metal plating layer is formed on the surface of the conductive pad 120 exposed out of the hollow area 80 to achieve better electrical connection with an external circuit board, so as to be used for input and output of electrical signals of an external device. For example, the material of the metal plating layer may be tin, nickel gold, or tin silver, and the invention is not limited herein. As shown in fig. 3D, for example, the dummy wafer 480 having the hollow area 80 is mounted on the second surface 100b of the substrate 100 by soldering or bonding, then the substrate is turned over again, and finally the second semiconductor chip 300 is soldered 303 on the side of the first semiconductor chip 200 away from the substrate 100 by a second soldering structure.
Fig. 4 is a schematic view of a manufacturing process of a method for manufacturing a semiconductor device according to another embodiment of the present invention, as shown in fig. 4, further including: after the second semiconductor chip 300 has been soldered to the first semiconductor chip 200 on the side facing away from the substrate 100, at least one third semiconductor chip 800 is soldered in a stacked manner to the second semiconductor chip 300 on the side facing away from the first semiconductor chip 200.
Fig. 5 is a schematic partial structural diagram of a semiconductor device according to an embodiment of the present invention, and as shown in fig. 5, in an embodiment of the present invention, the semiconductor device includes: a substrate 100, the substrate 100 having a first surface 100a and a second surface 100b opposite to each other; a first semiconductor chip 200, the first semiconductor chip 200 being disposed on the first surface 100a of the substrate 100 by a first bonding structure 201; a second semiconductor chip 300, the second semiconductor chip 300 being arranged on a side of the first semiconductor chip 200 facing away from the substrate 100 by means of a second solder structure 303; a balance sheet 400, the balance sheet 400 being disposed on the second surface 100b of the substrate 100 to absorb deformation caused by soldering between the first semiconductor chip 200 and the substrate 100.
Optionally, the balance tab 400 is disposed on the second surface 100b of the substrate 100 in a soldering manner.
Optionally, the balance sheet 400 is disposed on the second surface 100b of the substrate 100 in an adhesive manner.
Optionally, the balancing sheet 400 is bonded to the second surface 100b of the substrate 100 by removable glue.
Further, the balance sheet 400 is made of a material having a thermal expansion coefficient identical or close to that of the first semiconductor chip 200.
Further, the balance tab 400 is a ceramic tab.
Optionally, the balance tab 400 has a size corresponding to the first semiconductor chip 200.
Optionally, the size of the balance tab 400 is smaller than the size of the first semiconductor chip 200.
Further, the geometric center of the balance tab 400 is coaxial with the geometric center of the first semiconductor chip 200 in a direction perpendicular to the substrate 100.
Further, the first semiconductor chip 200 is a silicon-based optical chip (photonic integrated circuit chip, PIC), and the second semiconductor chip 300 is a silicon-based electrical chip (electronic integrated circuit chip, EIC).
Further, the first soldering structure 201 is a sphere made of solder.
Further, the second soldering structure 303 comprises a conductive bump 301 and a solder layer 302 on the conductive bump, wherein the conductive bump 301 is arranged in the front side electrical coupling region of the second semiconductor chip 300.
Further, the second surface 100b of the substrate 100 has a plurality of conductive pads 120 thereon and the substrate 100 is provided therein with via conductive structures 130 corresponding to each conductive pad 120 one by one, and the plurality of conductive pads 120 are electrically connected to a plurality of pins (not shown) of the first semiconductor chip 200 through the corresponding via conductive structures 130 to form an external terminal.
Further, a plurality of hollow areas 80 are disposed on the balance sheet 400, and partial areas of the plurality of conductive pads 120 are exposed at the plurality of hollow areas 80 of the balance sheet 400 to form external terminals for inputting and outputting external circuit signals.
Further, as shown in fig. 4, the semiconductor device further includes at least one third semiconductor chip 800, and the at least one third semiconductor chip 800 is bonded to the second semiconductor chip 300 on a side facing away from the first semiconductor chip 200 in a stacked manner.
It should be noted that, in the semiconductor device, components similar to those in the semiconductor manufacturing method and effects thereof have been described in detail in the foregoing semiconductor manufacturing method, and are not described again here.
It should be understood that only a portion of the semiconductor device integrated with the first semiconductor chip 200 and the second semiconductor chip 300 is shown in fig. 2A-5, and that the complete semiconductor device may also integrate other waveguides and electrodes, as well as other active and passive devices.
As can be seen from the above, in the semiconductor device and the method for manufacturing the semiconductor device according to the embodiments of the present invention, the first semiconductor chip and the balance piece are symmetrically mounted on two sides of the substrate, so that the problem of deformation caused by different thermal expansion coefficients of the first semiconductor chip and the substrate during the process of soldering the first semiconductor chip to the substrate can be solved, a relatively flat soldering area is provided for the second semiconductor chip, and the reliability of soldering the second semiconductor chip can be improved.
Fig. 6A-6B are schematic views illustrating a manufacturing process of a method for manufacturing a semiconductor device according to another embodiment of the present invention. As shown in fig. 6A to 6B, an embodiment of the present invention provides a method for manufacturing a semiconductor device including a substrate 100 and a first semiconductor chip 200, the method comprising: providing a substrate 100, wherein the substrate 100 has a first surface 100a and a second surface 100b opposite to each other; providing a first semiconductor chip 200, and soldering the first semiconductor chip 200 to the first surface 100a of the substrate 100; providing a deformation control device 500, wherein the deformation control device 500 comprises a first portion 501 and a second portion 502, and during at least a period of time during soldering of the first semiconductor chip 200 to the substrate 100, the first surface 100a of the substrate 100 is in contact with the first portion 501 of the deformation control device 500, the second surface 100b of the substrate 100 is in contact with the second portion 502 of the deformation control device 500, and the first portion 501 and the second portion 502 simultaneously exert a force on the substrate 100 to reduce the deformation of the substrate 100.
Illustratively, the contact may be partial contact or may be contact over the entire surface. During the process of contacting the first and second portions 501 and 502 with the substrate 100, the substrate 100 deforms due to heat of soldering, etc. to generate an acting force on the first and second portions 501 and 502, and thus the first and second portions 501 and 502 also generate a reaction force on the substrate 100, which can be regarded as a source of the acting force of the first and second portions 501 and 502 on the substrate 100 to reduce the deformation of the substrate 100. In addition, in some embodiments, the deformation control device 500 applies an additional force to compress the first portion 501, the second portion 502, and the substrate 100, thereby reducing the deformation of the substrate 100. In some embodiments, the contact area of the first portion 501 with the substrate 100 may be 20%, 30% to 70% of the area of the substrate 100. In some embodiments, the contact area of the first portion 501 with the substrate 100 occupies more than 10% of the area of the substrate 100, but is not limited thereto. In some embodiments, the contact area of the second portion 502 with the substrate 100 is 40% of the substrate area, and may be 45% or more, and may be 50% to 90% or more, and may also be 90% or more (e.g., fully contacting). The contact position and the contact area of the first part 501 and the second part 502 can be determined according to the position of deformation, and the like. Illustratively, one of the first portion 501 and the second portion 502 may serve as a load bearing function. In some embodiments, a force is simultaneously applied to the substrate 100 by the first portion 501 and the second portion 502 to reduce the deformation amount of the substrate 100 during deformation, the substrate 100 is disposed above the second portion 502, the second portion 502 carries the substrate 100, and the contact area of the first portion 501 and the substrate 100 occupies more than 10% of the substrate area.
Optionally, the first portion 501 of the deformation control apparatus 500 includes a portion protruding beyond the edge of the substrate 100, and the first portion 501 and the second portion 502 of the deformation control apparatus 500 may jointly apply an acting force to the substrate 100 to ensure that the substrate 100 is not deformed. Illustratively, to better control the deformation defining effect of the deformation control device 500 on the substrate 100, the deformation control device 500 is electrically connected to a control system (not shown) to receive a switch control signal from the control system and adjust the distance between the first portion 501 and the second portion 502 of the deformation control device 500 based on the switch control signal. The deformation control device 500 may compress the first portion 501, the second portion 502, and the substrate 100 to different degrees according to the control signal, thereby achieving a reduction in deformation of the substrate 100. After the first semiconductor chip 200 and/or the second semiconductor chip 300 are bonded to the substrate 100, the deformation control device 500 may be removed from contact with the substrate 100 or at least one of the first portion 501 and the second portion 502 may be removed from contact with the substrate 100 by the switching control signal of the control system.
Optionally, a second semiconductor chip 300 is provided, and the second semiconductor chip 300 is soldered to the first semiconductor chip 200 on a side facing away from the substrate 100.
Fig. 7A is a schematic view of a manufacturing process of a method for manufacturing a semiconductor device according to another embodiment of the present invention, and fig. 7B is a schematic view of a top structure of fig. 7A. As shown in fig. 7A-7B, the difference between fig. 7A and fig. 6A is that the first portion 503 of the deformation control apparatus 500 includes a plurality of opening structures 503a, and the plurality of opening structures 503a and the first surface 100a of the substrate 100 together form an accommodating space for accommodating a plurality of first semiconductor chips 200. The plurality of first semiconductor chips 200 may be soldered to the first surface 100a of the substrate 100 through the plurality of opening structures 503a of the first portion 503. Illustratively, as shown in fig. 7B, the first portion 503 of the deformation control device 500 includes a plurality of opening structures 503a, which can make the first portion 503 of the deformation control device 500 have more contact area with the substrate 100, so that the pressure distribution on the surface of the substrate 100 is more uniform to absorb the deformation of the substrate 100 caused by the soldering.
As can be seen from the above, in the manufacturing method of the semiconductor device according to the embodiment of the present invention, the first portion and the second portion of the deformation control device are disposed on the two sides of the substrate, so that deformation of the surface of the substrate can be limited, a problem of deformation caused by different thermal expansion coefficients of the first semiconductor chip and the substrate in a soldering process of the first semiconductor chip to the substrate is solved, a relatively flat soldering area is provided for a subsequent second semiconductor chip, and reliability of soldering of the second semiconductor chip is improved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, which is defined by the appended claims.
Claims (14)
1. A method of manufacturing a semiconductor device, the method comprising:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite;
providing a first semiconductor chip, and welding the first semiconductor chip to the first surface of the substrate;
providing a balance sheet, and mounting the balance sheet on the second surface of the substrate to absorb deformation caused by the welding;
providing a second semiconductor chip, and welding the second semiconductor chip to the first semiconductor chip on the side opposite to the substrate;
wherein the balance tab is mounted on the second surface of the substrate before the second semiconductor chip is soldered to the first semiconductor chip on a side thereof facing away from the substrate;
the second surface of the substrate is provided with a plurality of conductive bonding pads, the balance sheet is provided with a plurality of hollowed-out areas, and partial areas of the conductive bonding pads are exposed at the hollowed-out areas.
2. The method of manufacturing of claim 1, wherein the step of mounting the balancing sheet on the second surface of the substrate comprises:
the balance sheet is mounted on the second surface of the base plate by means of soldering or bonding.
3. The method of manufacturing of claim 1, wherein the method comprises: after the second semiconductor chip is soldered to the first semiconductor chip, the balance tab is removed.
4. The manufacturing method according to any one of claims 1 to 3, wherein the balance sheet is a ceramic sheet.
5. A semiconductor device, comprising:
a substrate having opposing first and second surfaces;
a first semiconductor chip disposed on the first surface of the substrate by a first bonding structure;
a second semiconductor chip disposed on a side of the first semiconductor chip facing away from the substrate by a second solder structure;
a balance sheet disposed on the second surface of the substrate to absorb deformation caused by soldering between the first semiconductor chip and the substrate;
wherein the balance tab is mounted on the second surface of the substrate before the second semiconductor chip is soldered to the first semiconductor chip on a side thereof facing away from the substrate;
the second surface of the substrate is provided with a conductive bonding pad, the balance sheet is provided with a plurality of hollowed-out areas, and partial areas of the conductive bonding pads are exposed out of the hollowed-out areas of the balance sheet.
6. The semiconductor device according to claim 5, wherein the balance sheet is provided on the second surface of the substrate by soldering or bonding.
7. The semiconductor device according to any one of claims 5 to 6, wherein the balance sheet is a silicon ceramic sheet.
8. The semiconductor device according to claim 5, wherein the first semiconductor chip is a silicon-based optical chip.
9. The semiconductor device of claim 5, wherein the second solder structure comprises a conductive bump and a solder layer on the conductive bump.
10. A method of manufacturing a semiconductor device, wherein the semiconductor device includes a substrate and a first semiconductor chip; the manufacturing method comprises the following steps:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite;
providing a first semiconductor chip, and welding the first semiconductor chip to the first surface of the substrate;
and controlling the deformation of the substrate by using deformation control equipment, wherein the deformation control equipment comprises a first part and a second part, the first surface of the substrate is contacted with the first part of the deformation control equipment and the second surface of the substrate is contacted with the second part of the deformation control equipment in at least one time period in the process of welding the first semiconductor chip to the substrate, and the first part and the second part simultaneously generate acting force to the substrate so as to reduce the deformation of the substrate.
11. The manufacturing method according to claim 10,
providing a second semiconductor chip, and welding the second semiconductor chip to the first semiconductor chip on the side opposite to the substrate.
12. The method of manufacturing of claim 11, wherein the method comprises: after soldering the first semiconductor chip onto the substrate and/or after soldering the second semiconductor chip onto a side of the first semiconductor chip facing away from the substrate, the deformation control device is brought out of contact with the substrate.
13. The manufacturing method according to claim 10,
the first part of the deformation control device comprises a plurality of opening structures, and the plurality of opening structures and the first surface of the substrate jointly form an accommodating space for accommodating a plurality of first semiconductor chips.
14. The method of any of claims 10-13, wherein during the simultaneous application of force to the substrate by the first portion and the second portion to reduce deformation of the substrate,
the second part bears the load of the substrate, and the contact area of the first part and the substrate accounts for more than 10% of the area of the substrate.
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