CN113794357B

CN113794357B - Fault processing circuit, chip, intelligent power module and household appliance

Info

Publication number: CN113794357B
Application number: CN202110863561.4A
Authority: CN
Inventors: 兰昊; 苏宇泉
Original assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd
Current assignee: Midea Group Co Ltd; Guangdong Midea White Goods Technology Innovation Center Co Ltd
Priority date: 2021-07-29
Filing date: 2021-07-29
Publication date: 2024-11-22
Anticipated expiration: 2041-07-29
Also published as: CN113794357A

Abstract

The application discloses a fault processing circuit, a chip, an intelligent power module and a household appliance, wherein the fault processing circuit comprises a detection circuit, a fault recovery time circuit and a logic control circuit, and the detection circuit is used for detecting the fault of the circuit and outputting a control signal; the fault recovery time circuit is connected with the detection circuit and is configured to input a power supply signal and output a first detection signal according to the power supply signal and the control signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and is used for amplifying current flowing through the first resistor; and the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal. By the mode, the fault recovery time can be prolonged, and the loss in the fault time recovery circuit is reduced.

Description

Fault processing circuit, chip, intelligent power module and household appliance

Technical Field

The application relates to the technical field of circuits, in particular to a fault processing circuit, a chip, an intelligent power module and a household appliance.

Background

At present, the chip is integrated with the functions of overcurrent protection, overtemperature protection, undervoltage protection, input interlocking, fault output, soft shutdown and the like. The fault output pulse width (i.e., fault recovery time t _FLTCLR) is typically determined by the resistance R and capacitance C of the RCIN port, which are located external to the chip. In order to reduce the number of intelligent power template package components and reduce IPM package complexity, R and C need to be integrated into the chip. In general, the resistance of resistor R may be increased to extend the fault recovery time, but this results in almost all of the current flowing through resistor R, making the fault time recovery circuit more lossy at R.

Disclosure of Invention

The application mainly provides a fault processing circuit, a chip, an intelligent power module and a household appliance, which can solve the problem of short fault recovery time in the prior art and reduce the loss in the fault time recovery circuit.

To solve the above technical problem, a first aspect of the present application provides a fault processing circuit, including: the detection circuit is used for detecting circuit faults and outputting control signals; a fault recovery time circuit connected to the detection circuit and configured to input a power signal for outputting a first detection signal in accordance with the power signal and the control signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and is used for amplifying current flowing through the first resistor; and the logic control circuit is connected with the fault recovery time circuit and is used for outputting a fault signal according to the first detection signal.

In order to solve the technical problem, a second aspect of the present application provides a chip, which includes a control circuit and the foregoing fault processing circuit, where the fault processing circuit is configured to output a fault signal, and the control circuit is connected to the fault processing circuit and configured to start or stop the operation of the chip according to the fault signal.

In order to solve the above technical problems, a third aspect of the present application provides an intelligent power module, which includes the foregoing chip.

In order to solve the technical problem, a fourth aspect of the present application provides a household appliance, which comprises the intelligent power module.

The beneficial effects of the application are as follows: the fault processing circuit comprises a detection circuit, a fault recovery time circuit and a logic control circuit, wherein the detection circuit is used for detecting circuit faults and outputting control signals; the fault recovery time circuit is connected with the detection circuit and is configured to input a power signal for outputting a first detection signal according to the power signal and the control signal; the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and is used for amplifying current flowing through the first resistor, so that the fault recovery time of the fault recovery circuit can be prolonged by increasing the resistance value of the first resistor, and meanwhile, the current flowing through the first resistor is amplified through the current amplifying circuit, so that the loss of the output current of the fault recovery time circuit can be reduced.

Drawings

For a clearer description of the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:

fig. 1 is a schematic diagram of a first embodiment of a driving circuit according to the present application;

FIG. 2 is a schematic diagram of a driving circuit according to a second embodiment of the present application;

FIG. 3 is a schematic diagram of a driving circuit according to a third embodiment of the present application;

fig. 4 is a schematic structural diagram of a fourth embodiment of a driving circuit according to the present application;

fig. 5 is a schematic structural diagram of a fifth embodiment of a driving circuit according to the present application;

fig. 6 is a schematic structural diagram of a sixth embodiment of a driving circuit according to the present application;

fig. 7 is a schematic structural diagram of a seventh embodiment of a driving circuit according to the present application;

FIG. 8 is a schematic diagram of a first embodiment of a fault handling circuit provided by the present application;

FIG. 9 is a schematic diagram of a second embodiment of a fault handling circuit provided by the present application;

FIG. 10 is a schematic diagram of an embodiment of the fail-over time circuit of FIG. 9;

FIG. 11 is a schematic diagram of an embodiment of the filter shaping circuit of FIG. 9;

FIG. 12 is a schematic diagram of an embodiment of a chip according to the present application;

FIG. 13 is a schematic diagram of another embodiment of a chip according to the present application;

FIG. 14 is a schematic diagram of an embodiment of a smart power module according to the present application;

fig. 15 is a schematic view of a structure of an embodiment of a home appliance provided by the present application;

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first" and "second" in the present application are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

Referring to fig. 1 to 3, fig. 1 is a schematic structural diagram of a first embodiment of a driving circuit according to the present application, fig. 2 is a schematic structural diagram of a second embodiment of a driving circuit according to the present application, and fig. 3 is a schematic structural diagram of a third embodiment of a driving circuit according to the present application.

As shown in fig. 1, in the present embodiment, the driving circuit 10 is configured to amplify a control signal output from a control circuit (not shown) so as to drive the power device 13 and realize driving control of the power device 13. The driving circuit 10 may include a switching unit 11 and a driving adjustment unit 12. The switching unit 11 is for outputting a driving signal, and the driving adjustment unit 12 is for adjusting the driving efficiency of the driving circuit 10. The driving adjustment unit 12 includes a first resistor Rg1 and a current amplification circuit 121, a first end of the first resistor Rg1 is connected to the switching unit 11, a first end of the current amplification circuit 121 is connected to the first resistor Rg1, and a second end of the current amplification circuit 121 is connected to the power device 13 for amplifying a current flowing through the first resistor Rg 1.

Wherein the power device 13 may be a power semiconductor device for acting as a power switch. Power semiconductor devices can be divided into three categories, namely diodes (Diode), thyristors (Silicon controlled rectifier) and controllable switches (Controllable switch). The switching state of the diode is controlled by the main circuit (power circuit) itself and is therefore also referred to as passive, uncontrollable switch. Thyristors, also known as thyristors, can be turned on by a low power control signal, but can only be turned off by the main circuit (power circuit) itself and not by the control signal, and are therefore also known as semi-controllable switches. The on and off of the controllable switch can be realized by a low-power control signal. The controllable switches include, for example, GTO (Gate Turn-Off Thyristor), IGCT (INTEGRATED GATE Commutated Thyristors, integrated Gate commutated Thyristor), IGBT (Insulated Gate Bipolar Transistor ), VMOS (vertical conductive V-groove MOS transistor). In some embodiments, the power device 13 may be a controllable switch.

The IGBT is a composite fully-controlled voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor, bipolar Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, insulated gate field effect Transistor), and has the advantages of both high input impedance of the MOSFET and low on-voltage drop of the GTR (Giant Transistor). The GTR saturation voltage is reduced, the current carrying density is high, but the driving current is high; the MOSFET has small driving power, high switching speed, large conduction voltage drop and small current carrying density. The IGBT combines the advantages of the two devices, and has small driving power and reduced saturation voltage. As a mainstream device of the novel power semiconductor device, the IGBT has been widely used in the conventional industrial fields of industry, 4C (communication, computer, consumer electronics, automotive electronics), aerospace, national defense, military and the like, and strategically emerging industrial fields of rail transit, new energy, smart grid, new energy automobiles and the like. The triodes of the IGBT are respectively a G-base electrode, a C-collector electrode and an E-emitter electrode. In this embodiment, the power device 13 is described as an IGBT.

As shown in fig. 2, the switching unit 11 may be configured to input a power supply signal VCC and a control signal, and output a driving signal according to the power supply signal and the control signal. The switching unit 11 may be composed of a transistor, for example, a MOS transistor.

The first input terminal (in) of the switching unit 11 may be connected to a control circuit (not shown) for outputting a control signal to the switching unit 11, the second input terminal of the switching unit 11 may be connected to a power supply, and the power supply may provide a high-level power supply signal. When the switching unit 11 inputs a control signal, the switching unit 11 outputs a driving signal according to the control signal and a power signal to drive the power device 13. The control circuit may be a microprocessor (e.g., MPU), and the control signal may be PWM (Pulse Width Modulation) pulse signals. The power supply voltage of the power supply is, for example, 10 to 15V, and the present embodiment is not limited.

As shown in fig. 2, the driving adjustment unit 12 may connect the switching unit 11 and the power device 13 for processing the driving signal to drive the power device 13 with the processed driving signal. The driving adjustment unit 12 includes a first resistor Rg1 and a current amplification circuit 121, a first end of the first resistor Rg1 is connected to the switching unit 11, a first end of the current amplification circuit 121 is connected to the first resistor Rg1, and a second end of the current amplification circuit 121 is connected to the power device 13 for amplifying a current flowing through the first resistor Rg 1. Alternatively, the first end of the current amplifying circuit 121 may be connected to the first end of the first resistor Rg1, or may be connected to the second end of the first resistor Rg1, as long as the current flowing through the first resistor Rg1 can be amplified.

In some embodiments, as shown in fig. 2, the current amplifying circuit 121 includes a first switching tube T1, a first end of the first switching tube T1 is connected to a first end of the first resistor Rg1, a second end of the first switching tube T1 is connected to the power device 13, and a control end of the first switching tube T1 is connected to a second end of the first resistor Rg 1. The first switching tube T1 can amplify a current flowing through the first resistor Rg 1.

In some embodiments, the current amplifying circuit 121 includes a first capacitor C1, a first end of the first capacitor C1 is connected to a second end of the first resistor Rg1, and a second end of the first capacitor C1 is grounded. The first capacitor C1 and the first resistor Rg1 are used for controlling the gain of the first switching tube T1, that is, controlling the amplification factor of the current flowing through the first resistor Rg1 by the first switching tube T1.

In some embodiments, the amplification factor of the first switching tube T1 is a (a > 1), and then the equivalent capacitance of the first resistor Rg1, the first capacitor C1, the first switching tube T1, and the driving adjustment unit 12 is a×c1. In this embodiment, the current of the control end of the first switching tube T1 is determined by the states of the first resistor Rg1 and the first capacitor C1, so that the current of the control end of the first switching tube T1 can be smaller under the condition of meeting the normal driving condition of the power device 13, so that the first resistor Rg1 can be properly enlarged, the first capacitor C1 can be properly reduced, and the occupied area of the first capacitor C1 and the first resistor Rg1 can be reduced. It will be appreciated that the resistance of the resistor becomes larger and the volume thereof will be reduced, so that the area of the driving circuit 10 can be reduced. The occupation area of the first switching tube T1 is much smaller than that of the gate resistor, so that the occupation area of the drive adjusting unit 12 in the drive circuit as a whole is reduced although the first switching tube T1 is increased.

In some embodiments, the first switching transistor T1 may be a transistor or the like that may implement current amplification. The embodiment takes the first switching tube T1 as a triode for illustration. A transistor, i.e., a semiconductor transistor, also called a bipolar transistor, a transistor, is a semiconductor device that controls a current, and functions to amplify a weak signal into an electric signal having a large amplitude. The triode has base, collector and emitter electrodes, and the current amplification of the triode effectively uses the small change of the base current to control the huge change of the collector current. The triode can be divided into germanium tube and silicon tube according to materials. The triode is characterized in that two PN junctions which are very close to each other are manufactured on a semiconductor substrate, the whole semiconductor is divided into three parts by the two PN junctions, the middle part is a base region, the two side parts are an emitter region and a collector region, and PNP and NPN are arranged. Currently, more transistors are used, silicon NPN and germanium PNP. In this embodiment, the types of the transistors are not limited, and may be NPN transistors made of silicon, for example.

In this embodiment, the first end of the first switching tube T1 is the collector of the triode, the second end of the first switching tube T1 is the emitter of the triode, and the control end of the first switching tube T1 is the base of the triode. The connection relation of the triode and other devices or units is continuously described as follows: the collector of the NPN triode can be connected with the switch unit 11, the emitter of the NPN triode can be connected with the power device 13, the base of the NPN triode can be connected with the first end of the first capacitor C1, and the second end of the first capacitor C1 can be connected with the ground level (namely, grounded). Correspondingly, the first end of the first resistor Rg1 can be connected with the collector electrode of the NPN type triode, the second end of the first resistor Rg1 is connected with the base electrode of the NPN type triode, the first end of the first capacitor C1 is also connected with the base electrode of the NPN type triode, and the second end of the first capacitor C1 is grounded.

In some embodiments, as shown in fig. 2, the switching unit 11 may include a second switching tube T2 and a third switching tube T3. The second switching tube T2 and the third switching tube T3 may be different kinds of switching tubes. For example, the switching characteristics of the second switching tube T2 and the third switching tube T3 may be opposite. The control end of the second switching tube T2 may be connected to a control circuit to input a control signal, the first end of the second switching tube T2 may be connected to a power supply to input a power signal, and the second end of the second switching tube T2 may be connected to the input end of the driving adjustment unit 12. The control end of the third switching tube T3 may be connected to the control circuit, the first end of the third switching tube T3 may be connected to the output end of the driving adjustment unit 12, and the second end of the third switching tube T3 may be grounded. It is understood that the types and parameters (breakdown voltage, power consumption, etc.) of the second switching tube T2 and the third switching tube T3 may be selected according to practical situations, which are not limited herein.

The MOS tube has the advantages of high input impedance, low noise, large dynamic range, small power consumption, easy integration and the like. The MOS tube can comprise an N-type MOS tube (NMOS tube) and a P-type MOS tube (PMOS tube). In some embodiments, the switch unit 11 may be a complementary MOS circuit composed of two tubes, namely, an NMOS tube and a PMOS tube, that is, a CMOS circuit. The second switching tube T2 may be a P-type MOS tube, and the third switching tube T3 may be an N-type MOS tube. It can be appreciated that the embodiment only illustrates the switch unit 11 formed by a pair of MOS transistors, and in other embodiments, the switch unit 11 may include a plurality of pairs of MOS transistors, and may specifically be a plurality of pairs of complementary MOS transistors (P-type MOS transistor and N-type MOS transistor), which will not be described herein.

In some embodiments, as shown in fig. 2, a gate of the PMOS transistor is connected to a control circuit (not shown) to input a control signal, a source of the PMOS transistor is connected to a power supply to input a power supply signal VCC, and a drain of the PMOS transistor is connected to a collector of the triode; the grid electrode of the NMOS tube is connected with the control circuit to input a control signal, and the source electrode of the NMOS tube is connected with the emitter electrode of the triode, so that the NMOS tube is connected with the base electrode of the IGBT, and the drain electrode of the NMOS tube is grounded. When the control signal is at a high level, the PMOS tube is conducted, the source electrode of the PMOS tube is input with a power supply signal VCC, the drain electrode of the PMOS tube outputs a driving signal, a part of current of the driving signal passes through a first resistor Rg1, the first capacitor C1 is charged through the first resistor Rg1, the first end of the first capacitor C1 is connected with the base electrode of the triode, and the second end of the first capacitor C1 is grounded, so that the base current of the triode can be formed after charging for a period of time, the collector electrode and the emitter electrode of the triode are conducted, at the moment, the other part of current of the driving signal is amplified by the triode and then is output to the power device 13, and in particular, the triode can amplify the current by A times (A > 1). Under the condition that the current of the driving signal is unchanged, since the triode passes through a part of current, the first resistor Rg1 passes through a part of current, and compared with the condition that all current directly acts on the first resistor Rg1, the reliability and the service life of the first resistor Rg1 in the driving adjustment unit 12 provided by the embodiment are better.

In some embodiments, as shown in fig. 3, the driving circuit 10 may further include a turn-off unit 14. The first end of the turn-off unit 14 is connected to the first end of the third switching tube T3, and the second end of the turn-off unit 14 is connected to the second end of the first switching tube T1. The shutdown unit 14 is used to adjust the driving efficiency of the driving circuit 10 when the control signal is a low level signal. In some embodiments, the turn-off unit 14 may include a second resistor Rg, off, where a first end of the second resistor Rg, off is connected to a first end of the third switching tube T3, and a second end of the second resistor Rg, off is connected to an output end of the driving adjustment unit 12, which is also a second end of the first switching tube T1.

Specifically, the first end of the second resistor Rg, off may be connected to the source of the NMOS transistor, and the second end of the second resistor Rg, off is connected to the emitter of the NPN transistor. Alternatively, the turn-off unit 14 may include a plurality of second resistors Rg, off, and the plurality of resistors may be connected in parallel and/or series, and the specific connection manner is not limited. For example, the shut-off unit may comprise two second resistances Rg, off, which are connected in parallel and then connected into a circuit.

In some embodiments, as shown in fig. 3, the driving circuit 10 may further include a filtering unit 15, where a first end of the filtering unit 15 is connected to a second end of the current amplifying circuit 121, that is, to a path between the first switching tube T1 and the power device 13, and a second end of the filtering unit 15 is grounded, so as to perform an auxiliary filtering process on a current signal output from an output end of the first switching tube T1.

In some embodiments, as shown in fig. 3, the filtering unit 15 may include a second capacitor C2, where a first end of the second capacitor C2 is connected to a second end of the first switching tube T1, that is, connected between the first switching tube T1 and the IGBT, and a second end of the second capacitor C2 is grounded. In other embodiments, the filtering unit 15 may include a plurality of second capacitors C2, and the plurality of second capacitors C2 may be connected in parallel and/or in series, and the specific connection manner is not limited. For example, the filtering unit 15 may include two, three or four second capacitances C2. In some embodiments, the first capacitor C1 and the second capacitor C2 may be variable capacitors, and specific parameters may be selected according to practical situations.

In the above scheme, the driving circuit comprises a switching unit and a driving adjusting unit, and is used for driving the power device, the switching unit is configured to input a power signal and a control signal, and outputs a driving signal according to the power signal and the control signal, the driving adjusting unit is connected with the switching unit and the power device and is used for amplifying the driving signal so as to drive the power device by using the amplified driving signal, wherein the driving adjusting unit comprises a first resistor and a current amplifying circuit, a first end of the first resistor is connected with the switching unit, a first end of the current amplifying circuit is connected with the first resistor, a second end of the current amplifying circuit is connected with the power device and is used for amplifying current flowing through the first resistor, so that the sizes of the first resistor and the first capacitor can be adjusted, the occupied area of the first resistor and the first capacitor is reduced, normal driving of the power device is realized, and the driving circuit can be integrated in a chip.

Referring to fig. 4 to 7, fig. 4 is a schematic structural diagram of a fourth embodiment of a driving circuit according to the present application, fig. 5 is a schematic structural diagram of a fifth embodiment of a driving circuit according to the present application, fig. 6 is a schematic structural diagram of a sixth embodiment of a driving circuit according to the present application, and fig. 7 is a schematic structural diagram of a seventh embodiment of a driving circuit according to the present application.

The present embodiment and the above embodiments can provide a driving circuit with a smaller occupied area, but compared with the above embodiments, the driving circuit provided in the present embodiment uses a switching transistor in the driving circuit as a resistor (i.e., a gate resistor) on a current path of a driving switch, thereby avoiding designing an additional resistor as the gate resistor in the driving circuit, and further reducing the occupied area of the driving circuit.

The driving circuit can be used for amplifying the control signal output by the control circuit so that the control signal can drive the power device and realize the driving control of the power device. In this embodiment, the driving circuit may include a first switching tube and a second switching tube. The first end of the first switching tube is configured to input a power supply signal, the first end of the second switching tube is connected with the second end of the first switching tube, and the second end of the second switching tube is connected with the power device; wherein the control terminal of one of the first switching tube and the second switching tube is configured to input a control signal as a driving switch, and the other of the first switching tube and the second switching tube 22 is configured to act as a resistor on the driving switch current path when the driving switch is turned on.

It can be appreciated that the driving circuit may include a plurality of switching tubes, where the plurality of switching tubes may be operated as driving switches in a time-sharing manner, that is, there are one or more idle switching tubes that are not operated in a certain period of time, and in this embodiment, the idle switching tubes are utilized as gate resistors, so as to fully utilize the switching tubes in the driving circuit and reduce the occupied area of the gate resistors in the driving circuit.

As shown in fig. 4 and 5, in the present embodiment, the driving circuit 20 may include a first switching tube 21 and a second switching tube 22, wherein the first switching tube 21 is a driving switch, a control signal is input to a control terminal of the first switching tube 21, a power signal is input to a first terminal of the first switching tube 21, and a second terminal of the first switching tube 21 is used for outputting a driving signal to drive the power device 25 with the driving signal; the second switching tube 22 connects the second end of the first switching tube 21 and the signal output end to serve as a resistor on the current path of the first switching tube 21 when the first switching tube 21 is turned on. At this time, the second switching tube 22 is in an on state when the first switching tube 21 is turned on. In this embodiment, the description of the power device 25 may refer to the corresponding positions of the above embodiments, and the description will be made below taking the power device 25 as an IGBT as an example.

In other embodiments, the first switching tube 21 and the second switching tube 22 may be interchanged, i.e. the second switching tube 22 may act as a driving switch, and the first switching tube 21 acts as a resistor on the current path of the first switching tube 21 when the first switching tube 21 is turned on. Specifically, the first switching tube 21 may be used as a resistor switch at this time, the first end of the first switching tube 21 inputs a power signal, the second end of the first switching tube 21 is connected to the first end of the second switching tube 22, the control end of the second switching tube 22 is used for inputting a control signal, the second end of the second switching tube 22 is connected to the signal output end, and the second switching tube 22 may output a driving signal according to the control signal. At this time, the first switching tube 21 is in an on state when the second switching tube 22 is turned on.

When the first switching tube 21 is a driving switch, the number of the second switching tubes 22 may be plural, and the plural second switching tubes 22 are connected in series. It will be appreciated that the number of the second switching tubes 22 may be selected according to the required gate resistance, and when there are a plurality of second switching tubes 22, a connection manner of the plurality of second switching tubes 22 may be designed, for example, a plurality of switching tubes may be connected in series and/or parallel, so as to obtain the required gate resistance. In other embodiments, when the second switching tube 22 is a driving switch, the number of the first switching tubes 21 may be plural, and the plural first switching tubes 21 may be connected in series and/or parallel. Next, this embodiment will be further described by taking the first switching tube 21 as an example of a drive switch.

In some embodiments, the first switch 21 may be a P-type transistor (e.g., a P-type MOS transistor), the control terminal of the first switch 21 may be a gate of the P-type transistor, the first terminal of the first switch 21 may be a source of the P-type transistor, and the second terminal of the first switch 21 may be a drain of the P-type transistor. The gate of the P-type transistor may be connected to a control circuit (not shown) to input a control signal, the source of the P-type transistor may be connected to a power supply to input a power supply signal (VBX or VCC), and the drain of the P-type transistor may be connected to the second switching transistor 22 to output a driving signal from the signal output terminal out through the second switching transistor 22. The base G of the IGBT is connected to the signal output terminal out to obtain a driving signal output from the signal output terminal out.

In some embodiments, as shown in fig. 5, the driving circuit 20 further includes a third switching tube 23, and the first switching tube 21 and the third switching tube 23 each function as a driving switch. Wherein the switching characteristics of the first switching tube 21 and the third switching tube 23 are opposite. A first end of the first switching tube 21 may input a power signal, a second end of the first switching tube 21 is used for outputting a driving signal, and a control end of the first switching tube 21 may input a control signal; the first end of the third switching tube 23 is connected with the signal output end out, and the second end of the third switching tube 23 is connected with the ground level, namely the ground; the control terminal of the third switching tube 23 inputs a control signal as a driving switch.

In some embodiments, as shown in fig. 5, the driving circuit 20 further includes a fourth switching tube 24, wherein the switching characteristics of the second switching tube 22 and the fourth switching tube 24 are also opposite. The first end of the second switching tube 22 is connected to the second end of the first switching tube 21, the second end of the second switching tube 22 is connected to the signal output end out, the first end of the fourth switching tube 24 is connected to the signal output end out, and the second end of the fourth switching tube 24 is connected to the first end of the third switching tube 23. The second switching tube 22 and the fourth switching tube 24 can be used as resistors in a circuit where the driving switch is located in a conducting state, so as to play a role in adjusting the driving efficiency.

In some embodiments, the second switching tube 22 and/or the fourth switching tube 24 may be in a normally open state, i.e., in a constantly on state. The second switching tube 22 may be in a normally open state, for example, the second switching tube 22 may be a P-type transistor, and a control terminal of the second switching tube 22 is grounded, where the second switching tube 22 is in a normally open state. In some embodiments, the fourth switching tube 24 may be in a normally-on state, for example, the fourth switching tube 24 is an N-type transistor, and the control terminal of the fourth switching tube 24 inputs a power signal, where the fourth switching tube 24 is in a normally-on state.

In other embodiments, the second switching tube 22 and/or the fourth switching tube 24 may be in a very open state, for example, the control ends of the second switching tube 22 and/or the fourth switching tube 24 are connected to a control circuit (not shown) to input a control signal, and are turned on or turned off according to the control signal. The second switch 22 may be a P-type transistor, and a gate of the P-type transistor is connected to the control circuit to input a control signal; the fourth switching transistor 24 is an N-type transistor, and a gate input of the N-type transistor is connected to the control circuit to input a control signal. When the first switching tube 21 and the second switching tube 22 are each turned on, correspondingly, the second switching tube 22 and the fourth switching tube 24 are also turned on, forming a resistance, and otherwise, the second switching tube 22 and the fourth switching tube 24 may be in an off state.

In the related art, the driving circuit 20 includes a plurality of gate resistors, so as to change the number of gate resistors in the access circuit according to the requirements of different application scenarios, thereby adjusting the resistance of the gate resistors in the access circuit. In general, a gate resistor having a small resistance is usually connected in parallel to a plurality of gate resistors, and it is understood that the resistance after the parallel connection is lower than any one of the resistors. However, the arrangement of a plurality of gate resistors occupies a large area of the driving circuit 20. In addition, the temperature and current capability requirements of the resistors in the drive circuit 20 are high.

Therefore, in this embodiment, the first switching tube 21 and the second switching tube 22 in the driving circuit 20 in the idle state are connected in series, and the third switching tube 23 and the fourth switching tube 24 are connected in series and serve as the resistors on the driving switch path when being turned on, so that the additional setting of the gate resistors in the driving circuit 20 can be avoided, in addition, the number of the second switching tube 22 and/or the fourth switching tube 24 in the access circuit can be selected, so that the resistance of the gate resistors combined by the second switching tube 22 and/or the fourth switching tube 24 in the access circuit can be adjusted according to the requirements of different application scenarios, and the operation is convenient and the cost is low.

In some embodiments, as shown in fig. 6, the driving circuit 20 may further include a first resistor Rg1, where the first resistor Rg1 connects the driving switch (the first switching tube 21 or the second switching tube 22) and the signal output terminal out. When the number of the second switching tubes 22 that can be used as resistors in the driving circuit 20 is small, that is, the resistance of the gate resistor formed by the plurality of second switching tubes 22 is small, the first resistor Rg1 can be set in the driving circuit 20, and the first resistor Rg1 is connected in series with the second switching tubes 22, so that when the number of the second switching tubes 22 is insufficient, the requirement of high-resistance gate resistor can be met in the access circuit.

In some embodiments, as shown in fig. 7, the driving circuit 20 may further include a first resistor Rg1 and a second resistor Rg2, where a first end of the first resistor Rg1 is connected to a second end of the second switch tube 22, a second end of the first resistor Rg1 is connected to the signal output out, a first end of the second resistor Rg2 is connected to the signal output out, and a second end of the second resistor Rg2 is connected to a first end of the fourth switch tube 24, that is, the first resistor Rg1 and the second resistor Rg2 are respectively disposed in a charging circuit for charging and a discharging circuit for discharging, that is, a current passes through the first resistor Rg1 during charging and a current passes through the second resistor Rg2 during discharging.

In some embodiments, the first switching tube 21 and the second switching tube 22 are the same switching tube, and/or the third switching tube 23 and the fourth switching tube 24 are the same switching tube. For example, the first switching tube 21 and the second switching tube 22 may be PMOS tubes, and the third switching tube 23 and the fourth switching tube 24 may be NMOS tubes. It can be understood that the same type of switch is convenient for calculating the resistance of the grid resistor when calculating the resistance, and is convenient for adjusting the switching tube to form the resistor with the target resistance. The same type of switch is the same type and resistance of the switch tube.

In the above scheme, the driving circuit of the present application is used for driving the power device, and the driving circuit includes: a first switching tube, a first end of which is configured to input a power signal; the first end of the second switching tube is connected with the second end of the first switching tube, and the second end of the second switching tube is connected with the power device; the control end of one switching tube of the first switching tube and the second switching tube is configured to input a control signal to serve as a driving switch, and the other switching tube of the first switching tube and the second switching tube is configured to serve as a resistor on a driving switching current path when the driving switch is turned on. Therefore, the first switching tube or the second switching tube in the driving circuit is configured to be used as the resistor on the current path of the driving switch when the driving switch is turned on, so that the additional arrangement of the grid resistor in the driving circuit can be avoided, and the area of the driving circuit can be reduced.

Further, by adjusting the switching tube to be a resistor, it is mature that the switching tube is consistent with the driving switch as a core part of the driving circuit due to its temperature performance and current capability.

Referring to fig. 8 to 11, fig. 8 is a schematic diagram of a first embodiment of a fault handling circuit according to the present application, fig. 9 is a schematic diagram of a second embodiment of a fault handling circuit according to the present application, fig. 10 is a schematic diagram of an embodiment of a fault recovery time circuit in fig. 9, and fig. 11 is a schematic diagram of an embodiment of a filter shaping circuit in fig. 9.

At present, the chip is integrated with the functions of overcurrent protection, overtemperature protection, undervoltage protection, input interlocking, fault output, soft shutdown and the like. The fault output pulse width (i.e., fault recovery time) is typically determined by the resistor R and capacitor C of the RCIN ports, and the fault recovery time is calculated as follows:

t_FLTCLR＝-(R·C)·In(1-V_RCIN+/VCC)，

wherein, V _RCIN+ fault recovery threshold voltage, VCC supply voltage, t _FLTCLR fault recovery time, R is the resistance value of the resistor, C is the capacitance value of the capacitor.

For example, when c=1nf, r=2.2mΩ, V _RCIN+ =8v, vcc=15v, t _FLTCLR =1.68 ms can be obtained.

Typically, the resistor R and the capacitor C are located outside the chip. To reduce the number of intelligent power template package components and reduce IPM package complexity, R and C may be integrated into the chip, but in order to bring t _FLTCLR within a suitable range, the R and C sizes need to be designed. In general, the capacitance of the capacitor in the fault recovery time circuit is relatively large, for example, when c=1nf, and the capacitance integrated in the chip is usually at most ten pF, if the capacitance of the pF level is used in the fault recovery time circuit, it is difficult for t _FLTCLR to achieve ms level, typically within several tens of us, and such t _FLTCLR is relatively short, which is unfavorable for the back-end control circuit to react. When the resistance value of R in the fault recovery time circuit is increased, almost all the current flows through R, and loss occurs. Thus, the present application provides a fault handling circuit that can extend fault recovery times, for example to the millisecond level. It is understood that t _FLTCLR may be determined by at least one of R and C.

In the present embodiment, the fault handling circuit 30 may include a detection circuit 31, a fault recovery time circuit 32, and a logic control circuit 33.

The detection circuit 31 is for detecting a circuit failure and outputting a control signal. For example, when the detection circuit 31 detects an overcurrent signal, it indicates that an overcurrent has occurred in the chip, and thus outputs a control signal for stopping the operation of the chip, thereby realizing an overcurrent protection function of the chip.

In some embodiments, as shown in fig. 9, the detection circuit 31 may include a comparator, a first input terminal of the comparator is used for inputting a signal to be detected, a second input terminal of the comparator is used for inputting a reference signal, and an output terminal of the comparator is used for outputting a control signal.

Wherein a comparator (comparator) may compare two or more data items to determine if they are equal, or to determine the size relationship and ordering between them. Typically, the comparator has five pins, namely a "-" input pin, a "+" input pin, an output pin, a positive side power pin, and a negative side power pin. The positive side power pin may be connected to a power source and the negative side power pin may be grounded. Any input pin can be selected as a reference pin to fix voltage, the difference between the reference voltage and the voltage input to the other pin is amplified, and high level or low level is output. In this embodiment, the output terminal of the comparator may be an output pin, the positive side power pin may be connected to a power supply to input the power supply voltage VCC, and the negative side power pin may be grounded GND.

In this embodiment, as shown in fig. 9, the first input terminal of the comparator may be a "-" input pin, the second input terminal of the comparator may be a "+" input pin, i.e., the "+" input pin is selected as the reference terminal, and when the potential of the signal to be detected input by the "-" input pin is greater than the potential of the reference signal, the output terminal of the comparator outputs a low level signal (e.g., 0V), otherwise, the output terminal of the comparator outputs a high level signal. It can be understood that when the potential of the signal to be detected is greater than the potential of the reference signal, it is indicated that an overcurrent phenomenon occurs at this time, so that a low-level signal needs to be output to enable the logic control circuit 33 to output a low-level fault signal as well, and the fault signal can be output to the control circuit at the rear end, so that the control circuit can control the chip to stop working, and further the chip is protected from being damaged. When the fault is recovered, the potential of the signal to be detected is smaller than that of the reference signal, the output end of the comparator outputs a high-level signal to the fault recovery time circuit 32, after the fault recovery time circuit 32 carries out delay processing, the comparator outputs a first detection signal to the logic control circuit 33, so that the logic control circuit 33 outputs a high-level fault signal, and the back-end control circuit can control the chip to start working according to the high-level fault signal.

In some embodiments, the detection circuit 31 may further include a bootstrap capacitor (not shown), where a first end of the bootstrap capacitor is connected to the second input of the comparator, so as to input the reference signal to the comparator, and a second end of the bootstrap capacitor is grounded. Optionally, the voltage of the bootstrap capacitor is 0.5V.

In some embodiments, as shown in fig. 9, the detection circuit 31 may further include an ESD (electrostatic discharge ) protection circuit. The input end of the ESD protection circuit is used for inputting a signal to be detected, and the output end of the ESD protection circuit is connected with the first input end of the comparator and is used for inputting the signal to be detected into the comparator for comparison. The ESD protection circuit may further include a positive side power supply pin to which a power supply may be connected to input the power supply voltage VCC, and a negative side power supply pin to which the ground GND may be connected.

Specifically, a first terminal of the ESD protection circuit may be connected ITRIP to the input port, and the ITRIP input port may output a signal to be detected to the ESD protection circuit.

The integrated circuit device works within a certain limited range of voltage, current and power consumption, a large amount of accumulated static charges can generate high-voltage discharge under proper conditions, and the static discharge is instantaneously transmitted through high voltage of a device lead, so that an oxide layer can be disconnected, and the device is abnormal in function. Among these, the generation causes of static electricity may be triboelectrification, induction electrification, and contact electrification. Specifically, the ESD protection circuit may include an ESD protection diode for preventing static electricity from affecting the inside of the detection circuit 31. The ESD protection diode is a new type of integrated electrostatic protection device, and the inside of the ESD protection diode is a zener diode, and when the input current exceeds its rated voltage, the ESD protection diode breaks down, and the excessive electric energy is led back to the ground, so as to play a role of protecting a circuit. The ESD protection diode may be a transient suppression diode that uses the reverse breakdown principle of the P-N junction to conduct the static electricity to ground, thereby functioning as a protection circuit. Optionally, the ESD protection circuit may also use other elements or combinations of elements to implement ESD protection, which is not limited in this embodiment.

As shown in fig. 10, the fault recovery time circuit 32 may be connected to the detection circuit 31 and configured to input a power signal for outputting a first detection signal according to the power signal and the control signal. The fault recovery time circuit 32 includes a first resistor R1, a first capacitor C1, and a current amplifying circuit 3221, where the current amplifying circuit 3221 is connected to the first resistor R1 and the first capacitor C1, and is configured to amplify a current flowing through the first resistor R1, so that the fault recovery time of the fault recovery circuit 21 can be prolonged by increasing a resistance value of the first resistor R1, and meanwhile, the current flowing through the first resistor R1 is amplified by the current amplifying circuit 3221, so that a loss of the current output by the fault recovery time circuit 32 can be reduced.

In some embodiments, the fault recovery time circuit 32 may include a first switching unit 321, a delay unit 322, and a first shaping unit 323. The first switching unit 321 may be configured to input a control signal and a power signal, and output a first detection signal according to the control signal and the power signal. The delay unit 322 may be connected to the first switch unit 321, and is configured to delay the first detection signal. The delay unit 322 may include a resistor R1, a first capacitor C1, and a current amplifying circuit 3221, where a first end of the first resistor R1 is connected to the first switch unit 321, a first end of the first capacitor C1 is connected to a second end of the first resistor R1, a second end of the first capacitor C1 is grounded, and a first end of the current amplifying circuit 3221 is connected to the first end of the first resistor R1, for amplifying a current flowing through the first resistor R1. The first shaping unit 323 is connected to the delay unit 322 and the logic control circuit 33, and is configured to perform shaping processing on the first detection signal.

As shown in fig. 10, specifically, a first end of the first switching tube T1 may be connected to a first end of the first resistor R1, a second end of the first switching tube T1 may be connected to the first shaping unit 323, and a control end of the first switching tube T1 is connected to a second end of the first resistor R1. The first switching tube T1 can play a role in current amplification. If the amplification factor of the first switching tube T1 is a (a > 1), the equivalent capacitance of the delay unit formed by the first switching tube T1, the first capacitor C1 and the first resistor R1 is a×c1, and the capacitance is larger, so that the delay effect is correspondingly better. In this embodiment, the current of the control terminal of the first switch tube T1 is determined by the states of the first capacitor C1 and the first resistor R1, so that the current of the control terminal of the first switch tube T1 can be relatively small, and the first resistor R1 is also a filter resistor, so that the first resistor R1 can be properly enlarged, the first capacitor C1 can be properly reduced, and the occupied area of the first capacitor C1 and the first resistor R1 can be reduced. It will be appreciated that the resistance of the resistor will be greater and its volume will be smaller, so the area of the fault handling circuit 30 will be smaller. The occupied area of the first switching tube T1 is far smaller than that of the driving resistor.

In this embodiment, the first end of the first switching tube T1 is the collector of the triode, the second end of the first switching tube T1 is the emitter of the triode, and the control end of the first switching tube T1 is the base of the triode. The connection relation of the triode and other devices or units is continuously described as follows: the collector of the NPN transistor may be connected to the first end of the first resistor R1, the emitter of the NPN transistor may be connected to the first shaping unit 323, the base of the NPN transistor may be connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 may be connected to a ground level (i.e., grounded). Correspondingly, the first end of the first resistor R1 can be connected with the collector electrode of the NPN type triode, the second end of the first resistor R1 is connected with the base electrode of the NPN type triode, the first end of the first capacitor C1 is also connected with the base electrode of the NPN type triode, and the second end of the first capacitor C1 is grounded.

Alternatively, the first switching unit 321 may be composed of a switching tube, such as a MOS tube.

In some embodiments, as shown in fig. 10, the first switching unit 321 may include a second switching tube T2 and a third switching tube T3. The second switching tube T2 and the third switching tube T3 may be different kinds of switching tubes. For example, the switching characteristics of the second switching tube T2 and the third switching tube T3 may be opposite. The control end of the second switching tube T2 is connected to the detection circuit 31 to input a control signal, the first end of the second switching tube T2 is connected to the power supply to input a power signal, and the second end of the second switching tube T2 is connected to the input end of the delay unit 322 to output a first detection signal to the delay unit 322 according to the control signal. The control end of the third switching tube T3 is connected with the detection circuit 31 to input a control signal, the first end of the third switching tube T3 is connected with the output end of the delay unit 322, and the second end of the third switching tube T3 is grounded. It is understood that the types and parameters (breakdown voltage, power consumption, etc.) of the second switching tube T2 and the third switching tube T3 may be selected according to practical situations, which are not limited herein.

The MOS tube has the advantages of high input impedance, low noise, large dynamic range, small power consumption, easy integration and the like. The MOS tube can comprise an N-type MOS tube (NMOS tube) and a P-type MOS tube (PMOS tube). In some embodiments, the first switching unit 321 may be a complementary MOS circuit composed of two tubes, i.e., a NMOS tube and a PMOS tube, i.e., a CMOS circuit. The second switching tube T2 may be a P-type MOS tube, and the third switching tube T3 may be an N-type MOS tube.

In some embodiments, the gate of the PMOS transistor is connected to the detection circuit 31 to input a control signal, the source of the PMOS transistor is connected to the power supply to input a power supply signal VCC, and the drain of the PMOS transistor is connected to the collector of the triode; the gate of the NMOS transistor is connected to the detection circuit 31 to input a control signal, the source of the NMOS transistor is connected to the emitter of the triode, and is connected to the first end of the first shaping unit 323, and the drain of the NMOS transistor is grounded. When the control signal is at a high level, the PMOS tube is conducted, the source electrode of the PMOS tube is input with a power supply signal VCC, the drain electrode of the PMOS tube outputs a first detection signal, a part of current of the first detection signal passes through a first resistor R1, the first resistor R1 charges a first capacitor C1, the first end of the first capacitor C1 is connected with the base electrode of the triode, the second end of the first capacitor C1 is grounded, so that the base current of the triode can be formed after charging for a period of time, the collector electrode and the emitter electrode of the triode are conducted, at the moment, the other part of current of the first detection signal is amplified by the triode and then is output to a first shaping unit 323, and in particular, the triode can amplify the current by a times (A > 1). Under the condition that the current of the driving signal is unchanged, since the triode passes through a part of current, the first resistor R1 passes through a part of current, and compared with the condition that all current directly acts on the first resistor R1, the first resistor R1 in the delay unit 322 provided by the embodiment has better reliability and service life.

In some implementations, the fault recovery time circuit 32 may also include a bias circuit (not shown) and a current control circuit 324. The bias circuit is configured to provide a bias signal, and the current control circuit 324 may be connected to the bias circuit and the first end of the second switching tube T2, and configured to control the current level of the power signal according to the bias signal. Wherein the current value of the paranoid signal is less than the current value of the control signal. Specifically, the current control circuit 324 is configured to reduce the current level of the power signal input to the first switching unit 321, so as to reduce the current level of the first detection signal input to the delay unit 322, and the smaller current may reduce the parameters such as the occupied area of T1, R1, and C1.

In some embodiments, the current control circuit 324 may include a fourth switching tube (not shown), a first end of the fourth switching tube may be connected to a power supply to input a power signal, a second end of the fourth switching tube is connected to a first end of the second switching tube T2, and a control end of the fourth switching tube is connected to a bias circuit to input a bias signal to output the power signal adjusted by the current control circuit 324 to the second switching tube T2 of the first switching unit 321.

In some embodiments, a bias voltage circuit may be included in the comparator, and the bias voltage signal output by the programming circuit may be transmitted to the current control circuit 324 through a blast line to control the magnitude of the current input to the first switching unit 321. The bias circuit may be a mirrored Current source also known as a Current Mirror (Current Mirror). Specifically, the fourth switching tube may be a PMOS tube, and the BLAS line may transmit the paranoid signal output by the programming circuit to the gate of the PMOS tube.

In some embodiments, as shown in fig. 10, the fault recovery time circuit 32 may further include a first filtering unit 325, where a first end of the first filtering unit 325 is connected to an output end of the delay unit 322, and a second end of the first filtering unit 325 is grounded, for performing an auxiliary filtering process on a current signal output from the output end of the delay unit 322.

In some embodiments, the first filtering unit 325 may include a second capacitor C2, where a first end of the second capacitor C2 is connected to a second end of the first switching tube T1, that is, between the first switching tube T1 and the first shaping unit 323, and a second end of the second capacitor C2 is grounded. In other embodiments, the first filtering unit 325 may include a plurality of second capacitors C2, and the plurality of second capacitors C2 may be connected in parallel and/or in series, and the specific connection manner is not limited. For example, the first filtering unit 325 may include two, three, or four second capacitors C2.

The first shaping unit 32325 may be connected to the delay unit 322 and the logic control circuit 33, and is configured to perform shaping processing on the first detection signal, and then output the first detection signal to the logic control circuit 33. The shaping process may include waveform transformation, pulse shaping, pulse amplitude qualification. The waveform transformation is to transform a sine wave into a square wave, the pulse shaping is to correct distortion of the pulse in the transmission process, the pulse amplitude identification is to input the pulses with different amplitudes into the first shaping unit 323, and only the pulse with the amplitude greater than the preset amplitude threshold value can generate a signal at the input end of the first shaping unit 323. When the amplitude of the input pulse is smaller than the preset amplitude threshold, it indicates that the delay unit 322 is in the on state at this time, but the amplitude of the first detection signal output by the delay unit 322 has not yet reached the maximum value, i.e. has not yet stabilized, and at this time, the first shaping unit 323 temporarily does not output the first detection signal to the logic control circuit 33 at the back end.

For example, the preset amplitude threshold may be 8V in this embodiment, when the amplitude of the first detection signal input by the first shaping unit 323 is greater than 8V, the first shaping unit 323 outputs the first detection signal, otherwise, the first detection signal is not output.

In some embodiments, the first shaping unit 323 may include a schmitt trigger, a first terminal of which is connected to the delay unit 322, and a second terminal of which is connected to the logic control circuit 33. The schmitt trigger may include a gate (e.g., a CMOS inverter), a transistor, or a 555 timer. For details, the circuit structure of the schmitt trigger may refer to the related art, and will not be described herein.

The logic control circuit 33 may be connected to the fault recovery time circuit 32 for outputting a fault signal in dependence of the first detection signal. The logic control circuit 33 may specifically include a T flip-flop.

The fault handling circuit 30 may further comprise a filter shaping circuit 34, the filter shaping circuit 34 may be connected to the detection circuit 31 and configured to input a power signal for outputting a second detection signal in dependence of the power signal and the control signal.

In some embodiments, as shown in fig. 11, the filter shaping circuit 34 includes a second switching unit 341, a second filtering unit 342, and a second shaping unit 343. The second switching unit 341 may be configured to input a power signal and a control signal, and output a second detection signal according to the power signal and the control signal. The second filtering unit 342 is connected to the second switching unit 341, and is configured to perform filtering processing on the second detection signal, where the second filtering unit 342 may be an RC circuit. The second shaping unit 343 is connected to the second filtering unit 342 and the logic control circuit 33, and is configured to perform shaping processing on the second detection signal.

In some embodiments, the second filter circuit may include a second resistor R2 and a third capacitor C3, where a first end of the second resistor R2 is connected to the switching unit, a second end of the second resistor R2 is connected to the second shaping unit 343, a first end of the third capacitor C3 is connected to a second end of the second resistor R2, and a second end of the third capacitor C3 is grounded.

In some embodiments, as shown in fig. 11, the second switching unit 341 may include a fifth switching transistor T5 and a sixth switching transistor T6. The fifth switching tube T5 and the sixth switching tube T6 may be different kinds of switching tubes. For example, the switching characteristics of the fifth switching transistor T5 and the sixth switching transistor T6 may be opposite. The control end of the fifth switching tube T5 is connected to the detection circuit 31 to input a control signal, the first end of the fifth switching tube T5 is connected to the power supply to input a power signal, and the second end of the fifth switching tube T5 is connected to the input end of the second filter unit 342 to output a first detection signal to the second filter unit 342 according to the control signal. The control end of the sixth switching tube T6 is connected to the detection circuit 31 to input a control signal, the first end of the sixth switching tube T6 is connected to the output end of the second filtering unit 342, and the second end of the sixth switching tube T6 is grounded. It is to be understood that the types and parameters (breakdown voltage, power consumption, etc.) of the fifth switching tube T5 and the sixth switching tube T6 may be selected according to practical situations, which are not limited herein.

In some embodiments, the fifth switching tube T5 may be a P-type MOS tube, and the sixth switching tube T6 may be an N-type MOS tube. The control end of the fifth switching tube T5 is a grid electrode of the P-type MOS tube, the first end of the fifth switching tube T5 is a source electrode of the P-type MOS tube, and the second end of the fifth switching tube T5 is a drain electrode of the P-type MOS tube; the control end of the sixth switching tube T6 is the grid electrode of the N-type MOS tube, the first end of the sixth switching tube T6 is the source electrode of the N-type MOS tube, and the second end of the sixth switching tube T6 is the drain electrode of the N-type MOS tube.

In some embodiments, the shaping process of the second shaping unit 343 may include waveform transformation, pulse shaping, pulse amplitude qualification. The second shaping unit 343 may include a schmitt trigger, a first terminal of which is connected to the second filtering unit 342, and a second terminal of which is connected to the logic control circuit 33. For the second shaping unit 343, reference may be made to the corresponding position of the first shaping unit 323, which is not described here.

In some embodiments, as shown in fig. 9, logic control circuit 33 may include an RS flip-flop, also known as a reset-set flip-flop. The R input of the RS flip-flop is connected to the filter shaping circuit 34 for inputting a first detection signal, and the S input of the RS flip-flop is connected to the fault recovery time circuit 32 for inputting a second detection signal for outputting a fault signal in accordance with the first detection signal and the second detection signal. The RS flip-flop includes an R input, an S input, a Q output, and a non-Q output. In this embodiment, the output terminal of the logic control circuit 33 is a Q output terminal. Wherein:

the R input end is connected with a low level, when the S input end is connected with the low level, the Q output end outputs 1, and the non-Q output end outputs 1;

the R input end is connected with a low level, the Q output end outputs 0 when the S input end is connected with a high level, and the non-Q output end outputs 1;

The R input end is connected with a high level, the Q output end outputs 1 when the S input end is connected with a low level, and the non-Q output end outputs 0;

The R input end is connected with a high level, and when the S input end is connected with the high level, the Q output end is kept unchanged, and the non-Q output end is kept unchanged.

It can be understood that when the first detection signal is at a high level and the second detection signal is at a low level, it is indicated that no fault or fault recovery occurs in the circuit at this time, and the Q output terminal outputs a high level, so that the circuit can be controlled to work normally according to the fault signal; when the first detection signal is at a low level and the second detection signal is at a high level, the Q output end outputs a fault signal at the low level, which indicates that a fault exists in the circuit, so that the Q output end outputs the low level, and the circuit can be controlled to stop working according to the fault signal; when the first detection signal is at a high level and the second detection signal is at a low level, the Q output end outputs a fault signal at a high level, which indicates that the fault is recovered at the moment, so that the high level can be output to control the circuit to start working according to the fault signal.

It will be appreciated that the RS flip-flop may also include a positive side power supply pin, which may be connected to a power supply to input the supply voltage VCC, and a negative side power supply pin, which may be connected to ground GND.

In the above scheme, the fault processing circuit comprises a detection circuit, a fault recovery time circuit and a logic control circuit, wherein the detection circuit is used for detecting the fault of the circuit and outputting a control signal; the fault recovery time circuit is connected with the detection circuit and is configured to input a power signal for outputting a first detection signal according to the power signal and the control signal; the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and is used for amplifying the current flowing through the first resistor, so that the fault recovery time of the fault recovery circuit can be prolonged by increasing the resistance value of the first resistor, and meanwhile, the current flowing through the first resistor is amplified through the current amplifying circuit, so that the loss of the output current of the fault recovery time circuit can be reduced. Secondly, the first detection signal can be shunted by the current amplifying circuit (the first switching tube), so that the current on the first resistor can be reduced, and the loss in the fault time recovery circuit can be further reduced.

Referring to fig. 12, fig. 12 is a schematic structural diagram of a chip according to an embodiment of the application.

In this embodiment, the chip 40 may include the control circuit 41 and the driving circuit 42 in any of the foregoing embodiments, where the control circuit 41 may provide a control signal for the driving circuit 42, and the driving circuit 42 may output a driving signal according to the control signal to drive the power device. The control circuit 41 is, for example, a microprocessor, the control signal is, for example, PWM (Pulse Width Modulation) pulse signals, and the power device is, for example, an IGBT. For the description of the driving circuit 42, please refer to the corresponding position in the above embodiment, and the description is omitted here.

In some embodiments, the chip 40 may be a high voltage integrated circuit chip (High Voltage Integrated Circuit, HVIC), which is an important component of IPM (INTELLIGENT POWER MODULE, smart power module). HVIC has intelligent protection function and high voltage isolation and power device driving function. The HVIC can convert the low-voltage signal of the MCU into a driving signal capable of driving power devices with different specifications.

In some implementations, the chip 40 may include the driving circuits in the first to third embodiments described above. Currently, the driving circuit integrated in the chip does not include the gate resistor and the driving capacitor, but the gate resistor and the gate resistor are designed outside the chip, which may lead to a complex package, thereby easily introducing parasitic capacitance and parasitic resistance. Since the resistance of the gate resistor is generally small, the area actually occupied by the gate resistor is large, the area of the driving capacitor is also large, and the available area of the chip is limited, so that it is difficult to design the gate resistor and the driving capacitor in the chip. And the resistance of the grid resistor is smaller, so that the current flowing through the grid resistor is higher, and the performance of the chip is affected.

In the above scheme, the chip comprises a control circuit and a driving circuit, the driving circuit comprises a switching unit and a driving adjusting unit, the switching unit is used for driving the power device, the switching unit is configured for inputting a power signal and a control signal, and outputting a driving signal according to the power signal and the control signal, the driving adjusting unit is connected with the switching unit and the power device and is used for amplifying the driving signal so as to drive the power device by using the amplified driving signal, wherein the driving adjusting unit comprises a first resistor and a current amplifying circuit, a first end of the first resistor is connected with the switching unit, a first end of the current amplifying circuit is connected with the first resistor, a second end of the current amplifying circuit is connected with the power device and is used for amplifying the current flowing through the first resistor, and due to the gain effect of the first switching tube, the sizes of the first resistor and the first capacitor can be adjusted, so that the occupied area of the first resistor and the first capacitor is reduced, and normal driving of the power device is realized, and the driving circuit can be integrated in the chip. Secondly, because with first resistance and first electric capacity integrate in the chip, the chip has integrated the function of adjusting grid drive efficiency promptly to can reduce the area occupied by first resistance and first electric capacity, can also reduce parasitic inductance clutter and parasitic capacitance and introduce resonance problem, in addition, can also reduce the electric current of first resistance, promote the reliability life-span of first resistance.

In other embodiments, the chip 40 may include the driving circuits in the fourth to seventh embodiments described above.

In the above scheme, the chip includes a driving circuit, and the driving circuit is used for driving the power device, and the driving circuit includes: a first switching tube, a first end of which is configured to input a power signal; the first end of the second switching tube is connected with the second end of the first switching tube, and the second end of the second switching tube is connected with the power device; the control end of one switching tube of the first switching tube and the second switching tube is configured to input a control signal to serve as a driving switch, and the other switching tube of the first switching tube and the second switching tube is configured to serve as a resistor on a driving switching current path when the driving switch is turned on. Therefore, the first switching tube or the second switching tube in the driving circuit is configured to be used as the resistor on the current path of the driving switch when the driving switch is turned on, so that the additional arrangement of the grid resistor in the driving circuit can be avoided, the area of the driving circuit can be reduced, and the area of a chip can be further reduced.

Referring to fig. 13, fig. 13 is a schematic structural diagram of a chip according to an embodiment of the application.

In this embodiment, the chip 50 includes the fault processing circuit 51 and the control circuit 52 in any of the above embodiments, the fault processing circuit 51 is configured to output a fault signal, and the control circuit 52 is connected to the fault processing circuit 51 and is configured to start or stop the operation of the chip according to the fault signal.

For the description of the fault handling circuit 51 and the control circuit 52 in this embodiment, reference may be made to the corresponding positions in the above-mentioned fault handling circuit embodiments, and details are not repeated here.

In the scheme, the chip comprises a fault processing circuit and a control circuit; the fault processing circuit comprises a detection circuit, a fault recovery time circuit and a logic control circuit, wherein the detection circuit is used for detecting circuit faults and outputting control signals; the fault recovery time circuit is connected with the detection circuit and is configured to input a power signal for outputting a first detection signal according to the power signal and the control signal; the logic control circuit is connected with the fault recovery time circuit and used for outputting a fault signal according to the first detection signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and is used for amplifying the current flowing through the first resistor, so that the fault recovery time of the fault recovery circuit can be prolonged by increasing the resistance value of the first resistor, and meanwhile, the current flowing through the first resistor is amplified through the current amplifying circuit, so that the loss of the output current of the fault recovery time circuit can be reduced. Secondly, the first detection signal can be shunted by the current amplifying circuit (the first switching tube), so that the current on the first resistor can be reduced, and the loss in the fault time recovery circuit can be further reduced.

Referring to fig. 14, fig. 14 is a schematic structural diagram of an embodiment of an intelligent power module according to the present application.

In this embodiment, the intelligent power module 60 (INTELLIGENT POWER MODULE, IPM) may include the chip 61 and the power device 62 in the above embodiment, where the chip 61 is connected to the power device 62, and is used to provide an operating current for the power device 62.

The intelligent power module 60 is a power switching device, which can convert a direct current voltage (current) into an alternating current voltage (current) with variable amplitude and frequency under the action of a control signal, and the output alternating current voltage is loaded on a motor to drive the motor to operate. The intelligent power module 60 is widely applied to variable frequency speed regulation, metallurgical machinery, electric traction, servo drive and variable frequency household appliances due to the advantages of high integration level, good reliability and the like. The IPM is formed by organic package of a high voltage integrated circuit chip (High Voltage Integrated Circuit, HVIC), an insulated gate bipolar transistor (Insulated Gate Bipolar Transistor, IGBT), a fast recovery diode (Fast Recovery Diode, FRD), a power semiconductor device (power device) and other resistive-capacitive devices, and mainly realizes power conversion and real-time protection and communication functions. Wherein the power of IPM is realized by IGBT and FRD, and can provide several a to several hundred a current capability. According to different current and voltage levels, the power device generally adopts an IGBT and a MOSFET.

In some embodiments, the intelligent power module 60 may include 1 or more power devices 62, the number of driving circuits in the chip 61 may correspond to the number of power devices 62, and each driving circuit is correspondingly connected to one power device 62 to provide an operating current for the power device 62. Although one driving circuit and one power device are taken as an example in the present application, the on/off of the plurality of power devices may be controlled by a plurality of driving circuits.

It will be appreciated by those skilled in the art that the intelligent power module not only integrates the power device and the driving circuit, but also integrates an overvoltage protection circuit, an overcurrent protection circuit, an overheat protection circuit, an undervoltage locking circuit and the like. Smart power modules typically use IGBTs or MOSFETs as power devices.

Referring to fig. 15, fig. 15 is a schematic structural diagram of an embodiment of a household appliance according to the present application.

In this embodiment, the household appliance 70 may include one or more of the driving circuit (not shown), the fault handling circuit (not shown), the chip (not shown), and the intelligent power module 71 in the above embodiments, that is, the household appliance 70 may include the driving circuit, the fault handling circuit, the chip, or the intelligent power module 71 alone, may include the driving circuit, the chip, or may include one, two, or three of the driving circuit, the chip, and the intelligent power module 71. In some implementations, the home appliance 70 may include the smart power module 71 in the above-described embodiments.

In some embodiments, the home appliance 70 may be an air conditioner, and the IPM module may be disposed on an electronic control board of the air conditioner. The IPM module may be connected to a main circuit of the air conditioner for DC-AC conversion function. The IPM module can also be used for home appliances 70 such as washing machines, refrigerators, and the like.

The foregoing description is only of embodiments of the present application, and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes using the descriptions and the drawings of the present application or directly or indirectly applied to other related technical fields are included in the scope of the present application.

Claims

1. A fault handling circuit, the fault handling circuit comprising:

The detection circuit is used for detecting circuit faults and outputting control signals;

a fault recovery time circuit coupled to the detection circuit and configured to input a power signal for outputting a first detection signal based on the power signal and the control signal; the fault recovery time circuit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the current amplifying circuit is connected with the first resistor and the first capacitor and is used for amplifying current flowing through the first resistor;

the logic control circuit is connected with the fault recovery time circuit and is used for outputting a fault signal according to the first detection signal;

The detection circuit comprises a comparator and an ESD protection circuit, wherein a second input end of the comparator is used for inputting a reference signal, an output end of the comparator is used for outputting the control signal, an input end of the ESD protection circuit is used for inputting a signal to be detected, and an output end of the ESD protection circuit is connected with a first input end of the comparator.

2. The fault handling circuit of claim 1, wherein the fault recovery time circuit comprises:

a first switching unit configured to input the power signal and the control signal and output the first detection signal according to the power signal and the control signal;

The delay unit comprises a first resistor, a first capacitor and a current amplifying circuit, wherein the first end of the first resistor is connected with the first switch unit, the first end of the first capacitor is connected with the second end of the first resistor, the second end of the first capacitor is grounded, and the first end of the current amplifying circuit is connected with the first end of the first resistor and is used for amplifying current flowing through the first resistor;

The first shaping unit is connected with the output end of the delay unit and the logic control circuit and is used for shaping the first detection signal.

3. The fault handling circuit of claim 2, wherein the current amplifying circuit comprises:

the first end of the first switch tube is connected with the first end of the first resistor, the second end of the first switch tube is connected with the first shaping unit, and the control end of the first switch tube is connected with the second end of the first resistor.

4. The fault handling circuit of claim 3, wherein the first switching tube is an NPN transistor, a collector of the NPN transistor is connected to the first end of the first resistor, an emitter of the NPN transistor is connected to the first shaping unit, and a base of the transistor is connected to the second end of the first resistor.

5. The fault handling circuit of claim 2, wherein the first switching unit comprises:

The control end of the second switching tube is connected with the detection circuit, the first end of the second switching tube inputs the power signal, and the second end of the second switching tube is connected with the input end of the delay unit;

the control end of the third switching tube is connected with the detection circuit, the first end of the third switching tube is connected with the output end of the delay unit, and the second end of the third switching tube is grounded.

6. The fault handling circuit of claim 5, wherein,

The fault recovery time circuit further includes:

a bias circuit for providing a bias signal;

the current control circuit is connected with the bias circuit and the first end of the second switching tube and is used for controlling the current of the power supply signal according to the bias signal;

wherein the current value of the bias signal is smaller than the current value of the control signal.

7. The fault handling circuit of claim 6, wherein,

The current control circuit comprises a fourth switching tube, the control end of the fourth switching tube is connected with the bias circuit, the first end of the fourth switching tube inputs the power signal, and the second end of the fourth switching tube is connected with the first end of the second switching tube.

8. The fault handling circuit of claim 2, wherein the fault recovery time circuit further comprises a first filter unit having a first end coupled to the output of the delay unit and a second end coupled to ground.

9. The fault handling circuit of claim 1, wherein,

The fault handling circuit further includes:

A filter shaping circuit connected to the detection circuit and configured to input a power signal for outputting a second detection signal in accordance with the power signal and a control signal;

The logic control circuit includes:

And the R input end of the RS trigger is connected with the filter shaping circuit, and the S input end of the RS trigger is connected with the fault recovery time circuit and is used for outputting a fault signal according to the first detection signal and the second detection signal.

10. A chip, comprising: a control circuit and a fault handling circuit as claimed in any one of claims 1 to 9 for outputting a fault signal, the control circuit being connected to the fault handling circuit for switching on or off operation of the chip in dependence on the fault signal.

11. An intelligent power module, comprising: the chip of claim 10.

12. A household appliance, comprising: the intelligent power module of claim 11.