CN113851164A - Operating method and system of phase change memory cell, computer readable storage medium - Google Patents
Operating method and system of phase change memory cell, computer readable storage medium Download PDFInfo
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Abstract
本发明提供了一种相变存储器单元的操作方法及系统、计算机可读存储介质，利用相变材料层在不同操作脉冲下具有不同的晶化比例，且在不同的晶化比例下，相变存储器单元具有不同的阻态，不同的阻态可以表示不同的数据的特性，对相变存储器单元施加预设的操作脉冲，能使得相变材料层相变至相应的晶化比例，以使得所述相变存储器单元存储相应的多位数据，即可以利用相应的操作脉冲对相变存储器单元进行完全编程、部分编程、部分复位或完全复位，进而使得相变存储器单元可以由现有的0或1的单位存储升级为双位或者更多位数据的存储，方案简单，易于实施，成本低。
The present invention provides an operation method and system for a phase-change memory cell, and a computer-readable storage medium. The phase-change material layer has different crystallization ratios under different operation pulses, and under different crystallization ratios, the phase change The memory cells have different resistance states, and different resistance states can represent different data characteristics. Applying a preset operation pulse to the phase change memory cell can make the phase change material layer phase change to a corresponding crystallization ratio, so that all The phase change memory cell stores corresponding multi-bit data, that is, the phase change memory cell can be completely programmed, partially programmed, partially reset or completely reset by using the corresponding operation pulse, so that the phase change memory cell can be changed from the existing 0 or The unit storage of 1 is upgraded to the storage of two or more bits of data, the solution is simple, easy to implement, and low cost.
Description
Technical Field
The present invention relates to the field of phase change memory technologies, and in particular, to a method and a system for operating a phase change memory cell, and a computer-readable storage medium.
Background
Phase Change Material (PCM) memory is a new type of non-volatile memory in which a Phase Change Material can undergo a reversible Phase Change between an amorphous state and a crystalline state when corresponding electrical pulses are applied to its Phase Change memory cells, and exhibits a high resistance state in the amorphous state and a low resistance state in the crystalline state. Therefore, the conventional phase change memory cell in the prior art can realize the unit value storage of binary 0 and 1 by using the high resistance state and the low resistance state of the phase change memory cell.
However, as higher performance products are required, how to make the phase change memory have higher storage density is one of the hot problems studied by those skilled in the art.
Disclosure of Invention
The present invention provides a method and a system for operating a phase change memory cell, and a computer readable storage medium, so as to implement multi-bit value storage of the phase change memory cell without changing the structure of the phase change memory cell, thereby effectively improving the storage density of the phase change memory.
To achieve the above object, the present invention provides a method for operating a phase change memory cell, comprising:
s1: determining a corresponding relation between an operation pulse input into a phase change memory unit and a resistance state of the phase change memory unit, wherein the phase change memory unit comprises a phase change material layer, the phase change material layer has different crystallization proportions under different operation pulses, the phase change memory unit has different resistance states under different crystallization proportions, and correspondingly, the number of data bits and the number of data values stored in the phase change memory unit are different;
and S2, applying a preset operation pulse to the phase change memory cell to enable the phase change material layer to change phase to a corresponding crystallization ratio so as to enable the phase change memory cell to store multi-bit data corresponding to the phase change material layer.
Optionally, the preset operation pulse includes a plurality of different programming pulses and a reset pulse, the number of steps set on a falling edge of each programming pulse is different, and after the programming pulse with the larger number of steps set on the falling edge is applied to the phase change memory cell, the higher the crystallization ratio of the phase change material layer after phase change is, the higher the crystallization ratio corresponding to the programming pulse with the largest number of steps set on the falling edge is 1; the number of steps set on the falling edge of the reset pulse is 0, and after the reset pulse is applied to the phase change memory unit, the phase change memory unit is reset, so that the phase change material layer is completely changed into an amorphous state, and the crystallization ratio is 0.
Optionally, the step of applying a preset operation pulse to the phase change memory cell comprises: applying a reset pulse to the phase change memory unit to enable the phase change material layer of the phase change memory unit to change phase to be 0 in crystallization ratio; and then, applying a programming pulse with a corresponding step number on a falling edge to the phase change memory unit so as to enable the phase change material layer of the phase change memory unit to change phase to a crystallization ratio corresponding to the phase change material layer.
Optionally, the preset operation pulse includes a programming pulse and a plurality of different reset pulses, pulse amplitudes of the different reset pulses are different, and after the reset pulse with the smaller pulse amplitude is applied to the phase change memory unit, a crystallization ratio of the phase change material layer after phase change is higher, and a crystallization ratio corresponding to the reset pulse with the largest pulse amplitude is 0; after the programming pulse is applied to the phase change memory unit, the phase change memory unit is programmed, so that the phase change material layer of the phase change memory unit is completely changed into a crystalline state, and the crystallization ratio is 1.
Optionally, the number of steps provided on the falling edge of the programming pulse is greater than 0.
Optionally, the step of applying a preset operation pulse to the phase change memory cell comprises: applying a programming pulse to the phase change memory unit to enable the phase change material layer of the phase change memory unit to change phase to a crystallization ratio of 1; then, a reset pulse with a corresponding pulse amplitude is applied to the phase change memory cell to cause the phase change material layer of the phase change memory cell to change phase to a crystallization ratio corresponding thereto.
Optionally, the total number of the types of the preset operation pulses is 2n, and the number of the multi-bit binary data that can be stored by the phase change memory cell is 2n, where n is a natural number greater than 1.
Optionally, the operating method further includes: applying a read pulse to the phase change memory cell to read multi-bit binary data stored by the phase change memory cell.
Optionally, the step of reading the multi-bit binary data stored by the phase change memory cell comprises: and utilizing multi-level reading voltage thresholds to carry out bit-by-bit judgment on multi-bit binary data stored in the phase change memory unit, wherein the reading voltage thresholds at all levels are different in size.
Optionally, when the total number of the types of the preset operation pulses is 4, the phase change memory cell stores two-bit binary data, which are 00, 10, 01, and 11; the step of judging the multi-bit binary data stored in the phase change memory unit bit by bit comprises the following steps:
firstly, judging whether the low-order data in the two-bit binary data stored in the phase change memory unit is 0 or 1 through a first-level reading voltage threshold;
if the current voltage of the phase change memory unit is not higher than the first-level reading voltage threshold value, the lower-order data in the binary data stored in the phase change memory unit is 1, and whether the upper-order data in the binary data stored in the phase change memory unit is 0 or 1 is further judged through a second-level reading voltage threshold value;
if the current voltage of the phase change memory unit is higher than the first-level reading voltage threshold value, the lower-order data in the binary data stored in the phase change memory unit is 0, and whether the upper-order data in the binary data stored in the phase change memory unit is 0 or 1 is further judged through another second-level reading voltage threshold value.
Based on the same inventive concept, the present invention further provides an operating system of a phase change memory, wherein a phase change memory cell of the phase change memory has a phase change material layer, the phase change material layer has different crystallization ratios under different operation pulses, and the phase change memory cell has different resistance states under different crystallization ratios, and correspondingly, the phase change memory cell stores different data bits and different values, the operating system includes:
a gating circuit for gating a corresponding phase change memory cell in the phase change memory;
and the erasing circuit is used for applying a preset operation pulse to the gated phase change memory unit to enable the phase change material layer of the phase change memory unit to change the phase to a corresponding crystallization proportion, so that the phase change memory unit stores the corresponding multi-bit data.
Optionally, the preset operation pulse applied by the erase/write circuit includes a plurality of different programming pulses and a reset pulse, the number of steps set on the falling edge of the different programming pulses is different, and after the programming pulse with the larger number of steps set on the falling edge is applied to the phase change memory cell, the crystallization ratio of the phase change material layer after phase change is higher, and the crystallization ratio corresponding to the programming pulse with the largest number of steps set on the falling edge is 1; the step number set on the falling edge of the reset pulse is 0, and after the reset pulse is applied to the phase change memory unit, the phase change memory unit is reset to ensure that the phase change material layer is completely changed into an amorphous state, and the crystallization ratio is 0;
or the preset operation pulse applied by the erasing circuit comprises a programming pulse and a plurality of different reset pulses, the pulse amplitudes of the different reset pulses are different, and after the reset pulse with the smaller pulse amplitude is applied to the phase change memory unit, the crystallization proportion of the phase change material layer after phase change is higher, and the crystallization proportion corresponding to the reset pulse with the largest pulse amplitude is 0; after the programming pulse is applied to the phase change memory unit, the phase change memory unit is programmed, so that the phase change material layer of the phase change memory unit is completely changed into a crystalline state, and the crystallization ratio is 1.
Optionally, the operating system further includes: and the reading circuit is used for applying a reading pulse to the phase change memory unit and reading the multi-bit binary data stored in the phase change memory unit.
Optionally, the read circuit is configured to perform bit-by-bit judgment on the multi-bit binary data stored in the phase change memory cell by using multiple levels of read voltage thresholds, where the read voltage thresholds of the levels are different in size.
Based on the same inventive concept, the present invention also provides a computer-readable storage medium having a computer program or algorithm stored thereon, wherein the computer program or algorithm, when executed by a processor, implements the method for operating the phase change memory cell according to the present invention.
Compared with the prior art, the technical scheme of the invention has at least one of the following technical effects:
1. the phase change memory unit is characterized in that the phase change material layer has different crystallization proportions under the action of different operation pulses, and the phase change memory unit has different resistance states under different crystallization proportions, different resistance states can represent the characteristics of different data, corresponding operation pulses are applied to the phase change memory unit, so that the phase change material layer is subjected to phase change to the corresponding crystallization proportions, the phase change memory unit stores corresponding multi-bit data, namely, the phase change memory unit can be partially programmed or partially reset by using the corresponding operation pulses, and the phase change memory unit can be upgraded from the existing 0 or 1 storage to the storage of double-bit or more-bit data.
2. On the phase change memory unit with the same stack or size, the bit density of the phase change memory unit can be increased by 2 times or more without changing the structure of the phase change memory unit and additional process treatment.
3. The reading scheme is optimized, and the multi-bit data stored by the phase change memory unit can be quickly read out.
4. The scheme is simple, easy to implement and low in cost.
Drawings
Fig. 1 is a schematic structural diagram of a three-dimensional stacked phase change memory.
FIG. 2 is a schematic diagram of pulses during operation of a phase change memory cell.
FIG. 3 is a diagram illustrating the relationship between physical models during a phase change of a phase change memory cell.
FIG. 4 is a graph illustrating resistance change curves of a phase change memory cell during programming and resetting.
FIG. 5 is a graph illustrating crystallization ratios of phase change memory cells under different programming pulses.
FIG. 6 is a schematic diagram of I-V characteristics of a phase change memory cell at different crystallization ratios Ca.
FIG. 7 is a waveform diagram of a predetermined operation pulse applied in the method for operating a phase change memory cell according to the first embodiment of the present invention and a curve diagram of a crystallization ratio Ca corresponding thereto.
FIG. 8 is a graph illustrating a multi-level read voltage threshold versus corresponding operation pulses in a method for operating a phase change memory cell according to a first embodiment of the present invention.
FIG. 9 is a flowchart illustrating a multi-level read in a method of operating a phase change memory cell according to a first embodiment of the present invention.
FIG. 10 is a waveform diagram of a predetermined operation pulse applied in a method for operating a phase change memory cell according to a second embodiment of the present invention and a curve diagram of a crystallization ratio Ca corresponding to the predetermined operation pulse.
Detailed Description
With the continuous increase of the demands of various electronic devices on integration level and data storage density, it is more and more difficult for a common two-dimensional phase change memory device to meet the demands, and under such a situation, three-dimensional (3D) PCM in the prior art is produced. In the conventional 3D PCM, referring to fig. 1, bit lines BL and word lines WL are formed perpendicular to each other, phase change memory cells Cell are formed in self-alignment at intersections of the bit lines BL and the word lines WL, and a plurality of phase change memory cells Cell may be stacked in a direction perpendicular to a substrate to improve the bit density and integration of the 3D PCM.
Referring to fig. 2, for the conventional phase change memory, operation pulses (e.g., light pulses, electric pulses, etc.) with different widths and heights are generally applied to the phase change memory cell, so that a write (Set) operation, a read operation, and an erase (Reset) operation of the phase change memory cell can be realized. Wherein, when a long and medium-intensity programming pulse (i.e. Set pulse) is applied to raise the temperature of the phase-change material layer of the phase-change memory cell below the melting temperature Tm and above the crystallization temperature Tx, and is kept for a period of time to promote crystal nucleus growth, the phase-change material layer of the phase-change memory cell can be switched from an amorphous state (corresponding to a high resistance state) to a crystalline state (corresponding to a low resistance state), and the process of switching the phase-change material layer from the high resistance state ("0" state) to the low resistance state ("1" state) is generally referred to as a Set process (also referred to as a write operation process); after a short and strong Reset pulse (i.e., Reset pulse) is applied to raise the temperature of the phase change material layer of the phase change memory cell above the melting temperature Tm, and then rapid cooling is performed (cooling down), so that the phase change material layer of the phase change memory cell can be converted from the crystalline state to the amorphous state, and a process of converting the phase change material layer from the low resistance state ("1" state) to the high resistance state ("0" state) is usually called a Reset process (also called an erase operation process), and the Reset process and the Set process are mutually reversible processes, so that the typical phase change memory cell uses the crystalline state to represent a unit binary data "1" and uses the amorphous state to represent a unit binary data "0"; reading of data stored in the phase change memory cell can be achieved by measuring the resistance of the phase change memory cell after applying a weak read pulse that does not affect the state of the phase change material layer.
In the existing technical scheme, although the bit density and the integration level of the phase change memory can be greatly improved by using a three-dimensional stacking technology, the requirement of the phase change memory with higher density still cannot be met.
Referring to fig. 3 and 4, the inventors have found that, when applying a corresponding operation pulse to a phase change memory cell, the final resistance state of the phase change memory cell is actually realized by the interaction of an electrical model, a temperature model and a phase change model, wherein the electrical model can represent the I-V characteristics, the resistance and the voltage Vt when reading data of the phase change memory cell, the temperature model can represent the temperature change of the phase change memory cell, and the phase change model can represent the crystallization ratio Ca of the phase change material layer in the phase change memory cell.
Furthermore, the inventors further investigated and found that, referring to fig. 5, for the programming pulse, the crystallization ratio Ca is related to the falling edge of the programming pulse, and the higher the first step disposed on the falling edge, the larger the crystallization ratio Ca. In addition, referring to FIG. 6, I-V characteristic curves of different crystallization ratios Ca are different.
That is to say, the pulse amplitude, the pulse width, the falling edge arrangement manner and the like of the operation pulse jointly determine the crystallization proportion of the phase-change material layer (namely determine the resistance state, the crystallization state and the stored data of the phase-change memory unit), and based on this, a relationship between the input operation pulse, the resistance (namely the resistance state) of the phase-change memory unit and the crystallization proportion of the phase-change material layer is established, so that the phase-change memory unit is partially programmed (or partially written in and partially set) or partially Reset (or partially erased and partially Reset) by applying the appropriate operation pulse, so that the phase-change memory unit is changed from storing binary data of 0 or 1 unit to storing binary data of two or more bits, thereby breaking through the traditional storage modes of '0' and '1', greatly improving the storage density and increasing the storage capacity of the memory, without significantly increasing the size or power consumption of the memory device, etc.
Therefore, the present invention provides an operation method and system for a phase change memory unit and a computer readable storage medium, wherein the phase change memory unit has different crystallization ratios of a phase change material layer of the phase change memory unit under different operation pulses, and the phase change memory unit has different resistance states under different crystallization ratios to correspond to characteristics of storing different data, and the phase change memory unit is enabled to perform phase change to the corresponding crystallization ratio by applying a preset operation pulse to the phase change memory unit to perform partial programming, full programming, partial resetting or full resetting, so as to enable the phase change memory unit to store corresponding multi-bit data.
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
First embodiment
The present embodiment provides an operation method of a phase change memory unit, which can be applied to any existing phase change memory, where each phase change memory unit of the phase change memory has a phase change material layer, the phase change material layer has different crystallization proportions under different operation pulses, and the phase change memory unit where the phase change material layer is located has different resistance states under different crystallization proportions, and correspondingly, the number of data bits and the number of data values stored in the phase change memory unit are different.
Referring to fig. 7, the method for operating the phase change memory cell of the present embodiment includes:
s1: determining a corresponding relation between an operation pulse input into a phase change memory unit and a resistance state of the phase change memory unit, wherein the phase change memory unit comprises a phase change material layer, the phase change material layer has different crystallization proportions under different operation pulses, the phase change memory unit has different resistance states under different crystallization proportions, and correspondingly, the number of data bits and the number of data values stored in the phase change memory unit are different;
s2 applies a predetermined operation pulse to the phase change memory cell to cause the phase change material layer of the phase change memory cell to change phase to a corresponding crystallization ratio, so that the phase change memory cell stores the corresponding multi-bit data.
Specifically, in step S1, a corresponding relationship between an operation pulse input to any phase change memory cell of the phase change memory and a resistance state of the phase change memory cell may be determined through a simulation test or the like, where each phase change memory cell of the phase change memory is the same, each phase change memory cell includes a phase change material layer, the phase change material layer has different crystallization ratios under different operation pulses, and the phase change memory cell in which the phase change material layer is located has different resistance states under different crystallization ratios, and correspondingly, the number of data bits and the number of data values stored in the phase change memory cell are different, so that a method for specifically implementing partial reset (also called partial erase, partial amorphization), total reset (also called total erase, total amorphization) of the phase change memory cell can be obtained, The operation pulse of partial programming (also called partial crystallization) and full programming (also called full crystallization and full crystallization) is used as the preset operation pulse required by step S2 for selection and use in step S2.
The preset operation pulses that can be applied to, programmed and Reset the phase change memory cell in step S2 of this embodiment include three different programming pulses set1, set2, set3 and one Reset pulse Reset, the number of steps set on the falling edge of the programming pulses set1, set2 and set3 is 1, 2 and 3 in sequence, the step number set on the falling edge of the Reset pulse Reset is 0, the pulse amplitudes of the programming pulses set1 and set2 are the same and are all V12, the pulse amplitude of the programming pulse set3 is V13, the pulse amplitude of the Reset pulse Reset is V11, and V12< V13< V11. Further, the pulse widths of the Reset pulse Reset and the program pulses set1, set2, set3 are sequentially increased, W11< W12< W13< W14.
After the Reset pulse Reset is applied to the phase change memory cell, the phase change memory cell can be Reset (or the phase change memory cell can be fully Reset) so that the phase change material layer is completely changed into an amorphous state, the corresponding crystallization ratio Ca is 0, and the resistance value of the phase change memory cell is the highest, that is, the phase change memory cell has the highest resistance state.
When the Reset pulse Reset and the programming pulses set1, set2, and set3 are respectively applied to the phase change memory cells, the phase change memory cells are correspondingly in states of L0, L1, L2, and L3, wherein in the programming pulses set1, set2, and set3, the larger the number of steps set on the falling edge, the higher the crystallization ratio of the phase change material layer of the phase change memory cell after phase change, that is, the crystallization ratios Ca corresponding to the programming pulses set1, set2, and set3 are all greater than 0 and sequentially increased.
In this embodiment, after the programming pulse set3 is applied to the phase change memory cell, the phase change memory cell can be completely programmed (or fully programmed) to make the phase change material layer of the phase change memory cell completely change into a crystalline state, the corresponding crystallization ratio Ca is 1, and at this time, the resistance value of the phase change memory cell is the lowest, that is, the phase change memory cell has the lowest resistance state.
After the programming pulses Set1 and Set2 are applied to the phase change memory cell, respectively, the phase change memory cell can be partially programmed, so that the phase change material layer of the phase change memory cell is partially changed into a crystalline state, but since the number of steps of the falling edge of the program pulse Set1 is less than the number of steps of the falling edge of the program pulse Set2, the degree of crystallinity of the phase change material layer of the phase change memory cell after the phase change is caused by the program pulse set2 is higher than the degree of crystallinity of the phase change material layer of the phase change memory cell after the phase change is caused by the program pulse set1, that is, the crystallization ratio Ca corresponding to the programming pulse set2 is less than 1 but greater than the crystallization ratio Ca corresponding to the programming pulse set2, at this time, the resistance value of the phase change memory cell corresponding to the programming pulse set2 is between the programming pulse set3 and the programming pulse set1, and the resistance value of the phase change memory cell corresponding to the programming pulse set1 is lower than the resistance value of the phase change memory cell corresponding to the Reset pulse Reset.
Therefore, in the present embodiment, the following are defined: the data stored in the phase change memory cell under the Reset pulse Reset is two-bit binary data "00", the data stored in the phase change memory cell under the programming pulse set1 is two-bit binary data "10", the data stored in the phase change memory cell under the programming pulse set2 is two-bit binary data "01", and the data stored in the phase change memory cell under the programming pulse set3 is two-bit binary data "11".
In this embodiment, the operations of operating and writing the phase change memory cell include: firstly, applying a Reset pulse Reset to the phase change memory unit to enable the phase change material layer of the phase change memory unit to change the phase to a crystallization ratio Ca of 0, and realizing the pre-erasing step or the pre-programming step of the phase change memory unit to enable the data stored in the phase change memory unit to be 00; then, a program pulse (one of set1, set2, set 3) having a corresponding step number set on a falling edge is applied to the phase change memory cell to cause the phase change material layer of the phase change memory cell to change phase to a corresponding crystallization ratio Ca, thereby writing data to be stored, for example, "10", "01", or "11", in the phase change memory cell.
The method for operating the phase change memory cell of the present embodiment further includes: and applying a reading pulse to the corresponding phase change memory cell to read the two-bit binary data stored in the phase change memory cell.
In this embodiment, the response value generated after the read pulse is applied to the phase change memory cell is a voltage value, the same read pulse may generate different voltage values when passing through the phase change memory cells with different resistance values, and the phase change memory cell with the higher resistance value may generate a higher voltage value.
Referring to fig. 8 and 9, in particular, in the present embodiment, as described above, when the Reset pulse Reset, the programming pulses set1, set2, and set3 are respectively applied to the phase change memory cell, the two-bit binary data stored in the phase change memory cell are "00", "10", "01", "11", respectively, and therefore the step of performing bit-by-bit judgment on the two-bit binary data stored in the phase change memory cell includes:
first, it is determined whether the lower data of the two-bit binary data stored in the phase change memory cell is "0" or "1" by a first-level read voltage threshold Vread 0. Specifically, if the resistance of the phase change memory cell is low, the current voltage of the phase change memory cell is not higher than the first level read voltage threshold Vread0, and at this time, it may be determined that the lower data of the two-bit binary data stored in the phase change memory cell is "1"; if the resistance of the phase change memory cell is high, the current voltage of the phase change memory cell is higher than the first-level read voltage threshold Vread0, and at this time, it may be determined that the lower data of the two-bit binary data stored in the phase change memory cell is "0";
then, the corresponding second-level read voltage threshold is used to further determine whether the upper data of the two-bit binary data stored in the phase change memory cell is "0" or "1". Specifically, when the lower bit data of the two-bit binary data stored in the phase change memory cell is determined to be "1", it is further determined whether the current voltage of the phase change memory cell is not higher than a second level read voltage threshold Vread1, if the current voltage of the phase change memory cell is not higher than the second level read voltage threshold Vread1, the upper bit data of the two-bit binary data stored in the phase change memory cell is determined to be "1", that is, the two-bit binary data read from the phase change memory cell is "11", and if the current voltage of the phase change memory cell is higher than the second level read voltage threshold Vread1, the upper bit data of the two-bit binary data stored in the phase change memory cell is determined to be "0", that is, the two-bit binary data read from the phase change memory cell is determined to be "01". When the lower bit data in the two-bit binary data stored in the phase change memory cell is judged to be "0", whether the current voltage of the phase change memory cell is not higher than another second-level read voltage threshold Vread2 is further judged, wherein Vread1< Vread0< Vread2, if the current voltage of the phase change memory cell is not higher than the second-level read voltage threshold Vread2, the upper bit data in the two-bit binary data stored in the phase change memory cell is judged to be "1", that is, the binary data read from the phase change memory cell is judged to be "10", and if the current voltage of the two-bit phase change memory cell is higher than the second-level read voltage threshold Vread2, the upper bit data in the two-bit binary data stored in the phase change memory cell is judged to be "0", that is, that the two-bit data read from the phase change memory cell is judged to be "00".
Based on the same inventive concept, the present invention also provides an operating system (not shown) of the phase change memory, which can apply the Reset pulse Reset, the programming pulses set1, set2, set3 and the read pulse to the phase change memory cell of the present embodiment to erase and read the phase change memory cell. The operating system of the embodiment includes: a strobe circuit (not shown), an erase circuit (not shown), and a read circuit (not shown).
The gating circuit is used for gating corresponding phase change memory cells in the phase change memory.
The erasing circuit is used for applying a preset operation pulse (namely one of Reset pulse Reset, programming pulse set1, set2 and set 3) to the gated phase change memory cell so that the phase change material layer of the gated phase change memory cell changes phase to a corresponding crystallization proportion, so that the gated phase change memory cell stores corresponding multi-bit data (namely one of two-bit binary data "11", "01", "10" and "00"), wherein the preset operation pulse is different, the crystallization proportion corresponding to the preset operation pulse is different, the resistance state of the phase change memory cell is different under different crystallization proportions, and correspondingly, the number of bits and the value of the data corresponding to the phase change memory cell are different.
Optionally, the preset operation pulses that can be applied by the erase circuit of this embodiment include Reset pulses Reset, programming pulses set1, set2, and set3, the numbers of steps set on the falling edges of the programming pulses set1, set2, and set3 are all different, and after the programming pulses with the larger number of steps set on the falling edges are applied to the phase change memory cell, the crystallization ratio Ca corresponding to the programming pulse set3 with the largest number of steps set on the falling edge is 1 as the crystallization ratio Ca of the phase change material layer of the phase change memory cell after phase change is higher; the number of steps set on the falling edge of the Reset pulse Reset is 0, and after the Reset pulse Reset is applied to the phase change memory cell, the phase change memory cell is Reset so that the phase change material layer is entirely changed into an amorphous state, and the crystallization ratio Ca is 0.
The read circuit is used for applying a read pulse to the gated phase change memory cell and reading the multi-bit binary data stored by the phase change memory cell. Optionally, the read circuit is configured to perform bit-by-bit judgment on two-bit binary data stored in the gated phase change memory cell by using two levels of read voltage thresholds, where the read voltage thresholds of the levels are different in size.
It should be noted that the erasing circuit can specifically implement the above-mentioned processes of full programming, partial resetting and full resetting, and the reading circuit can specifically implement the above-mentioned data reading process, and will not be described in detail herein.
Furthermore, it should be understood that, before the phase change memory is shipped from a factory, if a simulation test is not performed to give the correspondence between the operation pulse input to the phase change memory cell and the crystallization ratio of the phase change memory cell and the correspondence between the crystallization ratio of the phase change memory cell and the resistance state of the phase change memory cell, a simulation test circuit may be further added to the operating system for performing a simulation test on the phase change memory before the phase change memory is put into use, determining the correspondence between the operation pulse input to the phase change memory cell and the crystallization ratio of the phase change memory cell and the correspondence between the crystallization ratio of the phase change memory cell and the resistance state of the phase change memory cell, and the like, and further determining a preset operation pulse (including parameters of the pulse type, the pulse amplitude, and the like) that can be applied by the erase circuit, for the erase/write circuit to choose from reasonably.
Based on the same inventive concept, the present embodiments also provide a computer-readable storage medium having stored thereon a computer program, which may include code, algorithms, computer-executable instructions, which when executed by a processor, implement the method of operation of the phase change memory cell of the present embodiments and any variations thereof. The computer-readable storage medium can be any medium that can contain, store, communicate, propagate, or transport the instructions. For example, the computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, device, or propagation medium. Specific examples of the computer-readable storage medium include: magnetic storage devices, such as magnetic tape or Hard Disk Drives (HDDs); optical storage devices, such as compact disks (CD-ROMs); a memory, such as a Random Access Memory (RAM) or a flash memory; and/or wired/wireless communication links.
Second embodiment
Referring to fig. 10, the present embodiment provides an operation method of a phase change memory, which is different from the first embodiment in that the preset operation pulses that can be applied to, programmed and Reset the phase change memory cells in step S2 of the present embodiment include three different Reset pulses Reset1, Reset2, Reset3 and a program pulse set, the number of steps set on the falling edge of the Reset pulses Reset1, Reset2 and Reset3 is 0, but the pulse amplitudes of the program pulse set and the Reset pulses Reset1, Reset2 and Reset3 are sequentially increased, that is, V21< V22< V23< V24. In addition, the pulse widths of the Reset pulses Reset1, Reset2, Reset3 are the same and are all W21, and W21 is less than the pulse width W22 of the programming pulse set.
As an example, the number of steps set on the falling edge of the programming pulse set is 3, but the technical solution of the present embodiment is not limited thereto, and in other examples of the present embodiment, the number of steps set on the falling edge of the programming pulse set may be equal to 0, or may be any natural number greater than 0, where the more the number of steps set on the falling edge of the programming pulse set is, the higher the efficiency of phase change of all the phase change material layers of the phase change memory to the crystalline state is.
In this embodiment, after the reset pulse with the larger pulse amplitude is applied to the phase change memory cell, the amorphization ratio (i.e. 1-Ca) of the phase change material layer of the phase change memory cell after phase change is lower, or in other words, after the reset pulse with the smaller pulse amplitude is applied to the phase change memory cell, the crystallization ratio Ca of the phase change material layer of the phase change memory cell after phase change is higher, and the resistance value of the phase change memory cell is lower. Specifically, after the Reset pulse Reset3 is applied to the phase change memory cell, the phase change memory cell can be completely Reset, so that the phase change material layer of the phase change memory cell is completely changed into an amorphous state, the corresponding crystallization proportion Ca is 0, the phase change memory cell is in an L3' state, and the resistance value of the phase change memory cell is the highest; when Reset pulses Reset2 and Reset3 are applied to the phase change memory cell, the phase change memory cell can be partially Reset, so that the phase change material layer is partially changed into an amorphous state, the state of the phase change memory cell after the Reset pulse Reset2 is applied is L2 ', the state of the phase change memory cell after the Reset pulse Reset1 is applied is L1', the crystallization ratio Ca corresponding to the Reset pulse Reset2 is greater than 0 but greater than the crystallization ratio Ca corresponding to the Reset pulse Reset3, at this time, the resistance value of the phase change memory cell corresponding to the Reset pulse Reset2 is between the Reset pulse Reset1 and the Reset pulse 3, and the resistance value of the phase change memory cell corresponding to the Reset pulse 1 is higher than the resistance value of the phase change memory cell corresponding to the programming pulse set; after the programming pulse set is applied to the phase change memory unit, the phase change memory unit is completely programmed, so that the phase change material layer of the phase change memory unit is completely changed into a crystalline state, the crystallization ratio Ca is 1, and the resistance value of the phase change memory unit is the lowest at the moment.
Therefore, in the present embodiment, the following are defined: the data stored in the phase change memory cell under the programming pulse set is two-bit binary data "11", the data stored in the phase change memory cell under the Reset pulse Reset1 is two-bit binary data "01", the data stored in the phase change memory cell under the Reset pulse Reset2 is two-bit binary data "10", and the data stored in the phase change memory cell under the Reset pulse Reset3 is two-bit binary data "00".
In this embodiment, the erasing or writing operation on the phase change memory cell includes: firstly, applying a programming pulse set to the phase change memory unit to enable the phase change material layer of the phase change memory unit to change the phase to the crystallization ratio to be 1, and realizing the pre-programming step of the phase change memory unit, wherein the data stored in the phase change memory unit is '11'; then, a Reset pulse (i.e., one of Reset1, Reset2, and Reset 3) with a corresponding pulse amplitude is applied to the phase change memory cell to change the phase change material layer of the phase change memory cell to a corresponding crystallization ratio Ca, so as to implement partial erasing of the phase change memory cell, thereby updating the stored data of the phase change memory cell to "01", "10", or "00".
The method for operating the phase change memory further includes applying a read pulse to a corresponding phase change memory cell to read the two-bit binary data stored in the phase change memory cell. The data reading process is the same as the data reading process of the first embodiment, so reference may be made to the above description of the relevant parts of the first embodiment, and details are not repeated here.
Based on the same inventive concept, the present embodiment further provides an operating system (not shown) of the phase change memory, which can apply the Reset pulses Reset1, Reset2, Reset3, and the programming pulse set and the read pulse to the phase change memory cell of the present embodiment to erase and read the phase change memory cell. The operating system of the embodiment includes: a strobe circuit (not shown), an erase circuit (not shown), and a read circuit (not shown). The gating circuit is used for gating corresponding phase change memory cells in the phase change memory. The erasing and writing circuit is used for applying a corresponding operation pulse (namely one of Reset pulses Reset1, Reset2, Reset3 and programming pulse set) to the gated phase change memory cell, so that the phase change material layer of the gated phase change memory cell is changed to a corresponding crystallization proportion, and the gated phase change memory cell stores corresponding multi-bit data (namely one of two-bit binary data "11", "01", "10" and "00"), wherein different operation pulses correspond to different crystallization proportions, and the phase change memory cell stores different multi-bit data under different crystallization proportions.
The operating system of this embodiment is substantially the same as the operating system of the first embodiment, and therefore reference may be made to the above description of relevant portions of the first embodiment, which is not repeated herein.
Based on the same inventive concept, the present embodiments also provide a computer-readable storage medium having stored thereon a computer program, which may include code, algorithms, computer-executable instructions, which when executed by a processor, implement the method of operation of the phase change memory cell of the present embodiments and any variations thereof.
It should be noted that, in the above embodiments, there are only 4 (or 4, or 2) operation pulses for erasing (i.e. programming and resetting) the phase change memory cellnThe phase change memory cell can store n 2 bits of data 4, n is 2, and the number of binary data of two bits stored is specifically 4 (i.e., "11" or "10")"," 01 "and" 00 "), but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, the total number of kinds of the operation pulses for erasing (i.e., programming and resetting) the phase change memory cell may be set to 2nAt this time, the phase change memory cell can store multi-bit binary data with the number of bits n and the total number of bits 2nWherein n is a natural number greater than 1. At this time, the step of reading the multi-bit binary data stored in the phase change memory cell therein may include: and utilizing more levels of reading voltage threshold values to judge the multi-bit binary data stored in the phase change memory unit bit by bit, wherein the reading voltage threshold values of all levels are different in size.
In summary, in the technical solution of the present invention, the phase change material layer has different crystallization ratios under the action of different operation pulses, and the phase change memory cell has different resistance states under different crystallization ratios, and the different resistance states can represent different data characteristics, and corresponding operation pulses are applied to the phase change memory cell to cause the phase change material layer to change phase to the corresponding crystallization ratio, so that the phase change memory cell stores corresponding multi-bit data, that is, the phase change memory cell can be partially programmed or partially reset by using the corresponding operation pulses, and further the phase change memory cell can be upgraded from the existing unit of "0" or "1" to the storage of two-bit or more-bit data, and thus, on the phase change memory cell of the same stack or size, the structure of the phase change memory cell does not need to be changed, the bit density of the phase change memory unit can be increased by 2 times or more without additional process treatment, and the method has the advantages of simple scheme, easy implementation and low cost.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art according to the above disclosure are within the scope of the present invention.
Claims (15)
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004006730A (en) * | 2002-03-22 | 2004-01-08 | Semiconductor Energy Lab Co Ltd | Semiconductor memory element and semiconductor memory |
| KR20080061014A (en) * | 2006-12-27 | 2008-07-02 | 주식회사 하이닉스반도체 | Programming method of phase change memory device |
| US20100110779A1 (en) * | 2008-11-06 | 2010-05-06 | Micron Technology, Inc. | Multilevel phase change memory operation |
| US20150206582A1 (en) * | 2014-01-17 | 2015-07-23 | International Business Machines Corporation | Writing multiple levels in a phase change memory |
| CN110619906A (en) * | 2019-08-19 | 2019-12-27 | 中国科学院上海微系统与信息技术研究所 | Readout circuit and readout method of multilevel phase change memory |
| CN113205847A (en) * | 2020-01-31 | 2021-08-03 | 台湾积体电路制造股份有限公司 | Memory device and programming method thereof |
-
2021
- 2021-09-27 CN CN202111138338.XA patent/CN113851164A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2004006730A (en) * | 2002-03-22 | 2004-01-08 | Semiconductor Energy Lab Co Ltd | Semiconductor memory element and semiconductor memory |
| KR20080061014A (en) * | 2006-12-27 | 2008-07-02 | 주식회사 하이닉스반도체 | Programming method of phase change memory device |
| US20100110779A1 (en) * | 2008-11-06 | 2010-05-06 | Micron Technology, Inc. | Multilevel phase change memory operation |
| US20150206582A1 (en) * | 2014-01-17 | 2015-07-23 | International Business Machines Corporation | Writing multiple levels in a phase change memory |
| CN110619906A (en) * | 2019-08-19 | 2019-12-27 | 中国科学院上海微系统与信息技术研究所 | Readout circuit and readout method of multilevel phase change memory |
| CN113205847A (en) * | 2020-01-31 | 2021-08-03 | 台湾积体电路制造股份有限公司 | Memory device and programming method thereof |
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