CN113851457B - A non-ion implantation radiation-resistant power transistor and its preparation method - Google Patents
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Abstract
一种无离子注入抗辐照功率晶体管及其制备方法，属于晶体管技术领域。通过在晶体管有源区先形成致密的薄氧化硅层，再在薄氧化硅层上形成高致密性抗辐照阻挡层，再在抗辐照阻挡层上形成低致密性抗辐照吸收层，将辐照大幅度衰减，使底层氧化硅层受辐射的影响大幅度降低，使薄氧化硅层受辐照产生的电子空穴对快速被扫出氧化层，在氧化层界面不能形成带正电的氧化物陷阱电荷，大幅降低硅衬底中杂质浓度的再分布，大大提高载流子的寿命和电流增益，减少反向漏电流及饱和压降，使晶体管的抗辐照能力得到明显的提高。解决了必须采用高能离子注入工艺才能制造出抗辐照功率晶体管且成本高昂的问题。广泛应用于半导体晶体管及半导体集成电路抗辐照领域。
A non-ion-implanted radiation-resistant power transistor and a preparation method thereof belong to the field of transistor technology. By first forming a dense thin silicon oxide layer in the active area of the transistor, then forming a high-density radiation-resistant barrier layer on the thin silicon oxide layer, and then forming a low-density radiation-resistant absorption layer on the radiation-resistant barrier layer, the radiation is greatly attenuated, the influence of the radiation on the underlying silicon oxide layer is greatly reduced, the electron-hole pairs generated by the radiation of the thin silicon oxide layer are quickly swept out of the oxide layer, and the positively charged oxide trap charge cannot be formed at the oxide layer interface, the redistribution of the impurity concentration in the silicon substrate is greatly reduced, the carrier life and current gain are greatly improved, the reverse leakage current and the saturation voltage drop are reduced, and the radiation resistance of the transistor is significantly improved. The problem that a high-energy ion implantation process must be used to manufacture radiation-resistant power transistors and the cost is high is solved. It is widely used in the field of semiconductor transistors and semiconductor integrated circuits for radiation resistance.
Description
Technical Field
The invention relates to the field of semiconductor transistors, in particular to an ion implantation-free anti-irradiation power transistor structure and a preparation method thereof.
Background
Typical structures and production processes of the existing power transistors are shown in fig. 1 and 2, after irradiation tests, the current gain of the product produced by the design process is reduced, the reverse leakage current is increased, the saturation voltage drop is increased obviously, and the irradiation resistance of the product is poor. The reason is that for bipolar transistors, the instantaneous radiant energy creates electron hole pairs in the silicon dioxide passivation layer of the chip. Because of the high mobility of electrons in silicon dioxide, electrons in electron-hole pairs are swept out of the oxide layer in a matter of picoseconds, while holes that are not recombined are subjected to step motion in the oxide layer in a localized state toward the interface. When holes move to the vicinity of the interface, a part of holes are captured by traps at the interface to form positively charged oxide trap charges, so that the impurity concentration in the silicon substrate is redistributed, the service life of carriers is reduced, and the phenomena of reduced current gain, increased reverse leakage current, increased saturation voltage drop, obvious reduction of the anti-irradiation capability of the transistor and the like are caused. This trend is more pronounced as the oxide layer thickness increases. Therefore, in order to ensure that the irradiation resistance of the power transistor is improved and the matching between the processes of the subsequent products is better, the thermal oxidation thickness of the silicon wafer should be controlled to be the thickness of the oxidation layer when the power transistor is producedWithin the range. However, because the oxide layer generated by thermal oxidation of the silicon wafer is a dry, wet and dry process, the oxidation temperature is about 1150 ℃, and the thickness of the oxide layer is very thick by adopting the traditional process method of generating a base region and an emitter region by high-temperature diffusion, which generally reaches
In the actual process, the compactness of the oxide layer is lower than a theoretical value, so that the thickness of the oxide layer of the base region of the NPN transistor is usually equal to the value in order to ensure that the oxide layer does not pass through when phosphorus diffusesThe phenomenon of penetration of the emission area can not occur when the chip is diffused in the high-temperature emission area can be ensured, and the reason is that:
the thickness of the base oxide layer of the NPN transistor is calculated as follows:
The diffusion of impurity atoms in the silica also approximately follows the residual error distribution. The residual error distribution function is obtained by:
Diffusion junction depth of impurities in silicon dioxide
For an NPN transistor:
pre-diffusion of the emission region, wherein the pre-diffusion temperature of the emission region is 1080 ℃, the time is 60 min=3600s, and the diffusion coefficient in silicon dioxide at 1080 ℃ is set to be Can calculate the junction depth
The main diffusion of the emitting region is that the main diffusion temperature is 1050 ℃, the time is 10min+60min+10min+120min=200min=12000 s, and the diffusion coefficient in silicon dioxide at 1050 ℃ isCan calculate the junction depth
Total phosphorus diffusion junction depth
If the oxide layer is artificially controlled to beWithin the range, base region and emitter region punch-through phenomenon can occur, and qualified power transistor parameters can not be produced. Problems with 1)And 2) after depositing silicon nitride on the thin oxide layer, in the subsequent pre-diffusion of phosphorus, the passivation layer on the surface of the chip is completely cracked and the parameters are completely penetrated due to larger difference of expansion coefficients of the silicon nitride and the oxide layer. Therefore, the oxidation layer is controlled to be in the state of adopting the traditional process to produce the power transistor radiation-resistant capability productThe range is not feasible.
Considering that the base region oxide layer is in a dry, wet and dry process, the compactness of the oxide layer is lower than a theoretical value, so that the thickness of the base region oxide layer is usually taken as a value for an NPN transistor in order to ensure that no oxide layer penetration occurs during phosphorus diffusionTherefore, when the method for ensuring the radiation resistance of the power transistor is that the power transistor is produced, the thermal oxidation thickness of the silicon wafer is controlled to be the thickness of the oxidation layerThe base and emitter are formed by implanting the base and emitter regions by using ion implantation technology in the range. But ion implantation equipment is expensive to use and maintain. The base region of the device is generally implanted with a dose of 5e14 to 2e15 (base region square in) To ensure that the emitter region has sufficient emission efficiency, the emitter region needs to have a large doping concentration, and thus the implantation dose of the emitter region needs to reach more than about 3e16 (emitter region surface square: ). If a medium beam ion implanter is adopted, the beam current is smaller, and the long-time implantation can cause equipment failure due to overheat of a machine scanning mechanism, so that the single phosphorus implantation dose is limited to 5e14, and the scanning time is about 1.5min. If the dosage above 3E16 is injected, the single chip time length is longer than 90min, so that the process time is too long and the running risk of equipment is high. If a large beam ion implanter is used, the equipment cost, the material cost, the use cost and the maintenance cost can be greatly improved.
In view of this, the present invention has been made.
Disclosure of Invention
The invention aims to solve the problems that the irradiation-resistant power transistor can be manufactured only by adopting a medium beam ion injection process or a large beam ion injection process in the prior art, and the cost is high.
The invention adopts the technical conception that a middle beam ion injection process or a large beam ion injection process is canceled, the process structure of the traditional power transistor is improved (as shown in figures 1 and 2), a compact thin silicon oxide layer is firstly formed in an active region of the transistor, then a high-compactness anti-radiation blocking layer is formed on the thin silicon oxide layer, and then a low-compactness anti-radiation absorbing layer is formed on the anti-radiation blocking layer, namely, a high-compactness-low-compactness double-layer anti-radiation structure (as shown in figures 3 and 4) is adopted, radiation is greatly attenuated, the influence of radiation on a bottom silicon dioxide layer is greatly reduced, meanwhile, a thin silicon dioxide layer with the thickness as thin as possible is adopted, electron hole pairs generated by radiation are rapidly swept out of the oxide layer, oxide trap charges with positive electricity cannot be formed at an interface of the oxide layer, the impurity concentration in a silicon substrate is greatly reduced, the service life and the current gain of a carrier are greatly prolonged, the reverse leakage current and the saturation voltage drop are reduced, and the anti-radiation capability of the transistor is obviously improved.
To this end, the present invention provides an ion-implantation-free irradiation-resistant power transistor, as shown in fig. 3. Comprises an N + silicon substrate 1, a concentrated base region 2, a light base region 3, an emitter region 4, a concentrated boron ring 5, a thick silicon dioxide layer 6, a thin silicon dioxide layer 7, an emitter metal electrode 8, a base metal electrode 9, a radiation-resistant barrier layer 10, a radiation-resistant absorption layer 11 and a back metallization layer 12.
The method comprises the steps of epitaxially growing a thick base region 2 with a set thickness on the upper surface of an N + silicon substrate 1, diffusing a thin base region 3 with a set thickness in the middle region of the thick base region 2 at a high temperature, diffusing an emitter region 4 with a set thickness in the middle region of the thin base region 3, forming a thick boron ring 5 surrounding the thin base region 3 at the periphery of the thin base region 3, arranging a base lead hole in the middle region of the surface of the thick boron ring 5, arranging an emitter region lead hole in the middle region of the surface of the emitter region 4, arranging a thick silicon dioxide layer 6 on the peripheral region surface of the base lead hole, arranging a thin silicon dioxide layer 7 on the surface of the region between the base lead hole and the emitter region lead hole, arranging an emitter metal electrode 8 and a base metal electrode 9 on the emitter region lead hole and the base lead hole respectively, forming an emitter region outer lead bonding region and a base region outer lead bonding region respectively, arranging an anti-radiation blocking layer 10 on the thick silicon dioxide layer 6 and the thin silicon dioxide layer 7, arranging an anti-radiation absorbing layer 11 on the anti-radiation blocking layer 10, and arranging a back metallization layer 12 on the bottom surface of the N + silicon substrate 1.
The thick base region and the thin base region are doped with boron, the emitter region is doped with phosphorus, the thick boron ring spans the boundary line between the thick base region and the thin base region, and the depth of the thick boron ring is larger than the thickness of the thin base region.
The emitter metal electrode 8 is the emitter E of the power transistor, the base metal electrode 9 is the base B of the power transistor, and the back metallization layer 12 is the collector C of the power transistor. When the power transistor is placed in an irradiation environment, a part of irradiation is firstly absorbed by the low-compactness anti-irradiation absorption layer 11, irradiation which is not absorbed but penetrates through the anti-irradiation absorption layer 11 is then reflected and blocked by the compact anti-irradiation blocking layer 10, so that the influence of irradiation on the thin silicon dioxide layer 7 in the active region of the power transistor is greatly reduced, and the anti-irradiation function of the power transistor is realized.
Further, as shown in fig. 5, the upper surface of the anti-radiation absorbing layer 11 is provided with an anti-radiation reinforcing layer 13, which reflects and absorbs a large amount of radiation first, thereby further greatly improving the anti-radiation capability of the power transistor.
The preparation method of the ion implantation-free anti-irradiation power transistor is shown in fig. 4. The method comprises the following steps:
(1) Silicon wafer oxidation, growing thick silicon dioxide layer with thickness value of The above;
(2) Photoetching a thick base region;
(3) Diffusing concentrated boron;
(4) Photoetching a light base region;
(5) Light boron diffusion;
(6) Photoetching an emission area;
(7) Phosphorus diffusion in the emission region;
(8) Photoetching an active area;
(9) Growing a thin silicon dioxide layer, thickness value
(10) Growing a radiation-resistant barrier layer with a thickness value of
(11) Photoetching a lead hole;
(12) Growing a metal film;
(13) Photoetching a metal lead;
(14) An alloy;
(15) Growing an anti-radiation absorption layer with a thickness value of
(16) Photoetching a bonding area;
(17) Thinning the back surface;
(18) And (5) back surface metallization.
The invention has the beneficial effects that:
by analyzing the influence of various technological methods in the production of the power transistor on the irradiation performance and the product parameters of the transistor, the thickness value generated on the active area in the production process of the power transistor is adopted as After the oxide layer is etched by a photoetching method, forming a thickness value of the active regionThe thin oxide layer and the thickness of (a) are respectivelyA radiation-resistant barrier layer,The radiation-resistant absorption layer on the base region can inhibit the passivation layer on the base region from accumulating charges and the generated composite current on the surface of the base region, reduce the degradation degree of the current gain h FE caused by radiation, effectively control the generation of electron hole pairs in the oxide layer, reduce the capture of silicon dioxide to positive charges, reduce the oxide trap charges at the interface after instantaneous radiation, reduce the influence of radiation effect on the convection gain, reverse leakage current and saturation voltage drop, greatly reduce the influence of radiation on the performance of a power transistor (bipolar transistor), and greatly improve the radiation resistance of the power transistor.
The technical scheme of the invention can be widely applied to the field of radiation resistance of semiconductor transistors and semiconductor integrated circuits.
Drawings
Fig. 1 is a schematic diagram of an original transistor structure.
Fig. 2 is a schematic diagram of a conventional transistor manufacturing process.
Fig. 3 is a schematic diagram of a dual-layer anti-radiation transistor structure according to the present invention.
Fig. 4 is a schematic diagram of a transistor manufacturing process according to the present invention.
Fig. 5 is a schematic diagram of a three-layer anti-radiation transistor structure according to the present invention.
In the attached drawings, 1 is an N + silicon substrate, 2 is a concentrated base region, 3 is a light base region, 4 is an emitter region, 5 is a concentrated boron ring, 6 is thick silicon dioxide, 7 is thin silicon dioxide, 8 is an emitter metal electrode, 9 is a base metal electrode, 10 is an anti-radiation blocking layer, 11 is an anti-radiation absorbing layer, 12 is a back metallization layer, and 13 is an anti-radiation reinforcing layer.
Detailed Description
Referring to fig. 3-5, embodiments of the present invention are as follows:
1. Irradiation-resistant mode of thin silicon oxide layer and double-layer heterogeneous silicon nitride (high-density silicon nitride and low-density silicon nitride)
A compact thin silicon oxide layer is formed in an active region of the transistor, a high-compactness silicon nitride barrier layer is formed on the thin silicon oxide layer, and a low-compactness silicon nitride absorption layer is formed on the silicon nitride barrier layer, namely, a high-compactness-low-compactness double-layer silicon nitride structure is adopted, so that irradiation is reduced to the minimum extent, the influence of radiation on a bottom silicon oxide layer is minimized, meanwhile, a thin silicon oxide layer with the thickness as thin as possible is adopted, electron hole pairs generated by irradiation are rapidly swept out of the oxide layer, positive oxide trap charges cannot be formed at an interface of the oxide layer, redistribution of impurity concentration in a silicon substrate is greatly reduced, service life and current gain of carriers are greatly improved, reverse leakage current and saturation voltage drop are reduced, and irradiation resistance of the transistor is obviously improved.
Thickness value generated on active region in power transistor production process isEtching the oxide layer by photoetching, and then performing low-temperature oxidation (1000-1050 ℃ for 30 min) in the active region to obtain a dry oxide or deposited silicon dioxide growth thickness with a value ofIs of the thickness and the thin oxide layer of(650-750 ℃ And 30-40 min) and E-B junction surfaces of the light base region and the emitter region areThe thin oxide layer has no high temperature process after the silicon nitride is manufactured, and no thermal matching problem exists, and the process adopts LPCVD high temperature (650-750 ℃) and PECVD low temperature (400 ℃) double-layer heterogeneous silicon nitride structure. By adopting the thin oxide layer and double-layer heterogeneous silicon nitride structure, electron hole pairs generated in the oxide layer can be effectively controlled, and the capture of positive charges by silicon dioxide is reduced, so that the oxide trap charges at the interface after instantaneous radiation are reduced, the influence of radiation effect on convection gain, reverse leakage current and saturation voltage drop is reduced, and the irradiation resistance of the power transistor is improved.
The specific implementation key points are as follows:
1. Growth process of thick silicon oxide layer
Adopting an oxidation process of dry oxygen, wet oxygen and dry oxygen, performing thermal oxidation on a silicon wafer in a high-temperature furnace at about 1180 ℃ according to the time sequence of 10min+60min+10min, and obtaining the thickness of an oxidation layerIs a thick silicon oxide layer.
2. Thin silicon oxide layer growth process
Adopting a dry oxygen oxidation process, and performing thermal oxidation on the surface of the silicon wafer active region for 35min in a high-temperature furnace at 1000-1050 ℃ to obtain the thickness of the oxide layerIs a thin silicon oxide layer of (a).
3. High-compactness silicon nitride layer growth process
Introducing mixed process gas of SiH 2Cl2+NH3 in low pressure state in low pressure LPCVD furnace at 650-750deg.C for 30-40 min to obtain the final productIs a high-density silicon nitride (Si 3N4) radiation-resistant barrier layer.
4. Growth process of low-compactness silicon nitride layer
Introducing SiH 4+NH3 mixed process gas for 3-4 min in a PECVD furnace at 350-400 deg.C under vacuum state by low temperature plasma chemical vapor deposition (PECVD) process to obtain a film with a thickness ofIs a low-density silicon nitride (Si 3N4) radiation-resistant absorber layer.
5. The metal electrode is an aluminum metal film electrode.
6. The back metallization electrode is a gold electrode or a multi-layer composite metal film electrode.
2. The irradiation-resistant mode of the thin silicon oxide layer + double-layer heterogeneous silicon nitride (high-density silicon nitride + low-density silicon nitride) +polyimide is shown in fig. 5.
The surface of the low-density silicon nitride layer is subjected to spin coating, curing and etching processes to form the thicknessIs a polyimide radiation resistant reinforcing layer.
The polyimide is high-purity polyimide or mixed polyimide added with radiation absorbing substances.
Finally, it should be noted that the above-mentioned examples are only examples for the sake of clarity and that the present invention includes, but is not limited to, the above examples, which need not be, nor should they be exhaustive of all embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. All embodiments meeting the requirements of the invention are within the protection scope of the invention.
Claims (10)
1. The non-ion implantation anti-radiation power transistor is characterized by comprising an N + silicon substrate, a concentrated base region, a light base region, an emitter region, a concentrated boron ring, a thick silicon dioxide layer, a thin silicon dioxide layer, an emitter metal electrode, a base metal electrode, an anti-radiation blocking layer, an anti-radiation absorbing layer and a back metallization layer;
The upper surface of the N+ silicon substrate is a thick base region with set thickness through epitaxial growth, the middle region of the thick base region is a thin base region with set thickness through high-temperature diffusion, the middle region of the thin base region is an emitter region with set thickness through high-temperature diffusion, a thick boron ring surrounding the thin base region is arranged on the periphery of the thin base region, a base lead hole is arranged in the middle region of the surface of the thick boron ring, an emitter region lead hole is arranged in the middle region of the surface of the emitter region, a thick silicon dioxide layer is arranged on the surface of the peripheral region of the base lead hole, a thin silicon dioxide layer is arranged on the surface of the region between the base lead hole and the emitter region lead hole, an emitter metal electrode and a base metal electrode are respectively arranged on the emitter region lead hole and the base lead hole, an emitter region outer lead bonding region and a base region outer lead bonding region are respectively formed, an anti-radiation blocking layer is arranged on the thick silicon dioxide layer and the thin silicon dioxide layer, an anti-radiation absorbing layer is arranged on the anti-radiation blocking layer, and the bottom surface of the N + silicon substrate is provided with a back metallization layer;
The thickness value of the thick silicon dioxide layer is 7000A or more;
The thickness value of the thin silicon dioxide layer is 1000A-2000A;
the thickness value of the anti-radiation barrier layer is 2000A-2500A;
the thickness value of the radiation-resistant absorption layer is 4000A-5000A.
2. The ion implantation-free radiation-resistant power transistor of claim 1, wherein said thick base region and said thin base region are doped with boron, said emitter region is doped with phosphorus, and said thick boron ring spans the boundary between said thick base region and said thin base region and has a depth greater than the thickness of said thin base region.
3. The ion implantation-free radiation-resistant power transistor of claim 1, wherein said emitter metal electrode and said base metal electrode are aluminum metal film electrodes, and said back side metallization layer is a gold electrode or a multi-layer composite metal film electrode.
4. The ion implantation-free radiation-resistant power transistor of claim 1, wherein said thin silicon dioxide layer is a high-density silicon dioxide layer having a thickness of 1000 a-2000 a, said radiation-resistant barrier layer is a high-density silicon nitride having a thickness of 2000 a-2500 a, and said radiation-resistant absorber layer is a low-density silicon nitride having a thickness of 4000 a-5000 a.
5. The ion implantation-free radiation-resistant power transistor as defined in claim 1, further comprising a radiation-resistant reinforcing layer, wherein the radiation-resistant reinforcing layer is positioned on the upper surface of the radiation-resistant absorbing layer, the thickness of the radiation-resistant reinforcing layer is 8000 a-12000 a, and the radiation-resistant reinforcing layer is high-purity polyimide or mixed polyimide added with radiation absorbing substances.
6. The method for manufacturing an ion implantation-free irradiation-resistant power transistor according to claim 1, comprising the steps of:
(1) Oxidizing the silicon wafer, and growing a thick silicon dioxide layer, wherein the thickness value is more than 7000A;
(2) Photoetching a thick base region;
(3) Diffusing concentrated boron;
(4) Photoetching a light base region;
(5) Light boron diffusion;
(6) Photoetching an emission area;
(7) Phosphorus diffusion in the emission region;
(8) Photoetching an active area;
(9) Growing a thin silicon dioxide layer with a thickness of 1000 a-2000 a;
(10) Growing a radiation-resistant barrier layer with a thickness value of 2000A-2500A;
(11) Photoetching a lead hole;
(12) Growing a metal film;
(13) Photoetching a metal lead;
(14) An alloy;
(15) Growing an anti-radiation absorption layer, wherein the thickness value of the anti-radiation absorption layer is 4000A-5000A;
(16) Photoetching a bonding area;
(17) Thinning the back surface;
(18) And (5) back surface metallization.
7. The method for manufacturing an ion implantation-free irradiation-resistant power transistor according to claim 6, wherein the growing process of the thick silicon dioxide layer is as follows:
And (3) performing thermal oxidation on the silicon wafer in a high-temperature furnace at about 1180 ℃ according to the time sequence of 10min+60min+10min by adopting an oxidation process of dry oxygen, wet oxygen and dry oxygen, so as to obtain a thick silicon oxide layer with an oxide layer thickness of 7000A-10000A.
8. The method for manufacturing an ion implantation-free irradiation-resistant power transistor according to claim 6, wherein the growth process of the thin silicon dioxide layer is as follows:
And (3) performing thermal oxidation on the surface of the silicon wafer active region for 35min in a high-temperature furnace at the temperature of 1000-1050 ℃ by adopting a dry-oxygen oxidation process to obtain the thin silicon oxide layer with the oxide layer thickness of 1000-2000A.
9. The method for preparing the non-ion implantation irradiation-resistant power transistor according to claim 6, wherein the irradiation-resistant barrier layer is high-density silicon nitride, and the growth process of the high-density silicon nitride layer is as follows:
And (3) adopting a high-temperature low-pressure chemical vapor deposition LPCVD process, and introducing SiH 2Cl2+NH3 mixed process gas for 30-40 min in an LPCVD furnace at 650-750 ℃ under a low-pressure state to obtain the high-density silicon nitride anti-radiation barrier layer with the thickness of 2000-2500A.
10. The method for preparing the non-ion implantation irradiation-resistant power transistor according to claim 6, wherein the irradiation-resistant absorption layer is low-density silicon nitride, and the growth process of the low-density silicon nitride layer is as follows:
And (3) adopting a low-temperature plasma chemical vapor deposition PECVD process, and introducing SiH 4+NH3 mixed process gas for 3-4 min in a PECVD furnace at 350-400 ℃ under a vacuum state to obtain the low-density silicon nitride anti-radiation absorption layer with the thickness of 4000A-5000A.
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| CN103280409A (en) * | 2013-05-15 | 2013-09-04 | 电子科技大学 | Method for producing junction field effect transistor |
| CN106653601A (en) * | 2016-11-14 | 2017-05-10 | 北京时代民芯科技有限公司 | A bipolar device manufacturing method resistant to low dose rate radiation |
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| CN113851457A (en) | 2021-12-28 |
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