CN113868172B

CN113868172B - Interconnect interface

Info

Publication number: CN113868172B
Application number: CN202111142604.6A
Authority: CN
Inventors: 王惟林; 杨帆; 张帅; 郑春晖; 沈鹏
Original assignee: Shanghai Zhaoxin Semiconductor Co Ltd
Current assignee: Shanghai Zhaoxin Semiconductor Co Ltd
Priority date: 2021-09-28
Filing date: 2021-09-28
Publication date: 2024-06-18
Anticipated expiration: 2041-09-28
Also published as: CN113868172A

Abstract

An interconnect interface for use between packages, or between chips. An interconnect interface includes a first transmitter, a first receiver, and an electro-physical layer coupled between the first transmitter and the first receiver. Data provided by a first device is transmitted from the first transmitter to the electro-physical layer for transmission to the first receiver for retrieval from the first receiver by a second device. The first transmitter includes an arbiter that arbitrates multiple channels of the first device to obtain data from the first device. The first transmitter includes a packet generator that packetizes data obtained from the first device for transmission by the electro-physical layer. The first transmitter further includes a first buffer for buffering data obtained from the first device for retransmission.

Description

Interconnect interface

Technical Field

The present invention relates to an interconnection interface, and more particularly, to an interconnection interface (socket-to-socket interconnect interface) between packages, and an interconnection interface (die-to-die interconnect interface) between chips in each package.

Background

Conventional point-to-point transmission is implemented with a high-speed serial bus (PCIE).

However, the high-speed serial bus (PCIE) may complicate the pipeline design, even lead to a prolonged transmission delay, and may also have problems such as hardware consumption and limited effective bandwidth ….

There is a need in the art for an interconnect interface that has low latency, high reliability, and high bandwidth utilization.

Disclosure of Invention

The invention discloses high-performance interconnection interfaces, including an interconnection interface between packages (socket-to-socket interconnect interface) and an interconnection interface between chips in each package (die-to-die interconnect interface).

An interconnect interface (ZPI/ZDI) implemented in accordance with one embodiment of the present invention includes a first transmitter (TX 0), a first receiver (RX 0), and an electro-physical layer (EPHY) coupled between the first transmitter and the first receiver. Data provided by a first device (socket 0/Die 0) is transmitted from the first transmitter to the electro-physical layer for transmission to the first receiver. The first transmitter includes an arbiter (TXARB) that arbitrates the plurality of channels (CH 1-CHN) of the first device to obtain data from the first device. The first transmitter includes a packet generator (PACKETGEN) that generates packets (flits) from data obtained from the first device for transmission by the electro-physical layer. The first transmitter further includes a first buffer (RetryBuf) for buffering data obtained from the first device for retransmission.

In one embodiment, the first transmitter further comprises a dummy packet generator (FlitGen) that generates dummy packets and fills the electro-physical layer transmission when no packets are generated by the packet generator. The first transmitter further includes a parallel-to-serial converter (PtoS) for parallel-to-serial converting packets for transmission by the electro-physical layer. The first receiver includes a serial-to-parallel converter (StoP) that performs serial-to-parallel conversion on packets transmitted from the electro-physical layer. The first receiver also includes a decoder (FlitDec) that decodes the data from the received packet. The first receiver further includes a check logic module for discarding the received data and causing the second device to request retransmission from the first device when the check fails. The first receiver also includes an analysis module (RXanls) that analyzes the verified data for distribution to the plurality of channels (CH 1-CHN) of the second device.

In one embodiment, the interconnect interface further includes a second transmitter (TX 1) and a second receiver (RX 1) coupled across the electro-physical layer. The second transmitter is coupled to the second device, and the second receiver is coupled to the first device, such that the interconnect interface is a full duplex structure.

In one embodiment, the first transmitter further comprises a retransmission controller (RetryCon). When the check logic module of the first receiver fails to check data, the second device transmits the retransmission request to the first device through the second transmitter, the electric physical layer and the second receiver, and the first device drives the retransmission controller to take out the content of the first buffer for retransmission.

In one embodiment, the first transmitter further includes a state machine (LTSSM) that, when switching to a reduced speed state, stops operation of the arbiter and reduces the transmission rate of the electro-physical layer. The first transmitter further includes a second buffer for buffering packets not yet transmitted by the electro-physical layer when the state machine is in the reduced-speed state. In one embodiment, the first receiver further includes a third buffer for buffering data received from the electro-physical layer for verification and analysis. When the third buffer is fully loaded, the second device transmits a speed reduction request to the first device through the second transmitter, the electric physical layer and the second receiver, and the first device enables the state machine to be switched into the speed reduction state. In one embodiment, the state machine is switched to the reduced speed state by the first device in response to a low power consumption setting.

In one embodiment, a packet previously transmitted by the first device and the second device over the interconnect interface includes a unit code (FlitCode), packet information, a Cyclic Redundancy Check (CRC), and a channel code (FEC). Data from the first device or the second device is carried as the packet information. The unit code indicates an attribute of the packet information. The cyclic redundancy check code and the channel code are used by a receiver to check the packet information.

In one embodiment, the first transmitter and the first receiver are pipelined hardware.

In one embodiment, the first device and the second device linked by the interconnection interface are a first package (socket 0) and a second package (socket 1), respectively. The packets transmitted by the first and second packages over the interconnect interface are of indefinite length, 2 ^N bits in size, N being a variable. The first transmitter further includes a data compressor (DataComp) coupled between the arbiter and the packet generator in response to a request for inter-enclosure interconnect variable length packet transmission. The first receiver also includes a data reordering module (DataRea) that reorders data that passes the verification to the analyzer in response to a request for transmission of packets of varying length to the inter-enclosure interconnect.

In one embodiment, the first device and the second device linked by the interconnect interface are a first chip (Die 0) and a second chip (Die 1), respectively. The packets transmitted by the first chip and the second chip through the interconnect interface are of a fixed length.

In one embodiment, the first device is in handshake communication with the first transmitter, such that the first transmitter obtains data from the first device, sends the data to the electro-physical layer for transmission to the first receiver. The first receiver communicates with the second device in a handshake that hands over data received from the electro-physical layer to the first receiver.

The present invention will be described in detail with reference to the accompanying drawings.

Drawings

FIG. 1 is an embodiment of ZPI interconnect interfaces, where two package sockets 0 and 1 are linked by ZPI interconnect interface (numbered ZPI in the figure);

FIGS. 2A-2C illustrate other planar interconnect embodiments implemented with interconnect interfaces ZPI between packages;

FIGS. 3A, 3B illustrate a three-dimensional (3D) interconnect embodiment implemented with an interconnect interface ZPI between packages;

FIG. 4 is an embodiment of a ZDI interconnect interface;

FIGS. 5A-5C illustrate planar interconnect embodiments in which packages are linked by interconnect interface ZPI, while chips within the packages are linked by interconnect interface ZDI;

FIGS. 6A, 6B illustrate a three-dimensional interconnect embodiment in which packages are linked by interconnect interface ZPI, and chips within the packages are linked by interconnect interface ZDI;

FIG. 7 illustrates a package 700 that includes a chipset 702 as well as other chips (e.g., compute nodes, coprocessors, and accelerators);

FIG. 8 illustrates a communication architecture of the interconnect interface ZPI/ZDI of the present invention;

FIGS. 9A, 9B illustrate in waveform diagrams the input/output protocol (I/O protocol) between the device and the interconnect interface ZPI/ZDI;

Fig. 10 illustrates a packet format 1000 transmitted by interconnect interface ZPI/ZDI in accordance with one embodiment of the present invention;

FIGS. 11A and 11B illustrate information paths and hardware structures of an encapsulation socket0 and an interconnection interface ZPI between encapsulation sockets 1 according to one embodiment of the present invention; and

Fig. 12A, 12B illustrate the information path, and hardware structure, of the interconnect interface ZDI between chip Die0 and chip Die1 according to one embodiment of the present invention.

Detailed Description

The following description exemplifies various embodiments of the invention. The following description presents basic concepts of the invention and is not intended to limit the scope of the present invention. The actual scope of the invention is to be defined in the following claims.

The invention discloses high-performance interconnection interfaces, including a socket-to-socket interconnect interface interconnection interface between packages, and a die-to-die interconnect interface interconnection interface between chips in each package.

First, an interconnection interface (socket-to-socket interconnect interface) between packages is introduced, which is hereinafter named ZPI interconnection interface or interconnection interface ZPI.

Fig. 1 is an embodiment of ZPI interconnect interfaces, where two package sockets 0 and 1 are connected by ZPI interconnect interface (numbered ZPI in the figure). Two clusters (clusters) are shown in each package, labeled cluster0 and cluster1: other embodiments may have other numbers of clusters. Each cluster includes several Central Processing Unit (CPU) cores. Within each package may be a last level cache (LAST LEVEL CACHE, labeled LLC), an interconnect bus 102, and various components, such as an input/output controller 104, a clock module 106, a power consumption module 108 …, and the like. Each package may also link a dual-wire memory module (labeled DIMM).

Through the interconnection interface ZPI, the package socket0 and the socket1 form a system, where the central processing unit cores and the input/output resources of all clusters can be uniformly scheduled, and the memories owned by the package socket0 and the socket1 can be uniformly used.

For example, through interconnect interface ZPI, packets (flits) of different packed caches have a consistent format. Thus, any CPU core or I/O device of the system formed by the packages may access any memory resource within the system.

Fig. 2A-2C illustrate other interconnect embodiments implemented with interconnect interface ZPI between packages. Fig. 2A, 2B enable the package to form a ring-like link with interconnect interface ZPI. Fig. 2A is a three-package ring link. Fig. 2B is a four package ring link. The four-package of fig. 2C has more interconnect interfaces ZPI as compared to fig. 2B to ensure the shortest communication path between packages. The number of packages can be extended to larger values.

Fig. 3A, 3B illustrate a three-dimensional (3D) interconnect embodiment implemented with an interconnect interface ZPI between packages. FIG. 3A implements a three-layer interconnect; the packaging sockets 0 to 3 are a plane (belonging to the same layer), and the front layer and the back layer are respectively packaging sockets 4 and 5. The front layer packaging socket4 is linked with the interconnection interface ZPI on the middle layer plane, and the interconnection interface ZPI is linked with the rear layer packaging socket5 to form a ring-shaped link. Fig. 3B implements a two-layer interconnect. The packaging sockets 0 to 3 of the first layer plane and the packaging sockets 4 to 7 of the second layer plane are linked one by an interconnection interface ZPI. The three-dimensional interconnect may have more layers. The number of packages per plane can be extended to larger values.

In addition, the interconnect interface (die-to-die interconnect interface) between chips is described as follows; hereafter it will be named ZDI interconnect interface or interconnect interface ZDI.

Fig. 4 is an embodiment of a ZDI interconnect interface. Two chips Die0 and Die1 within a package 400 are shown connected by a ZDI interconnect interface (labeled ZDI). Other embodiments may have a greater number of chips packaged together. Each chip may include a plurality of clusters (clusters). Each chip may have a last level cache LLC, an interconnect bus 402, and various components (e.g., input/output controller 404, clock module 406, power consumption module 408 …, etc.), without limitation.

The above interconnect interfaces ZPI, ZDI may be used in combination so that chips in different packages may communicate with each other.

Fig. 5A-5C illustrate planar interconnect embodiments in which packages are linked by interconnect interface ZPI, while chips within the packages are linked by interconnect interface ZDI. Fig. 5A illustrates three packages with interconnect interfaces ZPI linked in a ring, each of the chips in the packages being linked by interconnect interfaces ZDI; thus, six chips form a system, and resources can be shared. Fig. 5B illustrates four packages with interconnect interfaces ZPI linked in a ring, each of the chips in the packages being linked by interconnect interfaces ZDI; thus, eight chips form a system, and resources can be shared. Compared to fig. 5B, fig. 5C has more interconnect interfaces ZPI to minimize the communication paths for the differently packaged chips. The number of chips per package may be variable.

Fig. 6A, 6B illustrate a three-dimensional interconnect embodiment in which packages are linked by interconnect interface ZPI, while chips inside the packages are linked by interconnect interface ZDI. FIG. 6A illustrates a three-layer interconnect, each layer may be a single package or multiple package planes, each package may include multiple chips (e.g., D0, D1); the three-layer plane implements ring links with interconnect interfaces ZPI, collocated with interconnect interface ZDI. Each chip is a node of the system and can control the resources of other nodes. FIG. 6B illustrates a dual-layer interconnect, on a dual-layer plane, each package including a plurality of chips; the chips on the double-layer architecture are each a node of the system and can control the resources of other nodes. The above three-dimensional interconnect can be extended to more layers and there can be any number of chips within each package. On chipset (chipset) applications, the interconnect interface ZPI of the present invention, as well as the ZDI, may be used as follows.

Fig. 7 illustrates a package 700 that includes a chipset 702 (a chip) and other chips (e.g., compute nodes, coprocessors, and accelerators). The chipset 702 is linked to other chips, such as compute nodes, coprocessors, accelerators, etc., through an interconnect interface ZDI. To make up a larger system, multiple chipset packages may be linked by interconnect interfaces ZPI to form the planar interconnect architecture of fig. 2A-2C, or the stereoscopic interconnect architecture of fig. 3A, 3B. In one embodiment, multiple chipsets may be included within a single package; to make up a larger system, such multiple packages may be linked by interconnect interfaces ZPI to form the planar interconnect architecture of fig. 5A-5C, or the stereoscopic interconnect architecture of fig. 6A, 6B.

Fig. 8 illustrates the communication architecture of the interconnect interface ZPI/ZDI of the present invention. The interconnect interface 800 provides a bi-directional transmission channel between Device0 and Device1, which is a full duplex design, allowing simultaneous bi-directional transmission. In one embodiment, device0 and Device are two packages and interconnect interface 800 is a ZPI interconnect interface. In another embodiment, device0 and Device are two chips and interconnect interface 800 is a ZDI interconnect interface.

The transmitter TX0 of the Device0 via the interconnect interface 800 transmits the packet signal 802 and the clock signal 804 for reception by the receiver RX0 of the Device1 coupled to the interconnect interface 800. Conversely, device1 may send out packet signal 806 and clock signal 808 via transmitter TX1 of interconnect interface 800, which is received by receiver RX1 of interconnect interface 800 at Device 0.

Fig. 9A, 9B illustrate in waveform diagrams the input/output protocol (I/O protocol) between the device and the interconnect interface ZPI/ZDI.

The data signal tx_entry of the source device is transmitted to the transmitter TX of the interconnect interface, and is transmitted to the receiver RX at the other end of the transmission line via the transmission line (the electrical physical layer EPHY) of the interconnect interface, and is received as the data signal rx_entry, and is then transmitted to the destination device.

Fig. 9A shows a handshake communication between a source device and a transmitter TX of interconnect interface ZPI/ZDI, causing the transmitter TX to retrieve transmissions from the source device (TX transmission sequence).

The signal READY/ACTIVE is pulled up, showing that interconnect interface ZPI/ZDI is indeed established. Clock (CLK) T0, source device pulls up signal tx_req and transmitter TX pulls up signal tx_ack in response, handshaking informing the transfer of data signal tx_entry from source device to transmitter TX. The signals tx_req and tx_ack are set down at clock T1, leaving data from the source device. Clocks T2-T3, source device pull-up signal tx_req, but transmitter TX has not yet pulled up signal tx_ack; representing that the source device is ready for the data signal, the transmitter TX has not yet fetched data from the source device. The clock T4, signals tx_req and tx_ack are both pulled up, and the data signal tx_entry of the source device is given to the transmitter TX. The transmitter TX successfully retrieves the data signal from the source device. The signals tx_req and tx_ack are signaled by clock T5 and the handshake signals the end of data transfer from the source device to interconnect interface ZPI/ZDI with clock T1. The transmitter TX prepares to fetch data from the source device (pull-up signal tx_ack) but the source device has no data (pull-down signal tx_req) at clocks T6-T7.

Fig. 9B shows handshake communication between the receiver RX of the interconnect interface ZPI/ZDI and the target device to enable transmission (RX transmission sequence) received by the receiver RX to be handed over to the target device.

The signal READY/ACTIVE is pulled up, showing that interconnect interface ZPI/ZDI is indeed established. At clock T0, the receiver RX of interconnect interface ZPI/ZDI pulls up signal rx_req and the target device pulls up signal rx_ack in response, handshaking informs of the transfer of data signal rx_entry from receiver RX to target device. The signals rx_req and rx_ack are put down at clock T1, at which time no data is yet taken out of the receiver RX. A clock T2 in which the receiver RX pulls up the signal rx_req but the target device has not pulled up the signal rx_ack; representing that the receiver RX is ready for data signals, but the target device is not yet ready to receive data from the receiver RX. Clock T3, signals rx_req and rx_ack are both pulled up, and receiver RX passes data signal rx_entry taken from interconnect interface ZPI/ZDI transmission line to the target device; the target device successfully retrieves the data signal from the receiver RX. The signals RX_REQ and RX_ACK are handshaking with clock T1 to inform interconnect interface ZPI/ZDI that data transfer to the target device is complete. The clocks T5 to T6 are the target devices to prepare for the data fetch from the receiver RX (pull-up signal rx_ack), but the receiver RX has no data (pull-down signal rx_req). The signal rx_req and the rx_ack are pulled up at clock T7 to handshake again to inform the transfer of the data signal rx_entry from the receiver RX to the target device. However, the target device may have a mechanism to reject the received data (e.g., the target device may reject the data from interconnect interface ZPI/ZDI in view of its own buffer status, or otherwise). The target device pull-up signal RX_BNT requests to block the transmitted data, and the receiver RX responds to the pull-up signal RX_ACK, indicating an acknowledge block request, at clocks T8, T9.

Fig. 10 illustrates a format 1000 of packets transmitted by the interconnect interface ZPI/ZDI, including a unit code FlitCode, packet information, cyclic Redundancy Check (CRC), and channel coding (or forward error correction) FEC, according to one embodiment of the invention. In interconnect interface ZPI applications, format 1000 is 2 ^N bits long and is of indefinite length. In an interconnect interface ZDI application, the length of format 1000 is a fixed length.

The unit code FlitCode may include 5 bits as follows:

* X_1: (TLP enable) representing that the packet information is taken from the information signal tx_entry;

* X_0: (TLP disable) representing the dummy content of the packet information not taken from the information signal TX_Entry, but generated by interconnect interface ZPI/ZDI;

000 x: (ACK/NAK DLLP) for making a retransmission (retry) request;

01 x_: (FCI/FCU DLLP) for feeding back the buffer status of the receiver RX;

1000_: (PM RELATED DLLP) for power management;

1100_; (DLLP disable) indicating that the packet information has no valid content;

1111_: (Reserved for PHY) for padding as start, end, or idle flags for transmission.

Fig. 11A, 11B illustrate information paths of the encapsulation socket0 and the interconnection interface ZPI between the encapsulation sockets 1, and hardware structures according to one embodiment of the present invention. As shown, the transmitter TX of the interconnect interface ZPI is linked to the encapsulation socket0, so that the data signal of the encapsulation socket0 is transmitted to the electro-physical layer EPHY of the interconnect interface ZPI through the transmitter TX, and then received by the receiver RX of the interconnect interface ZPI, and transferred to the encapsulation socket1 linked to the other end of the interconnect port ZPI. The reverse path of full duplex (encapsulation socket1 to socket 0) is also so designed. The clock of interconnect interface ZPI is generated by a phase locked loop PLL and clock generator CLKgen.

Fig. 11A details the transmitter TX in particular. The data of the various types of the packaging socket0 are arbitrated by an arbiter TXARB in the transmitter TX through different channels CH1 to CHN. The data that wins arbitration is compressed by a data compressor DataComp and passed to a packet generator PACKETGEN to generate packets (flits, e.g., format 1000). The data transmitted by the channels CH1 to CHN may include a plurality of packets each cycle when generating the packets, and the plurality of packets may have the same format and different contents, or may be one packet each cycle, and may be determined by the data amount and the data format. When the encapsulation socket0 has no data transmission requirement, the interconnection interface ZPI can then generate the dummy packet by the dummy packet generator FlitGen, and fill the dummy content therein. Then, the packet is transmitted to the receiver RX at the other end of the interconnect interface ZPI via the electrical physical layer EPHY via the parallel-to-serial converter PtoS, and then forwarded to one of the corresponding channels CH 1-CHN in the encapsulation socket1 according to the data type.

The hardware of interconnect interface ZPI may be designed using pipeline (pipelined). For the transmitter TX, the packet generator PACKETGEN wraps the first data packet, the data compressor DataComp compresses the second data packet, and the arbiter TXARB arbitrates the third data packet. Interconnect interface ZPI operates efficiently.

The transmitter TX may buffer the transmission data with a buffer RetryBuf. If the receiver RX finds that the data sent from the electro-physical layer EPHY is wrong, the retransmission mechanism is started. The retransmission controller RetryCon fetches the data from the buffer RetryBuf, and the data is re-packed into a packet by the packet generator PACKETGEN, and retransmitted. One embodiment is to send a retransmission request from the RX end of the encapsulation socket1 to retryon of the TX end of the encapsulation socket1 (the TX end of socket1 is not shown in fig. 11A), driving the retransmission controller RetryCon of the encapsulation socket 1. Referring to fig. 8, TX0 and RX1 in fig. 8 belong to socket1, and TX1 and RX0 belong to socket0. After the check data of the receiver RX1 fails, the package socket1 may propose a retransmission request, and the retransmission request is transmitted from the transmitter TX0 of the socket1, the receiver RX0 passing through the electrical physical layer EPHY and the socket0 to the package socket0, and the package socket0 drives the retransmission controller RetryCon to take out the content of the buffer RetryBuf for retransmission.

A state machine LTSSM is also shown for interconnect interface ZPI to control the transmission rate of interconnect interface ZPI. In one embodiment, the state machine LTSSM may switch to a reduced speed state, suspending the arbiter TXARB and the data compressor DataComp so that no more data is provided to the packet generator PACKETGEN wrapper. In addition, the state machine LTSSM may also control the transmission rate of the electro-physical layer EPHY to achieve a speed down of the interconnect interface ZPI. The state machine LTSSM may be switched to the reduced speed state by the encapsulation socket0 in response to a low power consumption request, reducing the transmission rate of the interconnect interface ZPI. In another embodiment, the receiver RX may be blocked (e.g., the buffer in the receiver RX is full), and the encapsulation socket1 may send a down request to the encapsulation socket0 (via the interconnect interface ZPI not shown to the transmission hardware in the other direction in the figure), so that the encapsulation socket0 requests the state machine LTSSM to switch the transmission rate of the interconnect interface ZPI. Referring to fig. 8, when the buffer in the receiver RX is full, the encapsulation socket1 may request a speed reduction, and the state machine LTSSM is switched to the speed reduction state by the encapsulation socket0 from the transmitter TX1, the electro-physical layer EPHY and the receiver RX 1. In one embodiment, the parallel to serial converter PtoS includes a buffer to handle the speed reduction. For example, when the state machine LTSSM decreases the transmission rate of the electro-physical layer EPHY, the buffer is used to buffer data that cannot be transmitted to the other end.

Fig. 11B details the receiver RX in particular. Packets received from the electro-physical layer EPHY are converted by the serial-to-parallel converter StoP, unpacked by the decoder FlitDec, and checked by the check logic. The check logic may be based on a cyclic redundancy check, CRC, code, and channel coding, FEC. If the check fails, the receiver RX skips the received data and triggers the retransmission mechanism described above. If the verification is passed, the received data is rearranged (DATA REARRANGEMENT) by the data rearrangement module DataRea, and then distributed to the corresponding channel CH1 … CHN in the packaging socket1 by the analysis module RXanls, so that the transmission from the packaging socket0 to the interconnection interface ZPI of the packaging socket1 is completed. The hardware of the receiver RX may also be designed with a pipeline (pipelined). When the analysis module RXanls analyzes the first data, the data rearrangement module DataRea rearranges the second data to perform verification, and the decoder FlitDec obtains the third data after unpacking. Interconnect interface ZPI operates efficiently.

Fig. 12A, 12B illustrate the information paths of the interconnect interface ZDI between the chip Die0 and the chip Die1, and the hardware structure according to one embodiment of the present invention. In particular, unlike interconnect interface ZPI, which is of indefinite format 1000 length (2 ^N bits), interconnect interface ZDI has a format 1000 length that is a fixed length. In contrast to the transmitter TX details of interconnect interface ZPI of fig. 11A, interconnect interface ZDI transmitter TX of fig. 12A is not provided with data compressor DataComp. In contrast to the receiver RX details of interconnect interface ZPI of fig. 11B, interconnect interface ZDI receiver RX of fig. 12B is not provided with data reordering module DataRea. The check retransmission and the state machine speed-down mechanism can be the same as those shown in fig. 11A and 11B.

In summary, an interconnect interface (ZPI/ZDI) implemented in accordance with one embodiment of the present invention includes a first transmitter (TX 0), a first receiver (RX 0), and an electro-physical layer (EPHY) coupled between the first transmitter and the first receiver. Data provided by a first device (socket 0/Die 0) is transmitted from the first transmitter to the electro-physical layer for transmission to the first receiver for retrieval from the first receiver by a second device (socket 1/Die 1). The first transmitter includes an arbiter (TXARB) that arbitrates the plurality of channels (CH 1-CHN) of the first device to obtain data from the first device. The first transmitter includes a packet generator (PACKETGEN) that generates packets (flits) from data obtained from the first device for transmission by the electro-physical layer. The first transmitter further includes a first buffer (RetryBuf) for buffering data obtained from the first device for retransmission.

The interconnection interface of the invention has retransmission, speed reduction, and other designs, and has exclusive transmission packet, and the hardware is a pipeline architecture. The communication between the interconnection interface and the device is handshake communication.

While the invention has been described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An interconnect interface, comprising:

A first transmitter and a first receiver; and

An electro-physical layer coupled between the first transmitter and the first receiver,

Wherein:

the first transmitter is further coupled to a first device, and the first receiver is further coupled to a second device;

the data provided by the first device is sent to the electric physical layer by the first transmitter and transmitted to the first receiver;

The first transmitter includes an arbiter for arbitrating a plurality of channels of the first device to obtain data from the first device;

the first transmitter includes a packet generator for grouping the data acquired from the first device and transmitting the grouped data to the electro-physical layer; and

The first transmitter further includes a first buffer for buffering data obtained from the first device for retransmission.

2. The interconnect interface of claim 1, wherein:

The first transmitter further includes a dummy packet generator for generating dummy packets, and padding the dummy packets for transmission to the electro-physical layer when the packet generator does not generate the packets.

3. The interconnect interface of claim 2, wherein:

the first transmitter further comprises a parallel-to-serial converter for performing parallel-to-serial conversion on the packet and transmitting the packet to the electric physical layer; and

The first receiver includes a serial-to-parallel converter that performs serial-to-parallel conversion on packets transmitted from the electro-physical layer.

4. The interconnect interface of claim 3, wherein:

The first receiver also includes a decoder that decodes the data from the received packet, the data including the data provided by the first device.

5. The interconnect interface of claim 4, wherein:

the first receiver further includes a check logic module for discarding the received data and causing the second device to request retransmission from the first device when the check fails.

6. The interconnect interface of claim 5, wherein:

The first receiver also includes an analysis module that analyzes the verified data for allocation to the plurality of channels of the second device.

7. The interconnect interface of claim 6, further comprising:

a second transmitter and a second receiver coupled to both ends of the electro-physical layer,

The second transmitter is coupled to the second device, and the second receiver is coupled to the first device, so that the interconnection interface is a full duplex structure.

8. The interconnect interface of claim 7, wherein:

the first transmitter further comprises a retransmission controller;

When the check logic module of the first receiver fails to check data, the second device transmits the retransmission request to the first device through the second transmitter, the electric physical layer and the second receiver, and the first device drives the retransmission controller to take out the content of the first buffer for retransmission.

9. The interconnect interface of claim 7, wherein:

The first transmitter further includes a state machine that, when switching to a reduced speed state, stops operation of the arbiter and reduces the transmission rate of the electro-physical layer.

10. The interconnect interface of claim 9, wherein:

the first transmitter further includes a second buffer for buffering the packet that has not been transmitted by the electro-physical layer when the state machine is in the reduced-speed state.

11. The interconnect interface of claim 10, wherein:

The first receiver also comprises a third buffer for buffering the data received from the electrical physical layer for verification and analysis;

When the third buffer is fully loaded, the second device transmits a speed reduction request to the first device through the second transmitter, the electric physical layer and the second receiver, and the first device enables the state machine to be switched into the speed reduction state.

12. The interconnect interface of claim 10, wherein:

the state machine is switched to the reduced speed state by the first device in response to a low power consumption setting.

13. The interconnect interface of claim 10, wherein:

The packet previously transmitted by the first device and the second device via the interconnect interface includes a unit code, a packet information, a cyclic redundancy check code, and a channel code;

Data from the first device or the second device is carried as the packet information;

The unit code marks the attribute of the grouping information; and

The cyclic redundancy check code and the channel code are used by a receiver to check the packet information.

14. The interconnect interface of claim 13, wherein:

the unit code includes data indicating that the packet information is dummy content or is taken from the device;

The unit code includes a flag indicating whether the packet information is a retransmission request; and

The unit code includes a flag indicating whether the packet information is fed back to the buffer status of the receiver to switch the interconnect interface to a down state.

15. The interconnect interface of claim 14, wherein:

The unit code includes a flag indicating whether the packet information is a power management request;

The unit code includes a flag indicating whether the packet information is valid content; and

The unit code includes a start, end, or idle flag indicating that the packet information is transmitted.

16. The interconnect interface of claim 6, wherein:

the first transmitter and the first receiver are pipelined hardware.

17. The interconnect interface of claim 6, wherein:

The linked first device and the second device are respectively a first package and a second package; and

The packets transmitted by the first and second packages through the interconnect interface are of indefinite length, 2 ^N bits in size, and N is a natural number.

18. The interconnect interface of claim 17, wherein:

the first transmitter further comprises a data compressor coupled between the arbiter and the packet generator, responsive to a request for inter-enclosure interconnect variable length packet transmission; and

The first receiver further includes a data reordering module that reorders data passing the verification to the analyzer in response to a request for transmission of packets of varying length to the inter-enclosure interconnect.

19. The interconnect interface of claim 6, wherein:

The first device and the second device are respectively a first chip and a second chip; and

The packets transmitted by the first chip and the second chip through the interconnect interface are of a fixed length.

20. The interconnect interface of claim 1, wherein:

The first device is in handshake communication with the first transmitter, such that the first transmitter obtains data from the first device, sends the data to the electro-physical layer for transmission to the first receiver; and

The first receiver communicates with the second device in a handshake that hands over data received from the electro-physical layer to the first receiver.