CN113884994B - FPGA-based radar diversified interference signal generation system - Google Patents
FPGA-based radar diversified interference signal generation system Download PDFInfo
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Abstract
The invention discloses a radar diversified interference signal generating system based on an FPGA, which comprises an interference parameter acquisition module, an interference signal generating module and a digital switch array, wherein the interference parameter acquisition module is used for acquiring an interference pattern type and corresponding parameter information according to an interference strategy from an upper computer; the interference signal generation module is used for generating various interference signals according to the interference pattern type and the corresponding parameter information; the digital switch array is used for selecting and outputting a corresponding interference signal or a combined waveform of a plurality of interference signals according to the type of the interference pattern. The radar diversified interference signal generation system not only can reduce the complexity and the implementation difficulty of radar interference waveform generation, but also can improve the diversity and the interference effect of the interference waveform, and has good real-time performance.
Description
Technical Field
The invention belongs to the technical field of signal processing, and particularly relates to a radar diversified interference signal generation system based on an FPGA.
Background
Radar interference is an important technical means in radar countermeasure, and can destroy and disturb the normal work of an enemy radar, so that the enemy radar cannot effectively play a role in a modern war complex electromagnetic environment. Radar interference can be classified into passive interference, which is interference generated by scattering, reflection, refraction, etc. of electromagnetic waves by non-target objects, and active interference, which is an interference mode in which a specific transmitter is used to intentionally transmit or forward some electromagnetic wave to disturb or fool an enemy radar device, according to energy sources.
At present, with the development of electronic technology and signal processing theory, the radar system is continuously upgraded, and a plurality of novel radars are generated. The capability of the radars for comprehensive processing in multiple domains such as a space domain, a time domain, a frequency domain and a modulation domain is obviously improved, so that the simple dependence on the traditional active interference pattern is insufficient to generate a good interference effect. In view of this, it is necessary to generate highly similar, rich diversity of interfering signals that are correlated with hostile radar signals.
In recent years, digital radio frequency memories (Digital Radio Frequency Memory, DRFM) are the primary technology for generating coherent interference signals, widely used in interference cancellation for non-coherent and coherent radars. The active interference signal generated by the DRFM can simulate the intra-pulse characteristic and the motion characteristic of a real echo signal, and has the same coherent processing gain as the real echo. The DRFM interference pattern is limited, mainly to create both repeater interference and spoofing interference, failing to cover the other large category of direction-compressed interference in active interference. Meanwhile, most DRFM interference generation methods have the problems of complex structure, general real-time performance and the like.
The field programmable gate array (Field Programmable GATE ARRAY, FPGA) is a digital integrated circuit device programmed by a user to implement desired logic functions, and has the characteristics of high parallelism and pipeline processing. Because of excellent performances of good time sequence control, rich high-speed interfaces and the like of the FPGA, the interference signals generated based on the FPGA can well meet the requirements of an interference system on interference signal relativity, pattern diversity and flexible parameter adjustability. However, the internal resources of the FPGA are limited, and the interference generating structure with too high complexity is difficult to realize, so that the interference generating structure with low complexity and high integration becomes a hot spot for research of industry-related personnel.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a radar diversified interference signal generation system based on an FPGA. The technical problems to be solved by the invention are realized by the following technical scheme:
the invention provides a radar diversified interference signal generating system based on an FPGA, which comprises an interference parameter acquisition module, an interference signal generating module and a digital switch array, wherein,
The interference parameter acquisition module is used for acquiring an interference pattern type and corresponding parameter information according to an interference strategy from the upper computer;
The interference signal generation module is used for generating various interference signals according to the interference pattern type and the parameter information;
The digital switch array is used for selecting and outputting a corresponding interference signal or a combined waveform of a plurality of interference signals according to the type of the interference pattern.
In one embodiment of the present invention, the interference signal generating module includes a repeating sub-module, a periodic intermittent repeating sub-module, a distance dragging interference sub-module, a speed modulating sub-module, a noise amplitude modulation sub-module, and a noise frequency modulation sub-module, which are respectively configured to obtain a repeating interference signal, a periodic intermittent repeating interference signal, a distance dragging interference signal, a speed modulating interference signal, a noise amplitude modulation interference signal, and a noise frequency modulation interference signal.
In one embodiment of the invention, the repeated forwarding submodule utilizes a dual-port RAM to realize repeated forwarding, specifically, detects the rising edge of a received radar signal, intercepts and stores a part of pulses of the radar signal when the rising edge of the radar signal is detected, and forwards signals with the same interception length one or more times according to the address sequence after the storage is completed.
In one embodiment of the invention, the cycle intermittent forwarding submodule utilizes a dual-port RAM to realize cycle intermittent forwarding, specifically, detects the rising edge of a received radar signal, intercepts and stores all pulses of the radar signal when the rising edge of the radar signal is detected, and forwards the pulse signal in a period without radar pulses according to the set number of interval pulses after the storage is completed.
In one embodiment of the present invention, the distance dragging interference submodule includes a first multiplier M1, a second multiplier M2, a third multiplier M3, a fourth multiplier M4, a fifth multiplier M5, a sixth multiplier M6, a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, a fifth register Reg5, a sixth register Reg6, and a first adder A1, wherein,
The first multiplier M1, the first register Reg1 and the second register Reg2 are sequentially connected in series, and the first multiplier M1 inputs D 0 andWherein D 0 is the initial distance between the radar and the interference signal generating system, and c is the light speed;
the second multiplier M2, the third multiplier M3, the third register Reg3 and the fourth register Reg4 are sequentially connected in series, and the second multiplier M2 inputs v and The output of the second multiplier M2 and the output of the third register Reg3 are used as the input of the third multiplier M3, wherein v is the towing speed, and T s is the sampling period;
the fourth multiplier M4, the fifth multiplier M5, the fifth register Reg5, the sixth multiplier M6 and the sixth register Reg6 are sequentially connected in series, and the fourth multiplier M4 inputs a and b The output of the fourth multiplier M4 and the output of the fifth register Reg5 serve as the input of the fifth multiplier M5, and the output of the fifth register Reg5 and the output of the sixth register Reg6 serve as the output of the sixth multiplier M6, wherein a is the towing acceleration;
The output of the second register Reg2, the output of the fourth register Reg4 and the output of the sixth register Reg6 are added in the first adder A1, so as to obtain a range gate drag delay time τ.
In one embodiment of the invention, the velocity modulation submodule includes a primary accumulation unit, a first direct digital frequency synthesizer, a first FIR filter and a first doppler modulator, wherein,
The primary accumulation unit is used for obtaining Doppler frequency shift component f d in the towing process according to the set towing speed and the set towing acceleration;
The first direct digital frequency synthesizer is used for generating a sine signal cos (2 pi f d n) and a cosine signal sin (2 pi f d n) according to the Doppler frequency shift component f d;
The first FIR filter is used for generating a quadrature component s Q (n) and a homodromous component s I (n) according to the acquired radar signal;
The first doppler modulator is configured to calculate and obtain a velocity-modulated interference signal according to the sine signal cos (2pi f d n), the cosine signal sin (2pi f d n), the orthogonal component s Q (n), and the homodromous component s I (n).
In one embodiment of the present invention, the primary accumulating unit includes a seventh multiplier M7, an eighth multiplier M8, a ninth multiplier M9, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a second adder A2, wherein,
The seventh multiplier M7, the seventh register Reg7 and the eighth register Reg8 are sequentially connected in series, and the seventh multiplier M7 inputs the towing speed v and the towing speed vWherein f c denotes a carrier frequency;
The eighth multiplier M8, the ninth multiplier M9, the ninth register Reg9 and the tenth register Reg10 are sequentially connected in series, and the eighth multiplier M8 inputs the towing acceleration a and the towing acceleration The output of the eighth multiplier M8 and the output of the ninth register Reg9 are taken as inputs of the ninth multiplier M9;
The output of the eighth register Reg8 and the output of the tenth register Reg10 are added in the second adder A2 to obtain a signal doppler shift component f d.
In one embodiment of the invention, the noise amplitude modulation submodule comprises a first M-sequence generating unit and a noise amplitude modulation unit, wherein,
The first M sequence generating unit is used for generating an M sequence;
the noise amplitude modulation unit is used for carrying out amplitude modulation on the received radar signal by utilizing the M sequence to obtain an interference signal after noise amplitude modulation.
In one embodiment of the invention, the noise frequency modulation sub-module comprises a second M-sequence generating unit, a second direct digital frequency synthesizer, a second FIR filter and a second doppler modulator, wherein,
The second M sequence generating unit is used for generating an M sequence f rand;
The second direct digital frequency synthesizer is used for generating a sine signal sin (2 pi f rand n) and a cosine signal cos (2 pi f rand n) according to the M sequence f rand;
The second FIR filter is used for generating a quadrature component s Q (n) and a homodromous component s I (n) according to the acquired radar signal;
The second doppler modulator is configured to calculate and obtain a speed-modulated interference signal according to the sine signal sin (2pi f rand n), the cosine signal cos (2pi f rand n), the orthogonal component s Q (n), and the homodromous component s I (n).
Compared with the prior art, the invention has the beneficial effects that:
1. the radar diversified interference signal generating system based on the FPGA can reduce complexity and implementation difficulty of radar interference waveform generation, can improve diversity and interference effect of interference waveforms, and has good real-time performance.
2. According to the radar diversified interference signal generating system based on the FPGA, the interference waveform parameters can be flexibly adjusted through the upper computer setting and the issuing of the interference pattern types and the parameter forms, the selectable dynamic range of the interference parameters is large, and the interference can be implemented on various system radars; the distance wave gate dragging and the speed dragging realize complex mathematical integral operation through secondary accumulation and primary accumulation respectively, so that operation steps are simplified. The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a block diagram of a radar diversity interference signal generating system based on an FPGA according to an embodiment of the present invention;
Fig. 2 is a repeated forwarding 1-to-2 interference timing diagram provided in an embodiment of the present invention;
FIG. 3 is a schematic diagram of implementing repeated forwarding by using dual-port RAM according to an embodiment of the present invention;
FIG. 4 is a schematic diagram comparing an original radar signal with a repeated repeating interference signal obtained using an embodiment of the present invention;
fig. 5 is a timing diagram of a periodically intermittent stop 1-to-1 forwarding interference provided by an embodiment of the present invention;
FIG. 6 is a schematic diagram of periodic intermittent forwarding implemented by using dual-port RAM according to an embodiment of the present invention;
FIG. 7 is a schematic diagram comparing an original radar signal with periodic intermittent forwarded interference signals obtained using an embodiment of the present invention;
FIG. 8 is a schematic diagram of a distance towing interference submodule according to an embodiment of the present invention;
FIG. 9 is a schematic diagram comparing an original radar signal with a range-pull interference signal obtained using an embodiment of the present invention;
FIG. 10 is a schematic diagram of a primary accumulation unit according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a method for generating Doppler shift amount according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of a speed modulation sub-module according to an embodiment of the present invention;
FIG. 13 is a schematic diagram comparing an original radar signal with a velocity modulated disturbance signal obtained using an embodiment of the present invention;
FIG. 14 is a schematic diagram of a 16-stage feedback shift register according to an embodiment of the present invention;
FIG. 15 is a schematic diagram of a noise amplitude modulation sub-module according to an embodiment of the present invention;
FIG. 16 is a waveform of a velocity modulated disturbance signal and a noise amplitude modulated disturbance power spectrum obtained with an embodiment of the present invention;
Fig. 17 is a schematic structural diagram of a noise modulation submodule according to an embodiment of the present invention;
fig. 18 is a waveform of a chirped interference signal and a noise chirped interference power spectrum obtained using an embodiment of the present invention.
Detailed Description
In order to further explain the technical means and effects adopted by the invention to achieve the preset aim, the following describes a radar diversified interference signal generating system based on the FPGA according to the invention in detail with reference to the attached drawings and the specific embodiments.
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments when taken in conjunction with the accompanying drawings. The technical means and effects adopted by the present invention to achieve the intended purpose can be more deeply and specifically understood through the description of the specific embodiments, however, the attached drawings are provided for reference and description only, and are not intended to limit the technical scheme of the present invention.
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element.
Referring to fig. 1, fig. 1 is a block diagram of a radar diversity interference signal generating system based on an FPGA according to an embodiment of the present invention. The radar diversified interference signal generation system comprises an interference parameter acquisition module 1, an interference signal generation module 2 and a digital switch array 3, wherein the interference parameter acquisition module 1 is used for acquiring an interference pattern type and corresponding parameter information according to an interference strategy from an upper computer 4; the interference signal generation module 2 is used for generating various interference signals according to the interference pattern type and the corresponding parameter information; the digital switch array 3 is used for selecting and outputting a corresponding interference signal or a combined waveform of a plurality of interference signals according to the type of the interference pattern.
In this embodiment, according to the received radar signal, an interference policy including an interference waveform, an interference parameter, and the like may be preset by the upper computer 4. The interference parameter acquisition module 1 is connected with the upper computer 4, and can receive an interference strategy issued by the upper computer and interpret the interference strategy to obtain an interference pattern type of an interference signal to be generated and corresponding parameter information.
The interference signal waveform design of this embodiment is mainly aimed at 6 waveforms of repeated forwarding, periodic intermittent forwarding, distance dragging, speed dragging, noise amplitude modulation, noise frequency modulation and the like and different types of combinations thereof, and simultaneously responds to an interference strategy issued by the upper computer 4, and selects a corresponding interference waveform or a digital combination of interference waveforms according to the strategy.
Based on this, the interference signal generating module 2 of the present embodiment includes a repeating sub-module 21, a period intermittent repeating sub-module 22, a distance dragging interference sub-module 23, a speed modulating sub-module 24, a noise amplitude modulating sub-module 25, and a noise frequency modulating sub-module 26, which are respectively configured to obtain a repeating interference signal, a period intermittent repeating interference signal, a distance dragging interference signal, a speed modulating interference signal, a noise amplitude modulating interference signal, and a noise frequency modulating interference signal.
The repeated forwarding of the interference signal is to firstly sample a part of the whole pulse interception of the obtained radar signal, then forward the signal with the same interception length after the sampling is completed, and then forward the signal with the same interception length continuously and repeatedly after the one-time forwarding is completed. If the pulse is still within the duration of the pulse width after the transfer is completed, the signal can be continuously sampled, and then the above-mentioned process is repeated. Referring to fig. 2, fig. 2 is a timing chart of repeated forwarding 1-to-2 interference provided in an embodiment of the present invention. Storing (1-1) a part of the radar pulse 1, then intercepting the pulse with the same length for forwarding (1-1-1), and then repeatedly forwarding (1-1-2) the intercepted pulse with the same length; after the forwarding is finished, the radar pulse is still in the pulse width duration, so the radar pulse is continuously intercepted and stored (1-2), then the pulse with the same intercepted length is forwarded (1-2-1, 1-2-2), and so on.
Referring to fig. 3, fig. 3 is a schematic diagram of implementing repeated forwarding by using a dual-port RAM provided by the embodiment of the present invention. The WrData ports of the dual-port RAM are written with radar original waveform data; wrEn port write enable flag, start storing data at the beginning of pulse rising edge; the WrAddr ports write the addresses of the data and store the addresses sequentially; reading data by the RdData port, and reading the stored radar data according to the address sequence; the RdEn port reads the enabling mark, and enables to read data after the storage is completed; rdAddr ports read addresses, store sequentially.
Specifically, the WrEn port detects the rising edge of the received radar signal, when the rising edge of the radar signal is detected, the WrData port starts to read and store the radar signal and intercept a part of the radar pulse, the storage length is the sampling point number corresponding to the intercepted radar signal pulse duration, after the storage is completed, the signals with the same interception length are read out according to the address sequence, and after the one-time forwarding is completed, the signals with the same interception length can be continuously repeated for a plurality of times. If the pulse is still within the duration of the pulse width after the retransmission is completed, the signal can be continuously sampled, and the repeated signal can be obtained, so that a repeated retransmission interference signal corresponding to the radar signal can be obtained, as shown in fig. 4.
The periodic intermittent forwarding interference signal is to sample the whole pulse of the radar signal, store the whole pulse data, then repeat the signal (multiple times) at a certain pulse repetition period, and then sample the signal for the next time, so as to repeat the signal. Referring to fig. 5, fig. 5 is a timing chart of a periodically intermittent stop 1-to-1 forwarding interference according to an embodiment of the present invention. After receiving the radar pulse N, intercepting and storing the whole radar signal (such as storing N), after the storage is completed, forwarding the pulse signal (such as forwarding N-1) in a period without the radar pulse at a certain sampling interval, and repeating the steps to obtain a periodic intermittent forwarding interference signal corresponding to the radar signal.
Referring to fig. 5, fig. 5 is a schematic diagram of implementing cycle intermittent forwarding by using a dual-port RAM provided by the embodiment of the present invention. The WrData ports of the dual-port RAM are written with radar original waveform data; wrEn port write enable flag, start storing data at the beginning of pulse rising edge; the WrAddr ports write the addresses of the data and store the addresses sequentially; reading data by the RdData port, and reading the stored radar data according to the address sequence; the RdEn port reads the enabling mark, and enables to read data after the storage is completed; rdAddr ports read addresses, store sequentially.
Specifically, the WrEn ports of the dual-port RAM detect a rising edge of a received radar signal, when the rising edge of the radar signal is detected, the WrData ports start to store and read the radar signal, intercept the radar data, store the number of sampling points with the length corresponding to the pulse width duration of the signal, and forward the pulse signal in a period without radar pulse after a certain sampling interval according to the sampling count acquired through WrAddr after the storage is completed, as shown in fig. 7.
Further, according to the range gate towing process, when the own towing rule is uniform acceleration towing, the pseudo-target distance function R j (t) corresponding to different pulses of the range towing interference signal can be expressed as
Wherein a is the acceleration during uniform acceleration towing, v is the uniform towing speed, R 0 is false target initial distance information, 0-t 1 is a stopping and towing period, t 1-t 2 is a towing period, t 2-t 3 is a stopping and towing period, and t 3-t 4 is an interference closing period.
The interference system carries out delay increment regular forwarding on each received radar pulse signal, and a delay forwarding quantity function delta t j (t) of different pulses of the distance towing interference pair is as follows:
the method can be used for obtaining the delay interference signal tau in the towing process, which shows quadratic change, and the delay can be calculated by a quadratic accumulation mode when the FPGA is realized.
Specifically, referring to fig. 8, fig. 8 is a schematic structural diagram of a distance towing interference submodule according to an embodiment of the present invention. The distance trailing interference submodule 23 includes a first multiplier M1, a second multiplier M2, a third multiplier M3, a fourth multiplier M4, a fifth multiplier M5, a sixth multiplier M6, a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, a fifth register Reg5, a sixth register Reg6, and a first adder A1, wherein the first multiplier M1, the first register Reg1, and the second register Reg2 are sequentially connected in series, and a first multiplier M1 input D 0 and a second multiplier M1 input D 0 Wherein D 0 is the initial distance between the radar and the interference signal generating system, and c is the light speed; the second multiplier M2, the third multiplier M3, the third register Reg3 and the fourth register Reg4 are sequentially connected in series, and the second multiplier M2 inputs v and vThe output of the second multiplier M2 and the output of the third register Reg3 serve as inputs to the third multiplier M3, where v is the towing speed and T s is the sampling period; the fourth multiplier M4, the fifth multiplier M5, the fifth register Reg5, the sixth multiplier M6 and the sixth register Reg6 are sequentially connected in series, and the fourth multiplier M4 inputs a and aThe output of the fourth multiplier M4 and the output of the fifth register Reg5 serve as the input of the fifth multiplier M5, and the output of the fifth register Reg5 and the output of the sixth register Reg6 serve as the output of the sixth multiplier M6, wherein a is the towing acceleration; the output of the second register Reg2, the output of the fourth register Reg4 and the output of the sixth register Reg6 are added in the first adder A1, thereby obtaining the range gate drag delay time τ.
Then, after each radar pulse is obtained, the radar pulse is forwarded after a range gate towing delay time τ has elapsed, thereby forming a range towing interference signal, as shown in fig. 9.
Further, for the speed modulation interference, the speed modulation submodule needs to perform frequency modulation on the radar pulse signal received each time, and when the own drawing rule is uniform acceleration drawing, the frequency offset f dj (t) change function of the false target generated by the speed drawing interference can be expressed as:
Wherein v 0 is the initial speed, the positive and negative of which are determined by the direction of the towing motion, a is the acceleration during uniform acceleration towing, the positive and negative of which are determined by the change rule of the towing speed, 0-t 1 is the stopping and towing period, t 1-t 2 is the towing period, t 2-t 3 is the stopping and towing period, and t 3-t 4 is the turning-off period.
From the above equation, the doppler shift component f d in the towing process shows a one-time change, and the doppler shift component can be calculated by one-time accumulation when the FPGA is implemented. Referring to fig. 10, fig. 10 is a schematic structural diagram of a primary accumulating unit according to an embodiment of the present invention. The primary accumulating unit 241 of the present embodiment includes a seventh multiplier M7, an eighth multiplier M8, a ninth multiplier M9, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a second adder A2, wherein the seventh multiplier M7, the seventh register Reg7, and the eighth register Reg8 are sequentially connected in series, and the seventh multiplier M7 inputs the trailing speed v and the trailing speed vWherein f c denotes a carrier frequency; an eighth multiplier M8, a ninth multiplier M9, a ninth register Reg9 and a tenth register Reg10 are sequentially connected in series, and the eighth multiplier M8 inputs the towing acceleration a andThe output of the eighth multiplier M8 and the output of the ninth register Reg9 are input to the ninth multiplier M9; the output of the eighth register Reg8 and the output of the tenth register Reg10 are added in the second adder A2 to obtain the signal doppler shift component f d. Each register is a register in the FPGA and is used for storing Doppler parameters.
Further, the doppler shift amount is usually generated by quadrature mixing, and referring to fig. 11, fig. 11 is a schematic diagram of the doppler shift amount generation according to an embodiment of the present invention.
Assume that the sampled radar echo signal is
The in-phase component after quadrature transformation is:
The orthogonal components are:
The orthogonal transformation may be implemented using a Hilbert Transformation (HT) by which orthogonal components are obtained. In the FPGA, hilbert transformation is realized through FIR filtering, specifically, the method comprises the steps of firstly generating a filter coefficient in Matlab, quantizing to a fixed point number with a fixed bit width, then importing the fixed point number into FPGA FIR IP cores, and filtering an original sampled radar signal.
Further, digital signals of cos (2pi f d n) and sin (2pi f d n) are generated by using a direct digital frequency Synthesizer (DIRECT DIGITAL Synthesizer, DDS), respectively multiplied by an in-phase component s I (n) and a quadrature component s Q (n), and then the two digital signals are subtracted to obtain:
As can be seen from the above equation, the digital quadrature mixed output s j (n) is one more doppler shift component f d than the echo signal s (n). By controlling the frequency of DDS synthesis, different Doppler shift frequency amounts can be generated after quadrature mixing, and false targets with different speeds can be formed. The FPGA can directly call the IP core of the DDS to realize the DDS technology.
Based on this, please refer to fig. 12, fig. 12 is a schematic diagram of a speed adjustment sub-module according to an embodiment of the present invention. The velocity modulation submodule 24 of the present embodiment includes a primary accumulating unit 241, a first direct digital frequency synthesizer 242, a first FIR filter 243 and a first doppler modulator 244, where the primary accumulating unit 241 is configured to obtain a doppler shift component f d in the towing process according to the set towing velocity and the set towing acceleration; the first direct digital frequency synthesizer 242 is configured to generate a sine signal cos (2pi f d n) and a cosine signal sin (2pi f d n) according to the doppler shift component f d; the first FIR filter 243 is used for generating a quadrature component s Q (n) and a co-directional component s I (n) according to the acquired radar signal; the first doppler modulator 244 is configured to calculate a velocity-modulated interference signal s j (n) according to the sine signal cos (2pi f d n), the cosine signal sin (2pi f d n), the quadrature component s Q (n), and the co-directional component s I (n).
Further, the noise amplitude modulation is to modulate the amplitude of the radar signal according to the change rule of the noise, and belongs to a form of the compression type interference. The noise signal is implemented in the FPGA by generating a pseudo-random sequence (M-sequence), which is the longest code sequence generated by a multistage shift register or its delay elements through linear feedback. In this embodiment, a 16-stage feedback shift register is used to generate an M-sequence, as shown in fig. 14, when 16-stage shift is used, the primitive polynomial of the corresponding M-sequence is x 16+x12+x3 +x+1, that is, C 1,3,12,16 =1, and the rest is zero, then
And (3) performing cyclic shift according to the above formula, outputting a pseudorandom number sequence with the bit width of 16 bits, and sequentially corresponding to a 0,a1,...,a15 from low order to high order.
As shown in fig. 15, the noise amplitude modulation sub-module 25 of the present embodiment includes a first M-sequence generating unit and a noise amplitude modulating unit, where the first M-sequence generating unit is configured to generate an M-sequence RanDat; the noise amplitude modulation unit is used for carrying out amplitude modulation on the received radar signal sig by using the M sequence to obtain an interference signal after noise amplitude modulation, and the modulation formula is as follows: (1+randat) sig, thereby obtaining a noise-modulated interference signal. As shown in fig. 16, the amplitude of the interference waveform is obviously modulated, conforming to the characteristics of noise amplitude modulation interference.
Further, noise frequency modulation is to modulate the frequency of a carrier signal according to the change rule of noise, and belongs to a form of compression type interference. The noise frequency modulation signal is generated in the FPGA similarly to the generation method of the speed towing, but the Doppler frequency of the speed towing is changed according to the kinematics rule, and the noise frequency modulation signal is randomly changed in a certain interval range and is irregular.
Specifically, as shown in fig. 17, the noise frequency modulation sub-module 26 of the present embodiment includes a second M-sequence generating unit 261, a second direct digital frequency synthesizer 262, a second FIR filter 263 and a second doppler modulator 264, where the second M-sequence generating unit 261 is configured to generate an M-sequence f rand; the second direct digital frequency synthesizer 262 is used for generating a sine signal sin (2 pi f rand n) and a cosine signal cos (2 pi f rand n) according to the M sequence f rand; the second FIR filter 263 is used for generating a quadrature component s Q (n) and a co-directional component s I (n) from the acquired radar signal; the second doppler modulator 264 is configured to calculate and obtain a velocity-modulated interference signal according to the sine signal sin (2pi f rand n), the cosine signal cos (2pi f rand n), the quadrature component s Q (n), and the homodromous component s I (n). As shown in fig. 18, the interference waveform frequency (spectrum) is obviously modulated, conforming to the characteristics of noise fm interference.
The digital switch array 3 is then used to select and output a corresponding interference signal or a combination waveform of multiple interference signals according to the type of interference pattern. Specifically, according to the type of interference obtained from the interference policy of the upper computer 4, the switch connected to the corresponding interference signal generating sub-module is turned on, so that the corresponding type of interference signal is output, and when a plurality of interference signals are input, the plurality of interference signals are combined. The common combined interference is noise interference and deception interference, so that the effect of suppressing the target can be achieved, and the radar can detect the false target so as to achieve the deception purpose. Multiple types of fraud may also be combined together, with the radar being spoofed in multiple dimensions of distance, speed, etc. Specifically, in the FPGA of this embodiment, a digital switch array is used to realize linear superposition output of multiple interference combinations, that is, to superpose multiple output interference signals of different types, that is, to obtain the finally generated interference signal.
The radar diversified interference signal generating system based on the FPGA not only can reduce the complexity and the implementation difficulty of radar interference waveform generation, but also can improve the diversity and the interference effect of the interference waveform, and has good real-time performance.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (7)
1. The radar diversified interference signal generating system based on the FPGA is characterized by comprising an interference parameter acquisition module (1), an interference signal generation module (2) and a digital switch array (3), wherein,
The interference parameter acquisition module (1) is used for acquiring an interference pattern type and corresponding parameter information according to an interference strategy from the upper computer (4);
The interference signal generation module (2) is used for generating various interference signals according to the interference pattern type and the parameter information;
The digital switch array (3) is used for selecting and outputting corresponding interference signals or combined waveforms of multiple interference signals according to the type of the interference pattern,
The interference signal generation module (2) comprises a repeated forwarding sub-module (21), a periodic intermittent forwarding sub-module (22), a distance dragging interference sub-module (23), a speed modulation sub-module (24), a noise amplitude modulation sub-module (25) and a noise frequency modulation sub-module (26) which are respectively used for obtaining repeated forwarding interference signals, periodic intermittent forwarding interference signals, distance dragging interference signals, speed modulation interference signals, noise amplitude modulation interference signals and noise frequency modulation interference signals;
The distance dragging interference submodule (23) comprises a first multiplier M1, a second multiplier M2, a third multiplier M3, a fourth multiplier M4, a fifth multiplier M5, a sixth multiplier M6, a first register Reg1, a second register Reg2, a third register Reg3, a fourth register Reg4, a fifth register Reg5, a sixth register Reg6 and a first adder A1, wherein,
The first multiplier M1, the first register Reg1 and the second register Reg2 are sequentially connected in series, and the first multiplier M1 inputs D 0 andWherein D 0 is the initial distance between the radar and the interference signal generating system, and c is the light speed;
the second multiplier M2, the third multiplier M3, the third register Reg3 and the fourth register Reg4 are sequentially connected in series, and the second multiplier M2 inputs v and The output of the second multiplier M2 and the output of the third register Reg3 are used as the input of the third multiplier M3, wherein v is the towing speed, and T s is the sampling period;
the fourth multiplier M4, the fifth multiplier M5, the fifth register Reg5, the sixth multiplier M6 and the sixth register Reg6 are sequentially connected in series, and the fourth multiplier M4 inputs a and b The output of the fourth multiplier M4 and the output of the fifth register Reg5 serve as the input of the fifth multiplier M5, and the output of the fifth register Reg5 and the output of the sixth register Reg6 serve as the output of the sixth multiplier M6, wherein a is the towing acceleration;
The output of the second register Reg2, the output of the fourth register Reg4 and the output of the sixth register Reg6 are added in the first adder A1, so as to obtain a range gate drag delay time τ.
2. The radar diversity interference signal generating system based on the FPGA of claim 1, wherein the repeating sub-module (21) uses a dual port RAM to implement repeating, specifically, detects a rising edge of a received radar signal, intercepts and stores a part of pulses of the radar signal when the rising edge of the radar signal is detected, and after the storing is completed, forwards signals with the same interception length one or more times in address order.
3. The radar diversity interference signal generating system based on the FPGA of claim 1, wherein the cycle intermittent forwarding sub-module (22) uses a dual port RAM to implement cycle intermittent forwarding, specifically, detects a rising edge of a received radar signal, intercepts and stores all pulses of the radar signal when the rising edge of the radar signal is detected, and forwards the pulse signal in a period without radar pulses according to a set number of interval pulses after the storage is completed.
4. The FPGA-based radar diversity jamming signal generating system of claim 1, wherein the speed modulation sub-module (24) includes a primary accumulation unit (241), a first direct digital frequency synthesizer (242), a first FIR filter (243), and a first doppler modulator (244), wherein,
The primary accumulation unit (241) is used for obtaining a Doppler frequency shift component f d in the towing process according to the set towing speed and the set towing acceleration;
The first direct digital frequency synthesizer (242) is configured to generate a sine signal cos (2pi f d n) and a cosine signal sin (2pi f d n) according to the doppler shift component f d;
the first FIR filter (243) is used for generating a quadrature component s Q (n) and a homodromous component s I (n) according to the acquired radar signal;
the first Doppler modulator (244) is configured to calculate and obtain a velocity modulated interference signal according to the sine signal cos (2pi f d n), the cosine signal sin (2pi f d n), the orthogonal component s Q (n) and the homodromous component s I (n).
5. The FPGA-based radar diversity jamming signal generating system of claim 4, wherein the primary accumulating unit (241) includes a seventh multiplier M7, an eighth multiplier M8, a ninth multiplier M9, a seventh register Reg7, an eighth register Reg8, a ninth register Reg9, a tenth register Reg10, and a second adder A2, wherein,
The seventh multiplier M7, the seventh register Reg7 and the eighth register Reg8 are sequentially connected in series, and the seventh multiplier M7 inputs the towing speed v and the towing speed vWherein f c denotes a carrier frequency;
The eighth multiplier M8, the ninth multiplier M9, the ninth register Reg9 and the tenth register Reg10 are sequentially connected in series, and the eighth multiplier M8 inputs the towing acceleration a and the towing acceleration The output of the eighth multiplier M8 and the output of the ninth register Reg9 are taken as inputs of the ninth multiplier M9;
The output of the eighth register Reg8 and the output of the tenth register Reg10 are added in the second adder A2 to obtain a signal doppler shift component f d.
6. The FPGA-based radar diversity jamming signal generating system of claim 1, wherein the noise amplitude modulation sub-module (25) includes a first M-sequence generating unit (251) and a noise amplitude modulating unit (252), wherein,
The first M sequence generation unit (251) is used for generating an M sequence;
the noise amplitude modulation unit (252) is used for carrying out amplitude modulation on the received radar signal by using the M sequence to obtain an interference signal after noise amplitude modulation.
7. The FPGA-based radar diversity jamming signal generating system according to any of claims 1-6, wherein the noise-frequency-modulation sub-module (26) includes a second M-sequence generating unit (261), a second direct digital frequency synthesizer (262), a second FIR filter (263), and a second doppler modulator (264), wherein,
The second M sequence generating unit (261) is used for generating an M sequence f rand;
-said second direct digital frequency synthesizer (262) is arranged to generate a sine signal sin (2pi f rand n) and a cosine signal cos (2pi f rand n) from said M-sequence f rand;
The second FIR filter (263) is used for generating a quadrature component s Q (n) and a homodromous component s I (n) according to the acquired radar signal;
The second Doppler modulator (264) is configured to calculate and obtain a velocity modulated interference signal according to the sine signal sin (2pi f rand n), the cosine signal cos (2pi f rand n), the orthogonal component s Q (n) and the homodromous component s I (n).
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