CN113889484A - Three-dimensional memory and preparation method thereof - Google Patents

Abstract

The present application provides a three-dimensional memory and a preparation method thereof. The method includes: forming a first insulating layer on a substrate, and sequentially forming a semiconductor layer and a stacked structure on a first portion of the first insulating layer; forming a memory string structure penetrating the stacked structure and electrically coupled with the semiconductor layer; forming passing through a first contact structure of the second portion of the first insulating layer; removing the substrate to expose the first contact structure; and forming a first pad structure connected to the first contact structure. The method simplifies the preparation process of the three-dimensional memory, increases the process window of the back-end process process, and is compatible with the process of forming a common source pick-up region on the backside.

Description

Three-dimensional memory and preparation method thereof

Technical Field

The present disclosure relates to the field of semiconductor technologies, and more particularly, to a three-dimensional memory and a method for fabricating the same.

Background

In the Xtacking architecture based three-dimensional memory (3D NAND), peripheral circuits responsible for data I/O and memory cell operations are formed on the same substrate, while a memory string structure is formed on another substrate. After the two semiconductor structures are respectively prepared, the two semiconductor structures are connected in a bonding mode, so that the memory string structure and the peripheral circuit are connected. In addition, it is also necessary to form metal layers on the back side of the substrate of the semiconductor structure having the memory string structure or the semiconductor structure having the peripheral circuit, and these metal layers are used to form the pad structure.

In the prior art, in the process of forming the Xtacking architecture three-dimensional memory, the process for forming the memory string structure and the pad structure is high in complexity, which is not favorable for actual production requirements. Therefore, it is one of the technical problems to be solved at present to provide a method for manufacturing a three-dimensional memory with simple process and low complexity and a three-dimensional memory.

Disclosure of Invention

The application provides a preparation method of a three-dimensional memory, which comprises the following steps: forming a first insulating layer on a substrate, and sequentially forming a semiconductor layer and a stacked structure on a first portion of the first insulating layer; forming a memory string structure penetrating through the stacked structure and electrically coupled to the semiconductor layer; forming a first contact structure through a second portion of the first insulating layer; removing the substrate to expose the first contact structure; and forming a first pad structure connected to the first contact structure.

In some embodiments, a second insulating layer is formed on the second portion of the first insulating layer, wherein the step of forming the first contact structure through the second portion of the first insulating layer may include: a first contact structure is formed through the second insulating layer and the second portion of the first insulating layer.

In some embodiments, the step of forming a memory string structure extending through the stacked structure and electrically coupled to the semiconductor layer may comprise: forming an opening penetrating through the laminated structure and extending to the semiconductor layer to expose the semiconductor layer; forming a functional layer on the side wall of the opening; forming a channel layer on a surface of the functional layer and a portion of the semiconductor layer exposed to the opening; and forming a doped region at a portion of the channel layer adjacent to the semiconductor layer.

In some embodiments, after the step of removing the substrate to expose the first contact structure, the method may further comprise: forming a second contact structure penetrating the first portion of the first insulating layer and connected to the semiconductor layer; and forming a second pad structure connected to the second contact structure.

In some embodiments, prior to the step of removing the substrate to expose the first contact structure, the method may further comprise: an interconnect layer is formed that is electrically coupled to the memory string structure and/or the first contact structure.

In some embodiments, the three-dimensional memory includes a peripheral circuit semiconductor structure, wherein, after the step of forming an interconnect layer electrically coupled to the memory string structure and/or the first contact structure, the method may further include: and bonding and connecting the semiconductor structure of the peripheral circuit structure on the interconnection layer.

In some embodiments, the semiconductor layer may be an N-type doped polysilicon layer.

The application also provides a three-dimensional memory. The three-dimensional memory includes a first semiconductor structure including: a first insulating layer; a semiconductor layer on a first portion of the first insulating layer; a stacked structure on the semiconductor layer; a memory string structure extending through the stacked structure and electrically coupled to the semiconductor layer; a first contact structure; and a first pad structure; the semiconductor layer, the laminated structure and the memory string structure are located on a first side of the insulating layer, the first contact structure penetrates through a second portion of the first insulating layer from the first side, and the first pad structure is located on a second side opposite to the first side and connected with the first contact structure.

In some embodiments, the first semiconductor structure further comprises: and a second insulating layer on a second portion of the first insulating layer, wherein the first contact structure may pass through the second insulating layer and the second portion of the first insulating layer.

In some embodiments, the memory string structure may include a functional layer and a channel layer from outside-in a radial direction thereof, the channel layer extending into the semiconductor layer, and a portion of the channel layer proximate to the semiconductor layer may have a doped region.

In some embodiments, the first semiconductor structure may further include: a second contact structure penetrating the first portion of the insulating layer and connected to the semiconductor layer; and a second pad structure located at the second side and connected to the second contact structure.

In some embodiments, the three-dimensional memory further includes a peripheral circuit semiconductor structure bonded to the first semiconductor structure.

In some embodiments, the first semiconductor structure further comprises an interconnect layer at the first side, wherein the peripheral circuit semiconductor structure and the first semiconductor structure are electrically coupled with the memory string structure and/or the first contact structure through the interconnect layer.

In some embodiments, the semiconductor layer may be an N-type doped polysilicon layer.

According to the preparation method of the three-dimensional memory, the insulating layer and the semiconductor layer are sequentially formed on the substrate, and the first contact structure penetrates through the insulating layer to the substrate, so that the first pad structure connected with the first contact structure can be directly formed after the subsequent substrate removing process, and the pre-formed semiconductor layer can be used for forming the common source electric coupling region of the plurality of memory string structures. The method simplifies the preparation process of the three-dimensional memory, increases the process window of the back-end process, and is compatible with the process of forming the common source pick-up region on the back side.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:

fig. 1 is a flowchart of a method of manufacturing a three-dimensional memory according to an embodiment of the present application; and

fig. 2A to 2G are schematic process cross-sectional views illustrating a method for fabricating a three-dimensional memory according to an embodiment of the present disclosure.

Detailed Description

For a better understanding of the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that the detailed description is merely illustrative of exemplary embodiments of the present application and does not limit the scope of the present application in any way.

The terminology used herein is for the purpose of describing particular example embodiments and is not intended to be limiting. The terms "comprises," "comprising," "includes" and/or "including," when used in this specification, specify the presence of stated features, integers, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, elements, components, and/or groups thereof.

This description is made with reference to schematic illustrations of exemplary embodiments. The exemplary embodiments disclosed herein should not be construed as limited to the particular shapes and dimensions shown, but are to include various equivalent structures capable of performing the same function, as well as deviations in shapes and dimensions that result, for example, from manufacturing. The locations shown in the drawings are schematic in nature and are not intended to limit the location of the various components.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. The layer can extend over the entire underlying or overlying structure or can have a smaller extent than the underlying or overlying structure. Furthermore, the layer can be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer can be located between any set of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layers can extend horizontally, vertically, and/or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereon, above, and/or below. The layer can comprise a plurality of layers.

The application provides a method 1000 for manufacturing a three-dimensional memory. Fig. 1 is a flow chart of a method 1000 of fabricating a three-dimensional memory according to an embodiment of the present application. As shown in fig. 1, the method 1000 for manufacturing a three-dimensional memory includes steps S110 to S150.

Fig. 2A to 2G are schematic process cross-sectional views illustrating a method 1000 for fabricating a three-dimensional memory according to an embodiment of the present disclosure. It should be understood that the steps shown in method 1000 are not exclusive and that other steps may be performed before, after, or between any of the steps shown. Further, some of the steps may be performed simultaneously or may be performed in an order different from that shown in fig. 1. The above steps S110 to S150 are further described below with reference to fig. 2A to 2G.

S110, forming a first insulating layer on the substrate, and sequentially forming semiconductors on a first portion of the first insulating layer Layers and laminate structures.

In step S110, as shown in fig. 2A, the substrate 110 may be used to support device structures thereon. The substrate 110 may be a single crystal silicon (Si) substrate, a single crystal germanium (Ge) substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like. The material of the substrate may also be a compound semiconductor. For example, the substrate may be a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, a silicon carbide (SiC) substrate, or the like. Substrate 110 may be a bulk wafer or an epitaxial layer. It is noted that the substrate 110 described herein may also be fabricated using at least one of the other semiconductor materials known in the art.

In an exemplary embodiment of this step, the first insulating layer 120, the semiconductor layer 130, and the stacked structure 140 may be sequentially stacked on the substrate 110 using a thin film deposition process such as Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), or any combination thereof (refer to fig. 2B). In this exemplary embodiment, the semiconductor layer 130 may, for example, cover the entire first insulating layer 120 (e.g., the first portion 120-1 of the first insulating layer 120 and the second portion 120-2 of the first insulating layer), the stacked structure 140 may, for example, cover the entire semiconductor layer 130 (refer to fig. 2), and portions of the semiconductor layer 130 and the stacked structure 140 outside the first portion 120-1 are removed during a subsequent process (e.g., a process of forming a step) such that the semiconductor layer 130 and the stacked structure 140 are formed on the first portion 120-1 of the first insulating layer 120 (refer to fig. 2C).

In some embodiments, the material of the first insulating layer 120 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating materials. The material of the semiconductor layer 130 may include, but is not limited to, doped monocrystalline silicon, polycrystalline silicon, or any other suitable semiconductor material. The semiconductor layer 130 may be connected to a memory string structure formed in a subsequent process and may serve as a common source electrical coupling region of the plurality of memory string structures. In some examples, the material of the semiconductor layer 130 may be an N-type doped polysilicon layer doped with an N-type dopant (e.g., phosphorus). Alternatively, N-type dopant incorporation can be achieved by, for example, a heat soak.

In some embodiments, as shown in fig. 2B, the stacked structure 140 may include a plurality of dielectric layers 141 and sacrificial layers 142 alternately stacked in a direction perpendicular to the substrate 110. Illustratively, a plurality of dielectric layers 141 and a plurality of sacrificial layers 142 may be formed on the semiconductor layer 130 (e.g., overlying the semiconductor layer 130 corresponding to the first and second portions 120-1 and 120-2 of the first insulating layer 120) using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The dielectric layer 141 and the sacrificial layer 142 may be made of materials with different etching selectivity, for example, the material of the dielectric layer 141 may be silicon oxide, and the material of the sacrificial layer 142 may be silicon nitride. The sacrificial layer 142 can be replaced by a gate layer during subsequent processing, and the gate layer can serve as a word line for memory cells in the memory string structure 150. Therefore, the number of stacked layers of the dielectric layer 141 and the sacrificial layer 142 may be designed according to actual memory requirements. For example, the number of stacked dielectric layers 141 and sacrificial layers 142 may be 8, 32, 64, 128, etc., which is not specifically limited in this application.

And S120, forming a memory string structure penetrating through the laminated structure and electrically coupled with the semiconductor layer.

In this step, as shown in fig. 2B, the memory string structure 150 is formed throughout the stacked structure 140 in the vertical direction (z-axis direction). Illustratively, a plurality of memory string structures 150 may be arranged apart from each other in a plane parallel to the substrate 110 (xy-plane) to form an array of memory string structures (not shown). Illustratively, each storage string structure 150 may have a circular shape in the xy-plane, and have a cylindrical shape for the storage string structure 150. However, the shape of the memory string structure 150 is not specifically limited in the present application, and the shape of the memory string structure 150 may also be a truncated cone, a prism, or the like.

In some embodiments, a method of forming the memory string structure 150 may include: openings are formed through the stacked structure 140 and extending to the semiconductor layer 130 using, for example, a dry or wet etching process. Further, a functional layer 154 including a blocking layer 151, a charge trapping layer 152 and a tunneling layer 153 may be sequentially formed on the sidewall of the opening using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. In other words, the functional layer 154 may include the blocking layer 151, the charge trap layer 152, and the tunneling layer 153, and the materials of the blocking layer 151, the charge trap layer 152, and the tunneling layer 153 may be silicon oxide, silicon nitride, and silicon oxide, in this order.

Further, a deep hole etching process (SONO etch) may be employed to remove a portion of the functional layer 154 in contact with the semiconductor layer 130 to expose the semiconductor layer 130. After the above process, the functional layer 154 may be located on the sidewall of the opening and separated at the bottom in contact with the semiconductor layer 130.

Further, the channel layer 155 may be formed on the surface of the functional layer 154 and the surface of the semiconductor layer 130 exposed to the opening using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The channel layer 155 may be made of the same material as the semiconductor layer 130, for example, doped polysilicon. After the above-described processes, the channel layer 155 may be in contact with the semiconductor layer 130, thereby forming an electrical connection path between the semiconductor layers 130 of the channel layer 155. Illustratively, the doped region 156 may be formed at a portion of the channel layer 155 near the semiconductor layer 130 using, for example, an ion implantation process and a laser annealing process. Illustratively, the doped region 156 may be doped with an N-type dopant (e.g., phosphorus), and the height of the doped region 156 in the z-axis direction may be greater than the height at which the at least one sacrificial layer 142 is located. The doped regions 156 and the corresponding functional layers 154 may be used to form bottom select transistors, and the bottom select transistors may have different threshold voltage values by adjusting the doping concentration of the doped regions 156. In some embodiments, the opening in which the functional layer 154 and the channel layer 155 are formed may be filled with an insulating material using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The insulating material may be, for example, silicon oxide, silicon nitride, or silicon oxynitride. Optionally, one or more air gaps may be formed during the filling process to relieve structural stress by controlling the filling process.

In some embodiments, a portion of the insulating material at the aperture may be etched back and filled with a conductive material using, for example, a dry or wet etching process, thereby forming a channel plug 157 in contact with the channel layer 155. The channel plug 157 may be made of the same material as the channel layer 155, such as doped polysilicon, and the channel plug 157 may serve as a drain terminal of the memory string structure 150.

After the above-described process, the direction in which the memory string structure 150 extends along the z-axis may be an axial direction thereof, and the memory string structure 150 may include a functional layer 154 and a channel layer 155 from outside to inside along a radial direction thereof, the channel layer 155 extending into the semiconductor layer 130 and electrically coupled with the semiconductor layer 130. A portion of the channel layer 155 adjacent to the semiconductor layer 130 may have a doped region 156.

In some embodiments, as shown in fig. 2C, a gate slit (not shown) extending through the stacked structure 140 and toward the substrate 110 may be formed by, for example, a dry or wet etching process. Further, all of the sacrificial layer 142 may be removed using, for example, a wet etching process using the formed gate slits as a passage for an etchant to form a plurality of sacrificial gaps. Further, the gate layer 143 may be formed within the plurality of sacrificial gaps using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, thereby replacing the sacrificial layer 142 within the stacked-layer structure 140 with the gate layer 143.

In some embodiments, the step structure may be formed by performing a plurality of "trim-etch" cycles to the plurality of dielectric layers 141 and the plurality of sacrificial layers 142 in the stacked-layer structure 140 before the process of "gate replacement". Wherein the exposed sacrificial layer 142 of the step structure in the direction parallel to the substrate 110 can be used as a contact region for a conductive channel formed during a subsequent process. In the process of forming the stepped structure, a portion of the stacked structure 140 and the semiconductor layer 130 corresponding to the second portion 120-2 of the first insulating layer 120 may be removed, so that the stacked structure 140 and the semiconductor layer 130 are positioned at a portion of the first portion 120-1 of the first insulating layer 120. Alternatively, the above-described process may be performed before the memory string structure 150 is formed.

In some embodiments, a top side of the second portion 121-2 of the first insulating layer and the step structure may be filled with an insulating material using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The insulating material may be made of the same material as the first insulating layer 120, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulating material. Herein, a layer formed of the insulating material on the second portion 121-2 of the first insulating layer may be referred to as a second insulating layer 122. Alternatively, the insulating material may cover the top surface of the stack structure 140, i.e., the insulating material may cover the end surface of the memory string structure 150 away from the substrate 110. Alternatively, a mechanical chemical polishing (CMP) process may be used to planarize the surface of the insulating material remote from the substrate 110.

S130, a first contact structure is formed through the second portion of the first insulating layer.

In step S130, as shown in fig. 2D, the first contact structure 161 extends to the surface of the substrate 110 through the second insulating layer 122 and the second portion 120-2 of the first insulating layer. Optionally, the first contact structure 161 may extend into the substrate 110, which is not specifically limited in this application. In one aspect, the first contact structure 161 may be used to transmit electrical signals between peripheral circuitry formed in the peripheral circuitry semiconductor structure and the memory string structure 150. On the other hand, the first contact structure 161 may be used for connection with a first pad structure formed in a subsequent process.

In some embodiments, the method of forming the first contact structure 161 may include: a first opening extending vertically to the substrate 110 is formed in the second portion 120-2 of the first insulating layer and the second insulating layer 122 using, for example, a dry or wet etching process. Further, a thin film deposition process such as ALD, CVD, PVD or any combination thereof may be employed to fill the conductive material into the first opening to form the first contact structure 161. The conductive material may include, but is not limited to, tungsten, cobalt, copper, aluminum, silicide, or any combination thereof.

In this step, a plurality of second openings may be simultaneously formed during the process of forming the first openings. A second opening may be formed in the insulating material covering the top side of the stepped structure and vertically extending to the gate layer 143 exposed in the stepped structure. Further, a thin film deposition process such as ALD, CVD, PVD, or any combination thereof may be used to fill the conductive material into the second opening to form the conductive via 162. The conductive material may include, but is not limited to, tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. The conductive via 162 contacts the gate layer 143 and may serve as an electrical connection structure for the gate layer 143 (word line).

In some embodiments, after forming the conductive via 162 and the first contact structure 161, the method further comprises the step of forming an interconnect layer 170. Specifically, the dielectric fill layer may be formed first using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The dielectric fill layer may cover the end surfaces of the first contact structures 161 and the conductive vias 162 that are remote from the substrate 110, and the material of the dielectric fill layer may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric, among other suitable materials. Further, a plurality of openings extending in a direction perpendicular to the substrate 110 may be formed through the dielectric filling layer and exposing the memory string structure 150, the first contact structure 161, and the conductive vias 162 using, for example, a dry or wet etching process. Further, a conductive material such as tungsten, cobalt, copper, aluminum, titanium, or any combination thereof may be filled in the opening using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof to form an interconnect via (via). Further, the same process may be used to form a dielectric fill layer, then to form an opening extending through the dielectric fill layer and exposing the interconnect via and extending laterally, and then to fill the opening with a conductive material to form the interconnect line. Further, the above process may be repeated to sequentially form the interconnect channel layer and the interconnect line layer at different levels until the plurality of memory string structures 150 electrically coupled to the interconnect layer 170 and the first contact structure 161 are brought into a predetermined functional circuit connection relationship. The dielectric filling layer processed by the above process may be a discrete layer structure at different horizontal levels, and may be further referred to as an interlayer dielectric layer. In other words, the interconnect layer 170 may include interconnect vias and interconnect lines in multiple inter-level dielectric layers.

In some embodiments, after forming the interconnect layer 170, as shown in fig. 2E, the method further includes the step of bonding connection with the peripheral circuit structure semiconductor structure 200. Wherein a plurality of driving devices for driving the memory string structure 150 may be formed in the peripheral circuit semiconductor structure 200. The driving devices may include, but are not limited to, active and/or passive semiconductor devices such as transistors, diodes, resistors, capacitors, and the like. The plurality of driving devices may form a peripheral circuit according to a preset circuit function. Illustratively, the peripheral circuits may include, but are not limited to, circuit blocks such as page buffers, address decoders, and read amplifiers. It is noted that the peripheral circuit semiconductor structure 200 can be formed simultaneously with the above processes, so that the peripheral circuit semiconductor structure 200 and the semiconductor structure including the memory string structure 150 can be processed in parallel to improve the efficiency of manufacturing. Illustratively, the peripheral circuit semiconductor structure 200 may include a device layer 220 and an interconnect layer 230 on a substrate 210 in sequence.

In this step, interconnect vias and/or interconnect lines in interconnect layer 170/230 may be exposed at the surface of interconnect layer 170/230 remote from substrate 110/230 and may serve as bonding contacts for the semiconductor structure formed by the above-described process and peripheral circuit semiconductor structure 200. Further, the semiconductor structure formed by the above process may be positioned on the peripheral circuit semiconductor structure 200 by aligning the bonding contacts located in the two semiconductor structures with each other, such that the two semiconductor structures are electrically connected at the positions where the bonding contacts are aligned, thereby electrically connecting the memory string structure 150 and the driving device in the peripheral circuit semiconductor structure 200.

And S140, removing the substrate to expose the first contact structure.

In step S140, as shown in fig. 2F, the substrate 110 may be removed from the back side of the substrate 110 (i.e., the side where the structures such as the memory string structure 150 are not formed) by using, for example, a CMP process. Illustratively, the substrate 110 may be thinned a plurality of times using, for example, a CMP process to expose an end portion of the first contact structure 161 remote from the substrate 110. In some embodiments, in the case where the first contact structure 161 extends into the substrate 110 (not shown), a majority of the substrate 110 may be removed from the backside of the substrate 110 using, for example, a CMP process, and then the remaining portion of the substrate 110 may be removed using, for example, a wet or dry etching process, such that after the substrate 110 is removed, the first contact structure 161 protrudes from the surface of the second portion 120-1 of the first insulating layer. In addition, the surface of the first portion 120-1 of the first insulating layer is also exposed after the above process.

In some embodiments, after the step of removing the substrate 110, the second contact structure 163 may be formed using, for example, a wet or dry etching process and a thin film deposition process. The second contact structure 163 may be made of the same material as the first contact structure 161, such as a conductive material of tungsten, cobalt, copper, aluminum, silicide, or any combination thereof. The second contact structure 163 penetrates the first portion 121-1 of the first insulating layer and is in contact with the semiconductor layer 130. The second contact structure 163 may be used to electrically connect the common source electrical coupling regions (the semiconductor layer 130) of the plurality of memory string structures 150 and serve as an electrical connection structure for a pad structure formed in a subsequent process.

And S150, forming a first pad structure connected with the first contact structure.

In step 150, as shown in fig. 2G, on the back side of the substrate 110, a first pad structure 181 may be formed in contact connection with the first contact structure 161 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The first pad structure 181 may be made of a conductive material selected from tungsten, cobalt, copper, aluminum, titanium, or any combination thereof. For example, in the case that the first pad structure 181 is made of aluminum, on the back side of the substrate 110, a metal aluminum layer may be formed on the surface of the first insulating layer 121 (including the first portion 121-1 and the second portion 121-2) by using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and then the first pad structure 181 for leading out the first contact structure 161 may be formed by using, for example, photolithography and a dry or wet etching process.

In some embodiments, the second pad structure 182 may be formed using the same process. The second pad structure 182 is in contact with the second contact structure 163, and may be made of the same material as the first contact structure 161, such as aluminum, for leading out the common source electrical coupling region (semiconductor layer 130) of the memory string structure 150. Alternatively, a dielectric material 183 such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof may be filled between the first and second pad structures 181 and 182 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

In some related arts, an electrical connection path is formed between the channel layer and the semiconductor layer, typically using a process method as described below. For example, a stacked-layer structure including no first insulating layer and no semiconductor layer is formed over a substrate. Further, a memory string structure may be formed that extends into, for example, the substrate. Since the semiconductor layer is not formed in advance, an electrical connection path between the channel layer and the semiconductor layer cannot be formed in advance. In general, it is necessary to remove the substrate to expose the channel layer, and to form an electrical connection path between the channel layer and the semiconductor layer by forming the semiconductor layer in contact with the channel layer.

In contrast to the related art described above, according to the method of manufacturing a three-dimensional memory according to some embodiments of the present application, the electrical connection channel between the channel layer and the semiconductor layer may be previously formed by previously forming the first insulating layer and the semiconductor layer on the substrate. After the substrate is removed, the semiconductor layer and the first contact structure can be exposed, and the first pad structure and the second pad structure can be formed through the same mask in the subsequent process of forming the first pad structure and the second pad structure, so that the process flow is simplified, and the mask cost is reduced.

According to the preparation method of the three-dimensional memory, the preparation process of the three-dimensional memory can be simplified, the process window of the back-end process can be increased, and the preparation method is compatible with the process of forming the common source pick-up region on the back side.

The application also provides a three-dimensional memory. The three-dimensional memory includes: a first insulating layer; a semiconductor layer on a first portion of the first insulating layer; a stacked structure on the semiconductor layer; a memory string structure extending through the stacked structure and electrically coupled to the semiconductor layer; a first contact structure; and a first pad structure; the semiconductor layer, the laminated structure and the memory string structure are located on a first side of the insulating layer, the first contact structure penetrates through a second portion of the first insulating layer from the first side, and the first pad structure is located on a second side opposite to the first side and connected with the first contact structure. Since the contents and structures referred to in the above description of the manufacturing method 1000 may be fully or partially applicable to the three-dimensional memory device described herein, the contents related or similar thereto will not be described in detail.

The above description is only a preferred embodiment of the present application and is illustrative of the principles of the technology employed. It will be appreciated by a person skilled in the art that the scope of the invention as referred to in the present application is not limited to the embodiments with a specific combination of the above-mentioned features, but also covers other embodiments with any combination of the above-mentioned features or their equivalents without departing from the inventive concept. For example, the above features may be replaced with (but not limited to) features having similar functions disclosed in the present application.

Claims (14)

1. A method for preparing a three-dimensional memory is characterized by comprising the following steps:

forming a first insulating layer on a substrate, and sequentially forming a semiconductor layer and a stacked structure on a first portion of the first insulating layer;

forming a memory string structure through the stacked structure and electrically coupled to the semiconductor layer;

forming a first contact structure through a second portion of the first insulating layer;

removing the substrate to expose the first contact structure; and

a first pad structure is formed in connection with the first contact structure.

2. The method of claim 1, wherein a second insulating layer is formed on the second portion of the first insulating layer, and wherein forming the first contact structure through the second portion of the first insulating layer comprises:

a first contact structure is formed through the second insulating layer and a second portion of the first insulating layer.

3. The method of claim 1, wherein forming a memory string structure extending through the stack and electrically coupled to the semiconductor layer comprises:

forming an opening through the stacked structure and extending to the semiconductor layer to expose the semiconductor layer;

forming a functional layer on the side wall of the opening;

forming a channel layer on a surface of the functional layer and a portion of the semiconductor layer exposed to the opening; and

and forming a doped region on the channel layer close to the semiconductor layer.

4. The method of manufacturing according to claim 1 or 2, wherein after the step of removing the substrate to expose the first contact structure, the method further comprises:

forming a second contact structure penetrating through a first portion of the first insulating layer and connected with the semiconductor layer; and

forming a second pad structure connected to the second contact structure.

5. The method of manufacturing of claim 4, wherein prior to the step of removing the substrate to expose the first contact structure, the method further comprises:

forming an interconnect layer electrically coupled to the memory string structure and/or the first contact structure.

6. The method of manufacturing of claim 5, wherein the three-dimensional memory comprises a peripheral circuit semiconductor structure, wherein, after the step of forming an interconnect layer electrically coupled to the memory string structure and/or the first contact structure, the method further comprises:

and bonding and connecting the peripheral circuit semiconductor structure on the interconnection layer.

7. The method according to claim 1 or 6, wherein the semiconductor layer is an N-type doped polysilicon layer.

8. A three-dimensional memory, comprising a first semiconductor structure, comprising:

a first insulating layer;

a semiconductor layer on a first portion of the first insulating layer;

a stacked structure on the semiconductor layer;

a memory string structure extending through the stacked structure and electrically coupled to the semiconductor layer;

a first contact structure; and

a first pad structure;

wherein the semiconductor layer, the stacked structure, and the memory string structure are located on a first side of the first insulating layer, the first contact structure passes through a second portion of the first insulating layer from the first side, and the first pad structure is located on a second side opposite to the first side and connected to the first contact structure.

9. The three-dimensional memory of claim 8, wherein the first semiconductor structure further comprises:

a second insulating layer on a second portion of the first insulating layer, wherein the first contact structure passes through the second insulating layer and the second portion of the first insulating layer.

10. The three-dimensional memory according to claim 8, wherein the memory string structure comprises a functional layer and a channel layer from outside to inside in a radial direction thereof, the channel layer extends into the semiconductor layer, and a portion of the channel layer adjacent to the semiconductor layer has a doped region.

11. The three-dimensional memory of claim 8, wherein the first semiconductor structure further comprises:

a second contact structure penetrating the first portion of the first insulating layer and connected to the semiconductor layer; and

and the second pad structure is positioned on the second side and is connected with the second contact structure.

12. The three-dimensional memory according to claim 8, further comprising a peripheral circuit semiconductor structure bonded to the first semiconductor structure.

13. The three-dimensional memory of claim 12, wherein the first semiconductor structure further comprises an interconnect layer on the first side, wherein the peripheral circuit semiconductor structure and the first semiconductor structure are electrically coupled with the memory string structure and/or the first contact structure through the interconnect layer.

14. The three-dimensional memory according to any one of claims 8 to 13, wherein the semiconductor layer is an N-doped polysilicon layer.

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