CN113904679A

CN113904679A - transceiver circuit

Info

Publication number: CN113904679A
Application number: CN202010562878.XA
Authority: CN
Inventors: 陈家源; 石益璋; 杨育哲
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2020-06-19
Filing date: 2020-06-19
Publication date: 2022-01-07

Abstract

The invention discloses a transceiver circuit, which comprises a transceiving antenna, a transmitter circuit, a receiver circuit, a frequency synthesizer and a base frequency circuit. The transmitter circuit is used for transmitting radio frequency signals corresponding to radio frequency through the transceiving antenna. The frequency synthesizer is used for providing a first local oscillation signal and a second local oscillation signal which respectively have a first local oscillation frequency and a second local oscillation frequency. The baseband circuitry operates in a transmitter mode and a receiver mode. In the transmitter mode, the frequency synthesizer provides a first local oscillation signal, and in the receiver mode, the frequency synthesizer provides a second local oscillation signal, and the first local oscillation frequency is a non-integer multiple of the rf frequency, and the second local oscillation frequency is an integer multiple of the rf frequency.

Description

Transceiver circuit

Technical Field

The present invention relates to a transceiver circuit, and more particularly, to a transceiver circuit that can be optimized for a transmitter and a receiver, respectively.

Background

Bluetooth technology has been widely used in recent years in various electronic devices, so that different electronic devices can perform low-power data transmission over a short distance.

In the prior art, the output signals of multiple wireless transmission technologies are often modulated only by an oscillation signal with a single frequency. When the frequency of the oscillation signal is designed to be an integer multiple of the radio frequency, the frequency is often affected by a transmitter pulling (TX pulling) effect when the transmitter transmits a signal, which causes problems such as phase error or frequency offset, and results in poor performance of the transmitter.

In order to avoid the problem of transmitter pulling, the frequency of the oscillation signal is designed to be a non-integer multiple of the rf frequency, however, when the non-integer multiple of the frequency is provided to the receiver as the local oscillation signal, the receiver has a disadvantage of high power consumption.

Therefore, it is an important subject of the art to provide a transceiver circuit that can be optimized for a transmitter and a receiver, respectively.

Disclosure of Invention

The present invention is directed to a transceiver circuit that can be optimized for a transmitter and a receiver respectively.

In order to solve the above technical problem, one of the technical solutions of the present invention is to provide a transceiver circuit, which includes a transceiving antenna, a transmitter circuit, a receiver circuit, a frequency synthesizer, and a baseband circuit. And the transmitter circuit is connected with the transceiving antenna and used for transmitting the radio frequency signal through the transceiving antenna. Wherein the radio frequency signal corresponds to a radio frequency. The receiver circuit is connected to the transceiving antenna and used for receiving the external signal with the radio frequency through the transceiving antenna. A frequency synthesizer is connected to the transmitter circuit and the receiver circuit, includes an oscillator, and is configured to provide a first local oscillation signal and a second local oscillation signal. The first local oscillation signal has a first local oscillation frequency, and the second local oscillation signal has a second local oscillation frequency. A baseband circuit is connected to the transmitter circuit, the receiver circuit, and the frequency synthesizer and is configured to operate in a transmitter mode and a receiver mode. Wherein in the transmitter mode, the baseband circuitry is configured to control the frequency synthesizer to provide the first local oscillator signal and to provide an input signal to the transmitter circuitry, the transmitter circuitry processing the input signal according to the first local oscillator signal to transmit the radio frequency signal through the transceiver antenna. Wherein in the receiver mode, the baseband circuitry is configured to control the frequency synthesizer to provide the second local oscillation signal, and the receiver circuitry processes the external signal according to the second local oscillation signal to transmit the processed external signal to the baseband circuitry. The first local oscillation frequency is a non-integral multiple of the radio frequency, and the second local oscillation frequency is an integral multiple of the radio frequency.

One of the advantages of the present invention is that the transceiver circuit provided by the present invention can provide the non-integer frequency-doubled local oscillation signal with the rf frequency in the transmitter mode to avoid the problem of transmitter pulling, and can provide the integer frequency-doubled local oscillation signal with the rf frequency in the receiver mode, so as to optimize the power consumption of the receiver and meet the requirement of low power consumption of the receiver.

For a better understanding of the features and technical content of the present invention, reference should be made to the following detailed description of the invention and accompanying drawings, which are provided for purposes of illustration and description only and are not intended to limit the invention.

Drawings

Fig. 1 is a block diagram of a transceiver circuit according to an embodiment of the invention.

Fig. 2 is a schematic diagram of a transceiver antenna, a transmitter circuit, a receiver circuit and a frequency synthesizer according to an embodiment of the invention.

Fig. 3 is a block diagram of an analog phase locked loop according to an embodiment of the invention.

Fig. 4 is a block diagram of an adpll according to an embodiment of the invention.

Fig. 5A and 5B are circuit layout diagrams of a vco or a dco according to an embodiment of the invention.

Description of the symbols:

in order to make the above and other objects, features, advantages and embodiments of the present invention more comprehensible, the following description is given:

a transceiver circuit: 1

A transmitting-receiving antenna: ant

A transmitter circuit: TX

A receiver circuit: RX

A frequency synthesizer: SYN

The base frequency circuit: BB

A digital power amplifier: DPA

A first frequency divider: div1

A low noise amplifier: LNA

A second frequency divider: div2

A mixer: MX

External signals: so, So'

An oscillator: OSC

First local oscillation signal: SLO1

The second local oscillation signal: SLO2

Inputting a signal: si

A voltage-controlled oscillator: VCO

An analog phase-locked loop: APLL

A phase frequency detector: PFD

A charge pump: CP (CP)

A low-pass filter: LPF

A third frequency eliminator: div3

Reference frequency signal: CLK _ REF

Detecting voltage: vp

Control voltage: vc

A digitally controlled oscillator: DCO

Digitally controlling the oscillation signal: sdco

Full analog phase-locked loop: ADPLL

Phase frequency control logic: PFCL

A digital low-pass filter: DLPF

Digital comparison signal: sdcp

Voltage control signal: vc'

Current source: is

Inductance: l is

Capacitance: c

Negative conductance device: NGm

A first transistor: m1

A second transistor: m2

Band selection capacitance: BSC

Band selection inductance: BSL

Detailed Description

The following is a description of the embodiments of the present disclosure relating to "transceiver circuit" by specific embodiments, and those skilled in the art will understand the advantages and effects of the present disclosure from the disclosure of the present disclosure. The invention is capable of other and different embodiments and its several details are capable of modifications and various changes in detail, all without departing from the spirit and scope of the present invention. The drawings of the present invention are for illustrative purposes only and are not intended to be drawn to scale. The following embodiments will further explain the related art of the present invention in detail, but the disclosure is not intended to limit the scope of the present invention. In addition, the term "or" as used herein should be taken to include any one or combination of more of the associated listed items as the case may be.

Referring to fig. 1, an embodiment of the invention provides a transceiver circuit 1, which includes a transceiver antenna Ant, a transmitter circuit TX, a receiver circuit RX, a frequency synthesizer SYN, and a baseband circuit BB.

The transmitter circuit TX is connected to the transmit-receive antenna Ant, and is configured to transmit a Radio Frequency (RF) signal through the transmit-receive antenna Ant. Wherein the radio frequency signal corresponds to a radio frequency, e.g., 2.4 GHz. Fig. 2 is a schematic diagram of a transceiver antenna, a transmitter circuit, a receiver circuit and a frequency synthesizer according to an embodiment of the invention. The transmitter circuit TX may comprise, among other things, a digital power amplifier DPA and a first frequency divider Div1 connected to the frequency synthesizer SYN.

Referring to fig. 1, the receiver circuit RX is connected to the transmit-receive antenna Ant for receiving the external signal So with the rf frequency through the transmit-receive antenna Ant. As shown in fig. 2, the receiver circuit RX may include a low noise amplifier LNA, a second frequency divider Div2 connected to the frequency synthesizer SYN, and a mixer MX connected to the second frequency divider Div2 and the low noise amplifier LNA.

The frequency synthesizer SYN is connected to the transmitter circuit TX and the receiver circuit RX, includes an oscillator OSC, and is configured to provide a first local oscillation signal SLO1 and a second local oscillation signal SLO 2. Wherein the first local oscillation signal SLO1 has a first local oscillation frequency and the second local oscillation signal SLO2 has a second local oscillation frequency.

Baseband circuitry BB may, for example, be digital baseband circuitry connected to transmitter circuitry TX, receiver circuitry RX, and frequency synthesizer SYN, configured to operate in a transmitter mode and a receiver mode, respectively.

In transmitter mode, fundamental frequency circuit BB is configured to control frequency synthesizer SYN to provide first local oscillation signal SLO1, and to provide input signal Si to transmitter circuit TX. Thus, the transmitter circuit TX may process the input signal Si according to the first local oscillation signal SLO1 to transmit the radio frequency signal through the transceiving antenna Ant. Thus, as shown in fig. 2, the first divider Div1 may be configured to receive the first local oscillation signal SLO1 in the transmitter mode, divide the frequency of the first local oscillation signal SLO1 by a non-integer multiple, and then amplify the signal through the digital power amplifier DPA to transmit the radio frequency signal associated with the transmitter mode according to the input signal Si. The first local oscillation frequency is a non-integer multiple of the rf frequency, for example, in a preferred embodiment, the first local oscillation frequency is, for example, 3.6GHz, and the non-integer multiple is 1.5, but the invention is not limited thereto.

In other words, when the transmitter circuit TX operates in the transmitter mode, the baseband circuit BB may control the frequency synthesizer SYN to provide the local oscillating signal with a non-integer multiple of the radio frequency (e.g., 3.6GHz at a frequency of 1.5 times 2.4 GHz) to avoid transmitter pulling problems.

On the other hand, in the receiver mode, the baseband circuit BB is configured to control the frequency synthesizer SYN to provide the second local oscillation signal SLO2, and the receiver circuit RX may process the external signal So according to the second local oscillation signal SLO2 to transfer the processed external signal So' to the baseband circuit BB.

As shown in fig. 2, the second frequency divider Div2 may receive the second local oscillating signal SLO2 in the receiver mode and divide the frequency of the second local oscillating signal SLO2 by an integer multiple, and the mixer MX may mix the external signal So amplified by the low noise amplifier LNA and the divided frequency of the second local oscillating signal SLO2 to generate a processed external signal So'. The second local oscillation frequency is an integer multiple of the rf frequency, for example, in a preferred embodiment, the second local oscillation frequency may be 4.8GHz, and the integer multiple is 2.

In other words, when the receiver circuit RX operates in the receiver mode, the baseband circuit BB can control the frequency synthesizer SYN to provide the local oscillator signal with integer multiple of the rf frequency (e.g., 4.8GHz with a frequency 2.4 GHz), so that the transceiver circuit of the present invention can provide a solution to the problem of transmitter pulling, and can optimize the power consumption of the receiver to meet the requirement of low power consumption of the receiver.

Details of the frequency synthesizer SYN are described further below. Reference is further made to fig. 3, which is a block diagram illustrating an analog phase locked loop according to an embodiment of the invention. As shown in fig. 3, in some embodiments, the oscillator OSC may be set as a voltage controlled oscillator VCO, and the frequency synthesizer SYN may include an analog phase locked loop APLL.

As shown in fig. 3, the analog phase-locked loop APLL may include a phase frequency detector PFD, a charge pump CP, a low pass filter LPF and a third frequency divider Div 3. The analog phase-locked loop (APLL) is a feedback control system, and the main function of the analog phase-locked loop is to change the oscillation frequency of a Voltage Controlled Oscillator (VCO), so that a feedback signal can track an input reference frequency signal, and finally, the feedback signal can be synchronized with the frequency and phase of the input reference frequency signal, and an output sine wave of a frequency multiple of the reference frequency signal is generated at the output end of the analog phase-locked loop (APLL).

In the embodiment, the PFD is configured to receive a reference frequency signal CLK _ REF, the charge pump CP is connected to the PFD, the low pass filter LPF is connected to the charge pump CP and the VCO, and the third divider Div3 is connected to the VCO and the PFD.

The PFD is configured to detect a phase difference between the reference frequency signal CLK _ REF and an output signal of the third divider Div3, and generate a detection voltage Vp to control the charge pump CP to charge and discharge the low pass filter LPF, so that the low pass filter correspondingly generates a control voltage Vc to adjust the voltage controlled oscillator VCO, thereby generating the first local oscillation signal SLO1 or the second local oscillation signal SLO 2.

Alternatively, the frequency synthesizer SYN may be practiced digitally. Please refer to fig. 4, which is a block diagram of an all-digital phase-locked loop according to an embodiment of the invention. The oscillator OSC may be set to a digitally controlled oscillator DCO configured to generate a digitally controlled oscillation signal Sdco, and the frequency synthesizer SYN may comprise a full analog phase locked loop ADPLL.

As shown in fig. 4, the full analog phase locked loop ADPLL includes a phase frequency control logic PFCL and a digital low pass filter DLPF. Similarly, the PFCL receives the reference clock signal CLK _ REF and the digitally controlled oscillation signal Sdco, is configured to detect a phase difference between the reference clock signal CLK _ REF and the digitally controlled oscillation signal Sdco, and outputs a digital comparison signal Sdcp.

On the other hand, the digital low-pass filter DLPF is connected to the phase frequency control logic PFCL and the digitally controlled oscillator DLPF, and configured to generate the voltage control signal Vc' according to the digital comparison signal Sdcp to adjust the digitally controlled oscillator DCO, thereby generating the first local oscillation signal SLO1 or the second local oscillation signal SLO 2.

In detail, the full analog phase locked loop ADPLL can be used as a frequency generator providing fast adjustment, precision, and high bandwidth, and has the characteristics of fast conversion, high resolution, small area, and low power. For example, the operation procedure of the whole system of the full analog phase-locked loop ADPLL is basically that the phase frequency control logic PFCL compares the rising edge or the falling edge of the digitally controlled oscillation signal Sdco with the rising edge or the falling edge of the reference frequency signal CLK _ REF.

Taking the rising edge as an example, when the rising edge of the digital control oscillation signal Sdco leads the rising edge of the reference clock signal CLK _ REF, a low-level digital comparison signal Sdcp is output, and otherwise, a high-level digital comparison signal Sdcp is output. The digital low-pass filter DLPF generates the corresponding voltage control signal Vc' according to the high-low level of the digital comparison signal Sdcp. The control word of the voltage control signal Vc ' is input to the digitally controlled oscillator DCO, and is used to determine the oscillation frequency of the digitally controlled oscillator DCO, and the digitally controlled oscillator DCO feeds back the digitally controlled oscillation signal Sdco generated by the voltage control signal Vc ' to the phase frequency control logic PFCL, compares the phase frequency control signal Sdco with the reference frequency signal CLK _ REF again, and thus continuously modifies the voltage control signal Vc ', so that the frequency phase difference between the reference frequency signal CLK _ REF and the digitally controlled oscillation signal Sdco output by the digitally controlled oscillator DCO is minimized, and when the locking operation is achieved, the high and low level numbers of the digital comparison signal Sdcp are all zero.

Possible embodiments of the voltage controlled oscillator VCO or the digitally controlled oscillator DCO are further explained below. Fig. 5A and 5B are circuit layout diagrams of a voltage controlled oscillator or a digitally controlled oscillator, respectively, according to an embodiment of the invention.

As shown in fig. 5A and 5B, the oscillator OSC (which may be configured as a voltage controlled oscillator VCO or a digitally controlled oscillator DCO) includes a current source Is, an inductor L connected to the current source Is, a capacitor C connected in parallel with the inductor L, and a negative conductance NGm connected in parallel with the inductor L and the capacitor C.

FIGS. 5A and 5B show LC controlled oscillators that use negative resistance to compensate for the loss of resonator parasitic resistance. The frequency of the lc-controlled oscillator can be controlled by changing the capacitance C or the inductance L, and in the configuration provided in fig. 5A and 5B, a cross-coupled pair (cross-coupled pair) transistor formed by the first transistor M1 and the second transistor M2 can be used to generate a negative resistance, so that oscillation can be generated when the input impedance is less than or equal to the loss of the resonant cavity.

In fig. 5A, the capacitor C is a variable capacitor and can be used as the band selection capacitor BSC, in fig. 5B, the inductor L is a variable inductor and can be used as the band selection inductor BSL, and the frequency of the lc controlled oscillator can be controlled by adjusting the size of the variable capacitor or the variable inductor, thereby generating the first local oscillation signal SLO1 and the second local oscillation signal SLO2 having non-integer frequency multiplication and integer frequency multiplication of the rf frequency, respectively. In other words, at least one of the inductor L and the capacitor C is variable and can be controlled by the baseband circuit BB or other control circuits, but the invention is not limited thereto.

The disclosure is only a preferred embodiment of the invention and is not intended to limit the scope of the claims, so that all equivalent technical changes made by using the contents of the specification and the drawings are included in the scope of the claims.

Claims

1. A transceiver circuit, the transceiver circuit comprising:

a transmit-receive antenna;

a transmitter circuit connected to the transceiver antenna for transmitting a radio frequency signal through the transceiver antenna, wherein the radio frequency signal corresponds to a radio frequency;

the receiver circuit is connected with the transceiving antenna and used for receiving an external signal with the radio frequency through the transceiving antenna;

a frequency synthesizer connected to the transmitter circuit and the receiver circuit, including an oscillator, and configured to provide a first local oscillation signal and a second local oscillation signal, wherein the first local oscillation signal has a first local oscillation frequency and the second local oscillation signal has a second local oscillation frequency;

a baseband circuit connected to the transmitter circuit, the receiver circuit, and the frequency synthesizer, configured to operate in a transmitter mode and a receiver mode,

wherein in the transmitter mode, the fundamental frequency circuitry is configured to control the frequency synthesizer to provide the first local oscillation signal and to provide an input signal to the transmitter circuitry, the transmitter circuitry processing the input signal in accordance with the first local oscillation signal to transmit the radio frequency signal through the transceiving antenna,

wherein in the receiver mode, the baseband circuitry is configured to control the frequency synthesizer to provide the second local oscillation signal, and the receiver circuitry processes the external signal in accordance with the second local oscillation signal to convey the processed external signal to the baseband circuitry,

wherein the first local oscillation frequency is a non-integer multiple of the radio frequency, and the second local oscillation frequency is an integer multiple of the radio frequency.

2. The transceiver circuit of claim 1, wherein the transmitter circuit comprises a first frequency divider connected to the frequency synthesizer and configured to receive the first local oscillator signal in the transmitter mode and divide the first local oscillator signal by a non-integer multiple.

3. The transceiver circuit of claim 2, wherein the first local oscillation frequency is 3.6GHz and the non-integer multiple is 1.5.

4. The transceiver circuit of claim 1, wherein the receiver circuit comprises a second frequency divider, connected to the frequency synthesizer, configured to receive the second local oscillation signal in the receiver mode and divide the second local oscillation signal by an integer multiple.

5. The transceiver circuit of claim 4, wherein the second local oscillation frequency is 4.8GHz and the integer multiple is 2.

6. The transceiver circuit of claim 4, the receiver circuit further comprising a mixer configured to mix the external signal and the second divided local oscillator signal to generate the processed external signal.

7. The transceiver circuit of claim 1, wherein the oscillator is a voltage controlled oscillator configured to generate a voltage controlled oscillating signal, and the frequency synthesizer comprises an analog phase locked loop comprising:

a phase frequency detector receiving a reference frequency signal;

a charge pump connected to the phase frequency detector;

a low pass filter connected to the charge pump and the voltage controlled oscillator; and

a third frequency divider connected to the voltage controlled oscillator and the phase frequency detector,

the phase frequency detector is configured to detect a phase difference between the reference frequency signal and an output signal of the third frequency divider, and generate a detection voltage to control the charge pump to charge and discharge the low-pass filter, so that the low-pass filter correspondingly generates a control voltage to adjust the voltage-controlled oscillator, thereby generating the first local oscillation signal or the second local oscillation signal.

8. The transceiver circuit of claim 1, wherein the oscillator is a digitally controlled oscillator configured to generate a digitally controlled oscillating signal, and the frequency synthesizer comprises an all-analog phase locked loop comprising:

phase frequency control logic receiving a reference frequency signal and the digitally controlled oscillation signal, configured to detect a phase difference of the reference frequency signal and the digitally controlled oscillation signal, and to output a digital comparison signal in response;

a digital low pass filter connected to the phase frequency control logic and the digitally controlled oscillator and configured to generate a voltage control signal to adjust the digitally controlled oscillator according to the digital comparison signal, thereby generating the first local oscillation signal or the second local oscillation signal.

9. The transceiver circuit of claim 7 or 8, wherein the oscillator comprises:

a current source;

the inductor is connected to the current source;

a capacitor connected in parallel with the inductor; and

a negative conductance device connected in parallel with the inductor and the capacitor,

wherein at least one of the inductance and the capacitance is variable controlled by the fundamental frequency circuit.

10. The transceiver circuit of claim 9, wherein the negative conductance device is a cross-coupled pair of transistors.