CN113921068B - Register protection circuit - Google Patents
Register protection circuit Download PDFInfo
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- CN113921068B CN113921068B CN202111141805.4A CN202111141805A CN113921068B CN 113921068 B CN113921068 B CN 113921068B CN 202111141805 A CN202111141805 A CN 202111141805A CN 113921068 B CN113921068 B CN 113921068B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The embodiment of the application discloses a register protection circuit, which comprises: a signal transmission logic circuit, an error correction circuit and a reset circuit; the signal transmission logic circuit is multiple; the plurality of signal transmission logic circuits are arranged to transmit a first value of the first node; the error correction circuit is configured to correct the output value of the signal transmission logic circuit with error according to the output value of the signal transmission logic circuit without error when the value transmitted by any signal transmission logic circuit in the plurality of signal transmission logic circuits has error, so that the received value of the second node is the first value; the reset circuit is configured to perform logic calculation to obtain a reset signal when errors occur in the numerical values transmitted by the plurality of signal transmission logic circuits, and reset the device which is expected to be reset through the reset signal. By the scheme of the embodiment, the protection circuit of the register has a fault tolerance mechanism, and is low in cost and simple in structure.
Description
Technical Field
Embodiments of the present disclosure relate to data storage technologies, and in particular, to a register protection circuit.
Background
The chip (especially the chip related to safety) contains some key registers, and the set values of the registers generally control the setting of important information access enabling (such as access authority setting, encryption logic enabling, key access enabling and the like) or other functions inside the chip; the change of the set value of the register directly affects the validity of the chip security logic or part of the functions. Once tampered, this will lead to functional failure and even leakage of critical information inside the chip. And is therefore very important for the protection of critical registers.
At present, three-mode redundancy and election circuit protection strategies are adopted to protect key registers, but the strategies have larger logic overhead and are relatively complex in design, and a protection circuit is provided herein
Disclosure of Invention
The embodiment of the application provides a register protection circuit which has stronger fault tolerance capability and flexible reset mechanism; and the structure is simple, and the resource cost is small.
The embodiment of the application provides a register protection circuit, which can include: a signal transmission logic circuit, an error correction circuit and a reset circuit; the signal transmission logic circuit is multiple;
the signal transmission logic circuits are arranged to transmit a first numerical value of the first node;
the error correction circuit is configured to correct the output value of the signal transmission logic circuit with error according to the output value of the signal transmission logic circuit without error when the value transmitted by any one of the signal transmission logic circuits with error occurs, so that the received value of the second node is the first value;
and the reset circuit is arranged for carrying out logic calculation according to the output values of the signal transmission logic circuits with errors when the values transmitted by the signal transmission logic circuits are all in errors, obtaining a reset signal and resetting the device which is expected to be reset through the reset signal.
In an exemplary embodiment of the present application, a plurality of input terminals of the signal transmission logic circuits are connected to the first node;
the input end of the error correction circuit is connected with the output ends of the signal transmission logic circuits, and the first output end of the error correction circuit is connected with the second node;
the first input end of the reset circuit is connected with the second output end of the error correction circuit, the second input end of the reset circuit is connected with the first node, and the output end of the reset circuit is connected with the reset end of the device which is expected to reset.
In an exemplary embodiment of the present application, the first value is a first logic value or a second logic value;
the plurality of signal transmission logic circuits includes: a first signal transmission logic circuit and a second signal transmission logic circuit;
the first signal transmission logic circuit and the second signal transmission logic circuit each include a D flip-flop.
In an exemplary embodiment of the present application, the D flip-flop included in the first signal transmission logic circuit and the D flip-flop included in the second signal transmission logic circuit store opposite logic values.
In an exemplary embodiment of the present application, when the first value is a first logical value:
the first signal transmission logic circuit includes: a first D flip-flop and a first not gate;
the input end of the first D trigger is used as the input end of the first signal transmission logic circuit and is connected with the first node;
the output end of the first D trigger is connected with the input end of the first NOT gate;
the output end of the first NOT gate is used as the output end of the first signal transmission logic circuit and is connected with the input end of the error correction circuit;
the second signal transmission logic circuit includes: a second D flip-flop and a second not gate;
the input end of the second NOT gate is used as the input end of the second signal transmission logic circuit and is connected with the first node;
the output end of the second NOT gate is connected with the input end of the second D trigger;
the output end of the second D trigger is used as the output end of the second signal transmission logic circuit and is connected with the input end of the error correction circuit.
In an exemplary embodiment of the present application, the error correction circuit includes: a first and gate and a third not gate;
the input end of the first AND gate is used as the input end of the error correction circuit and is connected with the output ends of the first signal transmission logic circuit and the second signal transmission logic circuit;
the output end of the first AND gate is connected with the input end of the third NOT gate;
the output end of the third NOT gate is used as a first output end of the error correction circuit and is connected with the second node.
In an exemplary embodiment of the present application, the reset circuit includes: a first NAND gate;
the first input end of the first NAND gate is used as the first input end of the reset circuit and is connected with the output end of the first AND gate, and the output end of the first AND gate is used as the second output end of the error correction circuit;
the second input end of the first NAND gate is used as the second input end of the reset circuit and is connected with the first node;
the output end of the first NAND gate is used as the output end of the reset circuit and is connected with the reset end of the device which is expected to reset.
In an exemplary embodiment of the present application, when the first value is a second logical value:
the first signal transmission logic circuit includes: a third D flip-flop and a fourth not gate;
the input end of the third D trigger is used as the input end of the first signal transmission logic circuit and is connected with the first node;
the output end of the third D trigger is connected with the input end of the fourth NOT gate;
the output end of the fourth NOT gate is used as the output end of the first signal transmission logic circuit and is connected with the input end of the error correction circuit; the second signal transmission logic circuit includes: a fifth NOT gate and a fourth D flip-flop;
the input end of the fifth NOT gate is used as the input end of the second signal transmission logic circuit and is connected with the first node;
the output end of the fifth NOT gate is connected with the input end of the fourth D trigger;
the output end of the fourth D trigger is used as the output end of the second signal transmission logic circuit and is connected with the input end of the error correction circuit.
In an exemplary embodiment of the present application, the error correction circuit includes: a first or gate and a sixth not gate;
the input end of the first OR gate is used as the input end of the error correction circuit and is connected with the output ends of the first signal transmission logic circuit and the second signal transmission logic circuit;
the output end of the first OR gate is connected with the input end of the sixth NOT gate;
the output end of the sixth NOT gate is used as a first output end of the error correction circuit and is connected with the second node.
In an exemplary embodiment of the present application, the reset circuit includes: a first exclusive-or gate;
the first input end of the first exclusive-OR gate is used as the first input end of the reset circuit and is connected with the output end of the first OR gate, and the output end of the first OR gate is used as the second output end of the error correction circuit;
the second input end of the first exclusive-OR gate is used as the second input end of the reset circuit and is connected with the first node;
the output end of the first exclusive-OR gate is used as the output end of the reset circuit and is connected with the reset end of the device which expects to reset.
In an exemplary embodiment of the present application, a plurality of the signal transmission logic circuits are discretely distributed in traces inside a printed circuit board PCB or a chip.
Compared with the related art, the embodiment of the application comprises the following steps: a signal transmission logic circuit, an error correction circuit and a reset circuit; the signal transmission logic circuit is multiple; the signal transmission logic circuits are arranged to transmit a first numerical value of the first node; the error correction circuit is configured to correct the output value of the signal transmission logic circuit with error according to the output value of the signal transmission logic circuit without error when the value transmitted by any one of the signal transmission logic circuits with error occurs, so that the received value of the second node is the first value; and the reset circuit is arranged for carrying out logic calculation according to the output values of the signal transmission logic circuits with errors when the values transmitted by the signal transmission logic circuits are all in errors, obtaining a reset signal and resetting the device which is expected to be reset through the reset signal. By the scheme of the embodiment, the protection circuit of the register has a fault tolerance mechanism, and is low in cost and simple in structure.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a schematic diagram of a register protection circuit according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a register protection circuit according to an embodiment of the present application when the register protection circuit is heteroduplex;
FIG. 3 is a schematic diagram of a register protection circuit with a security state logic value of 1 according to an embodiment of the present application;
fig. 4 is a schematic diagram of a register protection circuit with a logic value of 0 in a secure state according to an embodiment of the present application.
Detailed Description
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
An embodiment of the present application provides a register protection circuit, as shown in fig. 1, may include: a signal transmission logic circuit 1, an error correction circuit 2 and a reset circuit 3; the signal transmission logic circuit 1 is a plurality of signal transmission logic circuits;
a plurality of signal transmission logic circuits 1, configured to transmit a first value of a first node a;
the error correction circuit 2 is configured to correct, when the value transmitted by any one of the signal transmission logic circuits is wrong, the output value of the signal transmission logic circuit with the error according to the output value of the signal transmission logic circuit without the error, so that the received value of the second node B is the first value;
the reset circuit 3 is configured to perform logic calculation according to the output value of the signal transmission logic circuit with error to obtain a reset signal when the values transmitted by the signal transmission logic circuits are all error, and reset the device which is expected to reset by the reset signal.
In an exemplary embodiment of the present application, a plurality of the signal transmission logic circuits are discretely distributed in traces inside a printed circuit board PCB or a chip.
In an exemplary embodiment of the present application, a protection method for a critical register is provided, which aims to protect a register storage node on a critical path from functional failure or leakage of security information caused by a single event effect or by a laser (laser) attack.
In an exemplary embodiment of the present application, a heterogeneous multi-chain (e.g., double-chain) redundant circuit structure (e.g., multiple signal transmission logic circuits 1 are provided) is structurally employed, and multiple links are required to be discrete wires on a layout (e.g., a layout of a Printed Circuit Board (PCB)).
In an exemplary embodiment of the present application, as shown in fig. 2, a plurality of the signal transmission logic circuits 1 may include: a first signal transmission logic circuit 1-1 and a second signal transmission logic circuit 1-2;
the first signal transmission logic circuit 1-1 and the second signal transmission logic circuit 1-2 each comprise a D flip-flop.
In the exemplary embodiment of the present application, the purpose of the protection circuit of the register is to avoid that the value (logic value) of the upper register of the critical path is tampered with into an unsafe state during normal operation of the system (from the unsafe state to the safe state, the leakage of critical data is not caused, and the protection is considered as a safe behavior, and thus no extra protection is required), so in the embodiment of the present application, if one link (such as the D flip-flop in the link) in the multi-link (such as the first signal transmission logic circuit 1-1 and the second signal transmission logic circuit 1-2) is impacted by high-energy particles or a Laser attack, the value of the storage node is rewritten into the unsafe state, and the finally output value is still the value of the original safe state through the heterogeneous multi-link redundancy circuit in combination with the error correction circuit. If the value of a plurality of links (such as D flip-flops in the links) which are all interfered by the outside is rewritten into an unsafe state; the value on the final critical path is tampered with to be in an unsafe state; but at this time, the reset circuit is activated to reset the critical path or the safety data in the system, thereby achieving the protection purpose of the critical register.
In an exemplary embodiment of the present application, a user may flexibly define a scope of a reset signal according to requirements of system security and a use scenario, and the device that desires to reset may include, but is not limited to: the signal transmission logic circuits, the areas for storing the safety information, the whole system and the like.
In the exemplary embodiment of the present application, as shown in fig. 1 and fig. 2, a plurality of input terminals of the signal transmission logic circuits 1 are connected to the first node a;
the input end of the error correction circuit 2 is connected with the output ends of a plurality of signal transmission logic circuits 1, and the first output end of the error correction circuit 2 is connected with a second node B;
a first input terminal of the reset circuit 3 is connected to a second output terminal of the error correction circuit 2, a second input terminal of the reset circuit 3 is connected to the first node a, and an output terminal of the reset circuit 3 is connected to a reset terminal (reset) of a device that is desired to be reset, which may include, but is not limited to: the plurality of signal transmission logic circuits 1, specifically, may be D flip-flops (for example, a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a fourth D flip-flop D4, etc.) in the plurality of signal transmission logic circuits 1.
In an exemplary embodiment of the present application, the first value is a first logic value or a second logic value.
In an exemplary embodiment of the present application, the logic value of the safe (controllable) state on the critical path is typically either logic 0 or 1 depending on the system definition, and thus the first logic value may be 1 and the second logic value may be 0, and the following descriptions are identified with 1 and 0.
In an exemplary embodiment of the present application, the D flip-flop included in the first signal transmission logic circuit 1-1 and the D flip-flop included in the second signal transmission logic circuit 1-2 store opposite logic values.
In the exemplary embodiment of the present application, for example, if the logic value stored in the D flip-flop included in the first signal transmission logic circuit 1-1 is 1, the logic value stored in the D flip-flop included in the second signal transmission logic circuit 1-2 is 0, whereas if the logic value stored in the D flip-flop included in the first signal transmission logic circuit 1-1 is 0, the logic value stored in the D flip-flop included in the second signal transmission logic circuit 1-2 is 1.
In the exemplary embodiment of the present application, DFF (D flip-flop) stores opposite logic values in heterogeneous multi-link structure, reducing the probability of being altered when disturbed, and having higher robustness.
In an exemplary embodiment of the present application, as shown in fig. 3, when the first value is a first logic value (e.g., 1):
the first signal transmission logic circuit 1-1 may include: a first D flip-flop D1 and a first not gate F1;
the input end of the first D trigger D1 is used as the input end of the first signal transmission logic circuit 1-1 and is connected with the first node A;
the output end of the first D trigger D1 is connected with the input end of the first NOT gate F1;
the output end of the first NOT gate F1 is used as the output end of the first signal transmission logic circuit 1-1 and is connected with the input end of the error correction circuit 2;
the second signal transmission logic circuit 1-2 may include: a second D flip-flop D2 and a second not gate F2;
the input end of the second NOT gate F2 is used as the input end of the second signal transmission logic circuit 1-2 and is connected with the first node A;
the output end of the second NOT gate F2 is connected with the input end of the second D trigger D2;
the output end of the second D flip-flop D2 is used as the output end of the second signal transmission logic circuit 1-2, and is connected to the input end of the error correction circuit 2.
In an exemplary embodiment of the present application, the error correction circuit 2 may include: a first and gate Y1 and a third not gate F3;
the input end of the first AND gate Y1 is used as the input end of the error correction circuit 2 and is connected with the output ends of the first signal transmission logic circuit 1-1 and the second signal transmission logic circuit 1-2;
the output end of the first AND gate Y1 is connected with the input end of the third NOT gate F3;
the output end of the third NOT gate F3 is used as a first output end of the error correction circuit 2 and is connected with the second node B.
In an exemplary embodiment of the present application, the reset circuit 3 includes: a first nand gate YF1;
the first input end of the first nand gate YF1 is used as the first input end of the reset circuit 3 and is connected with the output end of the first and gate Y1, and the output end of the first and gate Y1 is used as the second output end of the error correction circuit 2;
a second input end of the first nand gate YF1 is used as a second input end of the reset circuit 3 and is connected with the first node a;
the output end of the first NAND gate YF1 is used as the output end of the reset circuit 3 and is connected with the reset end of the device which is expected to be reset; for example, the reset terminals of the first D flip-flop D1 and the second D flip-flop D2 are connected; the reset ends of the first D trigger D1 and the second D trigger D2 are respectively used as the reset ends of the first signal transmission logic circuit 1-1 and the second signal transmission logic circuit 1-2.
In an exemplary embodiment of the present application, it may be defined that the logical value stored by the registers on the critical path during normal operation of the system is a logical value 1 in the secure state.
In an exemplary embodiment of the present application, if the critical path is a path between the first node a to the second node B: a-B, wherein the first value (may be the logic value a) transmitted by the initial node a may be simultaneously calculated by logic on a plurality of (e.g., two) links (e.g., the first signal transmission logic circuit 1-1 and the second signal transmission logic circuit 1-2), so as to obtain the final effective value B at the second node B; the logical value b=logical value a in the normal case. If the position of the first D trigger D1 of the uplink (such as the first signal transmission logic circuit 1-1) at a certain moment is affected by a particle effect or a Laser (Laser) attack, the logic value stored in the first D trigger D1 is changed to be the logic value 0 in an unsafe state, and the downlink (such as the second signal transmission logic circuit 1-2) is the correct value, the subsequent error correction circuit 2 calculates the logic value; the final output logic value is still the logic value 1 in the secure state. If the logic value stored by the first D flip-flop D1 of the upper chain (e.g., the first signal transmission logic circuit 1-1) and the logic value stored by the second D flip-flop D2 of the lower chain (e.g., the second signal transmission logic circuit 1-2) are both tampered with to be the logic value 0 of the unsafe state, the finally output logic value is changed to be the logic value 0 of the unsafe state; but at the same time will trigger the reset circuit 3 to take effect (0 identifies the reset state).
In the exemplary embodiment of the present application, the single-chain error correction function described above makes the logic value stored in the D memory of the single link not affected by the logic value of the final output security state when being changed; has stronger fault tolerance capability.
In the exemplary embodiment of the present application, a reset mechanism is added through the reset circuit 3, and after the logic value in the secure state is tampered into the logic value in the non-secure state, a reset signal is generated immediately, so that the D flip-flop in the protection circuit is ensured to be reset in time, and the stored logic value in the secure state is restored.
In an exemplary embodiment of the present application, as shown in fig. 4, when the first value is a second logic value (e.g., 0):
the first signal transmission logic circuit 1-1 may include: a third D flip-flop D3 and a fourth not gate F4;
the input end of the third D trigger D3 is used as the input end of the first signal transmission logic circuit 1-1 and is connected with the first node A;
the output end of the third D trigger D3 is connected with the input end of the fourth NOT gate F4;
the output end of the fourth NOT gate F4 is used as the output end of the first signal transmission logic circuit 1-1 and is connected with the input end of the error correction circuit 2;
the second signal transmission logic circuit 1-2 may include: a fifth NOT gate F5 and a fourth D flip-flop D4;
the input end of the fifth NOT gate F5 is used as the input end of the second signal transmission logic circuit 1-2 and is connected with the first node A;
the output end of the fifth NOT gate F5 is connected with the input end of the fourth D trigger D4;
the output end of the fourth D flip-flop D4 is used as the output end of the second signal transmission logic circuit 1-2, and is connected to the input end of the error correction circuit 2.
In an exemplary embodiment of the present application, the error correction circuit 2 includes: a first or gate H1 and a sixth not gate F6;
the input end of the first OR gate H1 is used as the input end of the error correction circuit 2 and is connected with the output ends of the first signal transmission logic circuit 1-1 and the second signal transmission logic circuit 1-2;
the output end of the first OR gate H1 is connected with the input end of the sixth NOT gate F6;
the output terminal of the sixth not gate F6 is connected to the second node B as the first output terminal of the error correction circuit 2.
In an exemplary embodiment of the present application, the reset circuit 3 may include: a first exclusive or gate Z1;
a first input end of the first exclusive-or gate Z1 is used as a first input end of the reset circuit 3 and is connected with an output end of the first or gate H1, and an output end of the first or gate H1 is used as a second output end of the error correction circuit 2;
a second input end of the first exclusive-or gate Z1 is used as a second input end of the reset circuit 3 and is connected with the first node a;
the output end of the first exclusive-OR gate Z1 is used as the output end of the reset circuit 2 and is connected with the reset end of the device which is expected to be reset; for example, the reset terminals of the third D flip-flop D3 and the fourth D flip-flop D4 are connected; the reset ends of the third D flip-flop D3 and the fourth D flip-flop D4 are respectively used as the reset ends of the first signal transmission logic circuit 1-1 and the second signal transmission logic circuit 1-2.
In an exemplary embodiment of the present application, the security state of the logical value stored by the register on the critical path of the system during normal operation may be defined as a logical value of 0.
In an exemplary embodiment of the present application, if the critical path is a path between the first node a to the second node B: a-B, wherein the first value (may be the logic value a) transmitted by the initial node a may be simultaneously calculated by logic on a plurality of (e.g., two) links (e.g., the first signal transmission logic circuit 1-1 and the second signal transmission logic circuit 1-2), so as to obtain the final effective value B at the second node B; the logical value b=logical value a in the normal case. If the position of the first D flip-flop D1 of the uplink (e.g. the first signal transmission logic circuit 1-1) at a certain moment is affected by a particle effect or a Laser (Laser) attack, the logic value stored in the third D flip-flop D3 is changed to the logic value 1 of the unsafe state, and the downlink (e.g. the second signal transmission logic circuit 1-2) is the correct value, the subsequent error correction circuit 2 calculates the logic value; the final output logic value is still the logic value 0 in the secure state. If the logic value stored by the third D flip-flop D3 of the upper chain (e.g., the first signaling logic circuit 1-1) and the logic value stored by the fourth D flip-flop D4 of the lower chain (e.g., the second signaling logic circuit 1-2) are both tampered with to be the logic value 1 of the unsafe state, the finally output logic value is changed to be the logic value 1 of the unsafe state; but at the same time will trigger the reset circuit 3 to take effect (0 identifies the reset state).
In exemplary embodiments of the present application, at least the following advantages are included:
1. the logic overhead of the protection circuit is small;
2. the D trigger in the heterogeneous multi-link structure stores opposite logic values, so that the probability of being changed by interference is reduced, and the robustness is high;
3. the chain error correction function ensures that the logic value stored in the D memory of the single link is not influenced by the logic value of the final output security state when being changed; the fault tolerance is strong;
4. the reset mechanism is added, and after the logic value in the safe state is tampered into the logic value in the unsafe state, a reset signal is generated immediately, so that the D trigger in the protection circuit is reset in time, and the stored logic value in the safe state is restored.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (7)
1. A register protection circuit, comprising: a signal transmission logic circuit, an error correction circuit and a reset circuit; the signal transmission logic circuit is multiple;
the signal transmission logic circuits are arranged to transmit a first numerical value of the first node;
the error correction circuit is configured to correct the output value of the signal transmission logic circuit with error according to the output value of the signal transmission logic circuit without error when the value transmitted by any one of the signal transmission logic circuits with error occurs, so that the received value of the second node is the first value;
the reset circuit is arranged to obtain a reset signal by performing logic calculation according to the output value of the signal transmission logic circuit with errors when the values transmitted by the signal transmission logic circuits are all in errors, and reset the device which is expected to reset through the reset signal;
the input ends of a plurality of signal transmission logic circuits are connected with the first node;
the input end of the error correction circuit is connected with the output ends of the signal transmission logic circuits, and the first output end of the error correction circuit is connected with the second node;
the first input end of the reset circuit is connected with the second output end of the error correction circuit, the second input end of the reset circuit is connected with the first node, and the output end of the reset circuit is connected with the reset end of the device which is expected to be reset;
the first value is a first logic value or a second logic value;
when the first value is the first logic value, the reset circuit includes: a first NAND gate;
a first input end of the first NAND gate is used as a first input end of the reset circuit;
a second input end of the first NAND gate is used as a second input end of the reset circuit;
the output end of the first NAND gate is used as the output end of the reset circuit and is connected with the reset end of the device which is expected to be reset;
when the first value is the second logic value, the reset circuit includes: a first exclusive-or gate;
a first input end of the first exclusive-OR gate is used as a first input end of the reset circuit;
a second input end of the first exclusive-OR gate is used as a second input end of the reset circuit;
the output end of the first exclusive-OR gate is used as the output end of the reset circuit and is connected with the reset end of the device which expects to reset.
2. The register protection circuit of claim 1, wherein a plurality of said signal transmission logic circuits comprises: a first signal transmission logic circuit and a second signal transmission logic circuit;
the first signal transmission logic circuit and the second signal transmission logic circuit both comprise D flip-flops; and the D flip-flop included in the first signal transmission logic circuit and the D flip-flop included in the second signal transmission logic circuit store opposite logic values.
3. The register protection circuit of claim 2, wherein when the first value is the first logical value:
the first signal transmission logic circuit includes: a first D flip-flop and a first not gate;
the input end of the first D trigger is used as the input end of the first signal transmission logic circuit and is connected with the first node;
the output end of the first D trigger is connected with the input end of the first NOT gate;
the output end of the first NOT gate is used as the output end of the first signal transmission logic circuit and is connected with the input end of the error correction circuit;
the second signal transmission logic circuit includes: a second D flip-flop and a second not gate;
the input end of the second NOT gate is used as the input end of the second signal transmission logic circuit and is connected with the first node;
the output end of the second NOT gate is connected with the input end of the second D trigger;
the output end of the second D trigger is used as the output end of the second signal transmission logic circuit and is connected with the input end of the error correction circuit.
4. A register protection circuit according to claim 3, wherein said error correction circuit comprises: a first and gate and a third not gate;
the input end of the first AND gate is used as the input end of the error correction circuit and is connected with the output ends of the first signal transmission logic circuit and the second signal transmission logic circuit;
the output end of the first AND gate is used as the second output end of the error correction circuit
The output end of the first AND gate is connected with the input end of the third NOT gate;
the output end of the third NOT gate is used as a first output end of the error correction circuit and is connected with the second node.
5. The register protection circuit of claim 2, wherein when the first value is the second logical value:
the first signal transmission logic circuit includes: a third D flip-flop and a fourth not gate;
the input end of the third D trigger is used as the input end of the first signal transmission logic circuit and is connected with the first node;
the output end of the third D trigger is connected with the input end of the fourth NOT gate;
the output end of the fourth NOT gate is used as the output end of the first signal transmission logic circuit and is connected with the input end of the error correction circuit;
the second signal transmission logic circuit includes: a fifth NOT gate and a fourth D flip-flop;
the input end of the fifth NOT gate is used as the input end of the second signal transmission logic circuit and is connected with the first node;
the output end of the fifth NOT gate is connected with the input end of the fourth D trigger;
the output end of the fourth D trigger is used as the output end of the second signal transmission logic circuit and is connected with the input end of the error correction circuit.
6. The register protection circuit of claim 5, wherein said error correction circuit comprises: a first or gate and a sixth not gate;
the input end of the first OR gate is used as the input end of the error correction circuit and is connected with the output ends of the first signal transmission logic circuit and the second signal transmission logic circuit;
the output end of the first OR gate is used as a second output end of the error correction circuit;
the output end of the first OR gate is connected with the input end of the sixth NOT gate;
the output end of the sixth NOT gate is used as a first output end of the error correction circuit and is connected with the second node.
7. The register protection circuit of any one of claims 1-6, wherein a plurality of the signal transmission logic circuits are discretely distributed within a printed circuit board PCB or chip.
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| CN202111141805.4A CN113921068B (en) | 2021-09-28 | 2021-09-28 | Register protection circuit |
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| CN119415340B (en) * | 2025-01-07 | 2025-04-11 | 芯来智融半导体科技(上海)有限公司 | Register protection method, system, equipment and product |
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Denomination of invention: A Register Protection Circuit Granted publication date: 20230714 Pledgee: Huaxia Bank Co.,Ltd. Hefei high tech Zone sub branch Pledgor: HEFEI DATANG STORAGE TECHNOLOGY Co.,Ltd. Registration number: Y2024980009254 |
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