CN113935139B - Dynamic network clock synchronous simulation method, system, equipment and medium - Google Patents
Dynamic network clock synchronous simulation method, system, equipment and medium Download PDFInfo
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Abstract
The embodiment of the disclosure provides a dynamic network clock synchronous simulation method, a system, equipment and a medium, which belong to the technical field of wireless sensor networks and specifically comprise the following steps: obtaining topology model parameters, topology structure variation and noise random distribution characteristics of a dynamic network to be tested; generating a topological structure diagram and a noise distribution histogram; acquiring motion parameters and clock parameters of each node according to the topological structure diagram; generating a motion process of each node in a preset period according to the motion parameters, and generating offset of an actual clock and a reference clock of each node according to the clock parameters; substituting the noise distribution histogram, the motion process and the offset into an algorithm updating formula to obtain a simulation result of the dynamic network to be tested. According to the scheme, the topology structure of the dynamic network to be tested is analyzed, the motion and the clock of each node in the topology structure are improved and compensated, a simulation result is obtained, and the clock synchronization efficiency and the clock synchronization accuracy of the dynamic network are improved.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of wireless sensor networks, in particular to a dynamic network clock synchronous simulation method, a system, equipment and a medium.
Background
At present, a wireless sensor network is a network form formed by organizing and combining tens of thousands of sensor nodes through a wireless communication technology, and has wide potential application fields, such as: military, aviation, disaster relief, environmental, medical, home, industrial, etc. The wireless sensor network is used as a distributed network, and can cooperate to complete more corresponding tasks only under the same time reference. Therefore, the clock synchronization problem is a fundamental and primary problem in wireless sensor networks. However, with the development of wireless sensor network technology, unmanned aerial vehicle formation, intelligent vehicle networking, inter-satellite links, and lead series are gradually rising, and the movement of nodes in the network brings new characteristics to the wireless sensor network, and the movement of nodes in the dynamic network brings problems of topology transformation and asymmetric transmission delay. In order to improve the synchronization accuracy of the dynamic network, the problem of motion delay compensation needs to be considered. Therefore, aiming at the clock synchronization of the dynamic network, the software simulation environment is designed to help improve and enhance the effect of clock synchronization in the dynamic network. The existing clock synchronization algorithm has the problem of low synchronization efficiency and synchronization accuracy in the process of processing a dynamic network.
Therefore, a method for simulating clock synchronization of a dynamic network is needed to improve the clock synchronization efficiency and precision of the dynamic network.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a method, a system, an apparatus, and a medium for dynamic network clock synchronization simulation, which at least partially solve the problem in the prior art that the clock synchronization efficiency and the precision of a dynamic network are poor.
In a first aspect, an embodiment of the present disclosure provides a dynamic network clock synchronization simulation method, including:
Obtaining topology model parameters, topology structure variation and noise random distribution characteristics of a dynamic network to be tested;
Generating a topological structure diagram and a noise distribution histogram according to the topological model parameters, the topological structure variation and the noise random distribution characteristics;
Acquiring motion parameters and clock parameters of each node in the dynamic network to be tested according to the topological structure diagram;
Generating a motion process of each node in a preset period according to the motion parameters, and generating an offset of an actual clock and a comparison clock of each node according to the clock parameters;
Substituting the noise distribution histogram, the motion process and the offset into an algorithm updating formula to obtain a simulation result of the dynamic network to be tested.
According to a specific implementation manner of the embodiment of the present disclosure, the step of obtaining the topology model parameter, the topology structure variation and the noise random distribution feature of the dynamic network to be tested includes:
obtaining the topology type of the dynamic network to be tested;
Judging whether the topology type belongs to a preset type or not;
if the topology type belongs to the preset type, calculating the topology model parameter, the topology structure variation and the noise random distribution characteristic according to a network parameter;
And if the topology type does not belong to the preset type, calculating the topology model parameters, the topological structure variation and the noise random distribution characteristics according to a preset adjacency matrix.
According to a specific implementation manner of the embodiment of the present disclosure, the motion parameter includes an initial position and a motion speed of each node, and the step of generating a motion process of each node in a preset period according to the motion parameter includes:
establishing a Cartesian coordinate system;
and calculating a corresponding movement process of each node in the preset period according to the initial position and the movement speed of each node in the Cartesian coordinate system.
According to a specific implementation of an embodiment of the present disclosure, the algorithm update formula includes a relative rate estimation formula, a logic clock rate compensation formula, and a logic clock offset compensation formula.
According to a specific implementation manner of the embodiment of the present disclosure, the step of substituting the noise distribution histogram, the motion process and the offset into an algorithm update formula to obtain a simulation result of the dynamic network to be tested includes:
Substituting the noise distribution histogram, the motion process and the offset into the relative rate estimation formula, the logic clock rate compensation formula and the logic clock deviation compensation formula respectively, and forming the simulation result according to a calculation result.
In a second aspect, an embodiment of the present disclosure provides a dynamic network clock synchronization simulation system, including:
the first acquisition module is used for acquiring topology model parameters, topology structure variation and noise random distribution characteristics of the dynamic network to be detected;
The first generation module is used for generating a topological structure diagram and a noise distribution histogram according to the topological model parameters, the topological structure variation and the noise random distribution characteristics;
The second acquisition module is used for acquiring the motion parameters and the clock parameters of each node in the dynamic network to be tested according to the topological structure diagram;
The second generation module is used for generating a motion process of each node in a preset period according to the motion parameters and generating an offset of an actual clock and a comparison clock of each node according to the clock parameters;
And the simulation module is used for substituting the noise distribution histogram, the motion process and the offset into an algorithm updating formula to obtain a simulation result of the dynamic network to be tested.
In a third aspect, embodiments of the present disclosure further provide an electronic device, including:
at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the dynamic network clock synchronization simulation method of the first aspect or any implementation of the first aspect.
In a fourth aspect, embodiments of the present disclosure also provide a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the dynamic network clock synchronization simulation method of the first aspect or any implementation manner of the first aspect.
In a fifth aspect, embodiments of the present disclosure also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the dynamic network clock synchronization simulation method of the first aspect or any implementation of the first aspect.
The dynamic network clock synchronous simulation scheme in the embodiment of the disclosure comprises the following steps: obtaining topology model parameters, topology structure variation and noise random distribution characteristics of a dynamic network to be tested; generating a topological structure diagram and a noise distribution histogram according to the topological model parameters, the topological structure variation and the noise random distribution characteristics; acquiring motion parameters and clock parameters of each node in the dynamic network to be tested according to the topological structure diagram; generating a motion process of each node in a preset period according to the motion parameters, and generating an offset of an actual clock and a comparison clock of each node according to the clock parameters; substituting the noise distribution histogram, the motion process and the offset into an algorithm updating formula to obtain a simulation result of the dynamic network to be tested.
The beneficial effects of the embodiment of the disclosure are that: according to the scheme, the topology structure of the dynamic network to be tested is analyzed, the motion and the clock of each node in the topology structure are improved and compensated, a simulation result is obtained, and the clock synchronization efficiency and the clock synchronization accuracy of the dynamic network are improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
Fig. 1 is a schematic flow chart of a dynamic network clock synchronous simulation method according to an embodiment of the disclosure;
fig. 2 is a schematic diagram of node information transceiving under a high-speed motion condition according to a dynamic network clock synchronization simulation method provided by an embodiment of the present disclosure;
fig. 3 is a schematic diagram of a partial communication process involved in a dynamic network clock synchronous simulation method according to an embodiment of the present disclosure;
fig. 4 is a schematic structural diagram of a dynamic network clock synchronous simulation system according to an embodiment of the present disclosure;
fig. 5 is a schematic diagram of an electronic device according to an embodiment of the disclosure.
Detailed Description
Embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present disclosure will become readily apparent to those skilled in the art from the following disclosure, which describes embodiments of the present disclosure by way of specific examples. It will be apparent that the described embodiments are merely some, but not all embodiments of the present disclosure. The disclosure may be embodied or practiced in other different specific embodiments, and details within the subject specification may be modified or changed from various points of view and applications without departing from the spirit of the disclosure. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict. All other embodiments, which can be made by one of ordinary skill in the art without inventive effort, based on the embodiments in this disclosure are intended to be within the scope of this disclosure.
It is noted that various aspects of the embodiments are described below within the scope of the following claims. It should be apparent that the aspects described herein may be embodied in a wide variety of forms and that any specific structure and/or function described herein is merely illustrative. Based on the present disclosure, one skilled in the art will appreciate that one aspect described herein may be implemented independently of any other aspect, and that two or more of these aspects may be combined in various ways. For example, an apparatus may be implemented and/or a method practiced using any number of the aspects set forth herein. In addition, such apparatus may be implemented and/or such methods practiced using other structure and/or functionality in addition to one or more of the aspects set forth herein.
It should also be noted that the illustrations provided in the following embodiments merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In addition, in the following description, specific details are provided in order to provide a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects may be practiced without these specific details.
At present, a wireless sensor network is a network form formed by organizing and combining tens of thousands of sensor nodes through a wireless communication technology, and has wide potential application fields, such as: military, aviation, disaster relief, environmental, medical, home, industrial, etc. The wireless sensor network is used as a distributed network, and can cooperate to complete more corresponding tasks only under the same time reference. Therefore, the clock synchronization problem is a fundamental and primary problem in wireless sensor networks. However, with the development of wireless sensor network technology, unmanned aerial vehicle formation, intelligent vehicle networking, inter-satellite links, and lead series are gradually rising, and the movement of nodes in the network brings new characteristics to the wireless sensor network, and the movement of nodes in the dynamic network brings problems of topology transformation and asymmetric transmission delay. In order to improve the synchronization accuracy of the dynamic network, the problem of motion delay compensation needs to be considered. Therefore, aiming at the clock synchronization of the dynamic network, the software simulation environment is designed to help improve and enhance the effect of clock synchronization in the dynamic network. The existing clock synchronization algorithm has the problem of low synchronization efficiency and synchronization accuracy in the process of processing a dynamic network.
The embodiment of the disclosure provides a dynamic network clock synchronous simulation method which can be applied to dynamic network clock synchronous processes of scenes such as military, aviation, disaster relief, environment, medical treatment, home or industry.
Referring to fig. 1, a flow chart of a dynamic network clock synchronous simulation method according to an embodiment of the disclosure is provided. As shown in fig. 1, the method mainly comprises the following steps:
s101, obtaining topology model parameters, topology structure variation and noise random distribution characteristics of a dynamic network to be tested;
In the specific implementation, the network structure of the structural clock synchronization protocol is mainly a tree structure or a cluster structure, one or more reference nodes are arranged, the algorithm protocol is simple and has high convergence speed, but the system maintenance cost is higher when the network topology is dynamically changed, and the robustness and the expandability are relatively insufficient; the distributed clock synchronization protocol has no special nodes such as reference nodes or root nodes, each node only needs to acquire the relative clock information of the adjacent nodes, and has strong robustness and expandability to topology change and node faults. Therefore, the distributed clock synchronization algorithm can solve the problems faced in the dynamic network to a certain extent. However, the node movement in the dynamic network brings about not only topology transformation but also the problem of asymmetric transmission delay. In addition to improving the synchronization accuracy of dynamic networks, the problem of motion delay compensation needs to be considered.
As shown in fig. 2, the nondeterministic delay of information transmission in the wireless sensor network is a main reason for influencing the clock synchronization precision, and the existence of the delay of information transmission leads to inaccurate estimation of the relative clock rate and the relative clock reading, thereby influencing the synchronization effect.
In the case of high-speed movement of the node, the propagation time in the information transmission delay is the most affected compared with the static condition. As shown, A, B are two nodes that are in message transfer, if both nodes are in a quiescent state, the link propagation delay between the two nodes is
Delay＝DAB/c＝T2-T1
Where D AB represents the distance between two nodes at the time of a node message transmission, c represents the signal propagation speed, which is the speed of light when propagating by radio, T 1 represents the time of a node message transmission, and T 2 represents the time of B node message reception in the stationary case.
However, due to the high-speed movement of the node, the node B also moves simultaneously in the process of message propagation, and the propagation delay change Δt caused by the movement of the node is not negligible in order to realize high-precision clock synchronization.
Δt＝DB/vB＝T3-T2
Where D B represents the distance the node B moves during the message transmission, v B represents the speed of the node B movement, and T 3 represents the moment of message reception in the case of high speed movement of the node B. The link propagation Delay between two nodes is delay+Δt in the high-speed motion state.
It can be seen that the magnitude of the propagation delay is related not only to the distance of the AB node, but also to the movement of the node receiving the message, as shown in fig. 3. In the distributed clock synchronization algorithm, the relative rate estimation formula involves a time stamp, and in an ideal case, (T8-T4)/(T5-T1) can obtain the relative rate estimation value between the node a and the node B, but since the transmission delays in the process of T1- > T4 and T5- > T8 are asymmetric, and cannot be offset by simple subtraction, compensation of the motion delay is necessary.
When a clock synchronization design is needed for a certain dynamic network, the dynamic network is used as the dynamic network to be tested, then the corresponding topological model parameter topological structure variation and noise random distribution characteristics are obtained, specifically, the stability of the clock is reflected by considering that the noise can influence the clock frequency of the node, and the Gaussian random distribution needs to be configured with two parameters of a mean value and a standard deviation; the noise random distribution characteristics can be generated by configuring corresponding parameters aiming at the dynamic network to be tested.
S102, generating a topological structure diagram and a noise distribution histogram according to the topological model parameters, the topological structure variation and the noise random distribution characteristics;
In the implementation, after the topology model parameters, the topology structure variation and the noise random distribution characteristics are obtained, a topology structure diagram and a noise distribution histogram corresponding to the dynamic network to be tested can be generated according to the topology model parameters, the topology structure variation and the noise random distribution characteristics.
S103, acquiring motion parameters and clock parameters of each node in the dynamic network to be tested according to the topological structure diagram;
In the implementation, considering that in the practical application process, each node may have a motion process, and in the case of high-speed motion of the node, compared with a static condition, the most affected propagation time is the propagation time in the information transmission time delay, after the topology structure diagram is obtained, the motion parameters and the clock parameters of each node in the dynamic network to be tested can be obtained, so that subsequent steps are facilitated.
S104, generating a motion process of each node in a preset period according to the motion parameters, and generating an offset of an actual clock and a reference clock of each node according to the clock parameters;
In the implementation, after the motion parameters and clock parameters of each node in the dynamic network to be tested are obtained, a motion process of each node in a preset period is generated according to the motion parameters, and the offset of the actual clock and the reference clock of each node can be generated according to the configured clock information and the clock parameters, so that the performance quality of the actual clock is reflected.
S105, substituting the noise distribution histogram, the motion process and the offset into an algorithm updating formula to obtain a simulation result of the dynamic network to be tested.
In specific implementation, a corresponding clock synchronization algorithm can be allocated to the dynamic network to be tested, then a corresponding algorithm updating formula is configured, and then the noise distribution histogram, the motion process and the offset are substituted into the algorithm updating formula to obtain a simulation result of the dynamic network to be tested, and the simulation result is used for compensating the offset generated in the moving process of each node in the dynamic network to be tested.
According to the dynamic network clock synchronous simulation method, the dynamic network to be tested is analyzed, the motion and the clock of each node in the topological structure are improved and compensated, a simulation result is obtained, and the clock synchronous efficiency and the clock precision of the dynamic network are improved.
Based on the above embodiment, step S101, obtaining the topology model parameters, the topology structure variation and the noise random distribution characteristics of the dynamic network to be tested, includes:
obtaining the topology type of the dynamic network to be tested;
Judging whether the topology type belongs to a preset type or not;
if the topology type belongs to the preset type, calculating the topology model parameter, the topology structure variation and the noise random distribution characteristic according to a network parameter;
And if the topology type does not belong to the preset type, calculating the topology model parameters, the topological structure variation and the noise random distribution characteristics according to a preset adjacency matrix.
In specific implementation, the network clock can be synchronized or not according to the topology structure. Several preset topologies may be provided for the network topology, which may include linear topology, ring topology, star topology, tree topology, mesh topology. Wherein, the linear topology, the ring topology and the star topology need to be configured with the number of nodes; the tree topology needs to configure the number of sub-nodes and the layer number; the mesh topology and the random mesh topology need to configure the number of nodes in the length-width direction; in addition, a presence/absence graph may be selected, and then the topology model parameters, the topology change amount, and the noise random distribution feature are calculated according to network parameters. For other topologies, the configuration can be performed by a user inputting legal adjacency matrix, and then calculating the topology model parameters, the topology variation and the noise random distribution characteristics according to a preset adjacency matrix. The dynamic network also involves topology change, and a user can set the topology change condition of the network and change the topology change condition into a specified topology structure at a specified moment. According to the whole network topology structure and its change in the course of the above-mentioned process configuration software system simulation process, and drawing correspondent topology structure diagram
Optionally, the motion parameters include an initial position and a motion speed of each node, and the step of generating, according to the motion parameters, a motion process of each node in a preset period in step S104 includes:
establishing a Cartesian coordinate system;
and calculating a corresponding movement process of each node in the preset period according to the initial position and the movement speed of each node in the Cartesian coordinate system.
In the implementation, considering that the motion condition of each node needs to be described, a Cartesian coordinate system can be established for the motion of the node, and the initial position and the motion speed in the directions of three coordinate axes of x, y and z are configured, or a speed function of the node is provided. And drawing the motion process of the nodes in the network according to the configured motion information.
On the basis of the above embodiment, the algorithm update formula includes a relative rate estimation formula, a logic clock rate compensation formula, and a logic clock offset compensation formula.
Further, in step S105, substituting the noise distribution histogram, the motion process and the offset into an algorithm update formula to obtain a simulation result of the dynamic network to be tested, including:
Substituting the noise distribution histogram, the motion process and the offset into the relative rate estimation formula, the logic clock rate compensation formula and the logic clock deviation compensation formula respectively, and forming the simulation result according to a calculation result.
In specific implementation, an existing distributed clock synchronization algorithm can be improved, a corresponding algorithm update formula is set, specifically, the algorithm update formula can include the relative rate estimation formula, the logic clock rate compensation formula and the logic clock deviation compensation formula, then the noise distribution histogram, the motion process and the offset are respectively substituted into the relative rate estimation formula, the logic clock rate compensation formula and the logic clock deviation compensation formula, and the simulation result is formed according to the calculation result, so that the distributed clock synchronization algorithm is improved according to the simulation result, and the clock synchronization efficiency and the synchronization accuracy of a dynamic network are improved.
In the following, a specific embodiment will be described, where the existing distributed clock synchronization algorithm includes a proportional-integral estimator-based clock synchronization algorithm and an average consistency clock synchronization algorithm, where the proportional-integral estimator-based clock synchronization algorithm needs to configure a sampling period, a cycle number, a harmonic parameter, a proportional gain, an integral gain, and an information rate; the average consistency time synchronization algorithm requires configuration of the sampling period, the number of cycles, and 3 reconciliation parameters. Furthermore, the distributed clock synchronization algorithm is typically divided into three steps: relative rate estimation, logic clock rate compensation, logic clock bias compensation, and then the update formula of the algorithm may be configured.
For example, a proportional-integral estimator based clock synchronization algorithm substituted into the algorithm update formula:
Relative rate estimation:
clock rate compensation:
Virtual clock reading compensation:
Wherein T is the sampling period, ρ is the harmonic parameter, which is essentially the compromise between the new measurement input and the last time estimate, K p is the proportional gain, K is the number of cycles, the number of iterative updates of the clock synchronization algorithm, γ is the information rate, the new information characterizing how much of the ratio is introduced into the feedback, and K i is the integral gain.
Substituting the average consistency clock synchronization algorithm of the algorithm update formula:
Relative rate estimation:
clock rate compensation:
clock bias compensation:
Wherein T is a sampling period, k is the number of cycles, ρ is a harmonic parameter, ρ v is a harmonic parameter, and ρ o is a harmonic parameter.
Corresponding to the above method embodiment, referring to fig. 4, the disclosed embodiment further provides a dynamic network clock synchronization simulation system 40, including:
The first obtaining module 401 is configured to obtain topology model parameters, topology structure variation and noise random distribution characteristics of the dynamic network to be tested;
a first generating module 402, configured to generate a topology structure chart and a noise distribution histogram according to the topology model parameter, the topology structure variation and the noise random distribution feature;
a second obtaining module 403, configured to obtain, according to the topology structure diagram, a motion parameter and a clock parameter of each node in the dynamic network to be tested;
a second generating module 404, configured to generate a motion process of each node in a preset period according to the motion parameter, and generate an offset between an actual clock and a reference clock of each node according to the clock parameter;
and the simulation module 405 is configured to substitute the noise distribution histogram, the motion process and the offset into an algorithm update formula to obtain a simulation result of the dynamic network to be tested.
The system shown in fig. 4 may correspondingly execute the content in the foregoing method embodiment, and the portions not described in detail in this embodiment refer to the content described in the foregoing method embodiment, which is not described herein again.
Referring to fig. 5, an embodiment of the present disclosure also provides an electronic device 50, including: at least one processor and a memory communicatively coupled to the at least one processor. The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the dynamic network clock synchronization simulation method of the foregoing method embodiment.
The disclosed embodiments also provide a non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the dynamic network clock synchronization simulation method in the foregoing method embodiments.
The disclosed embodiments also provide a computer program product comprising a computer program stored on a non-transitory computer readable storage medium, the computer program comprising program instructions which, when executed by a computer, cause the computer to perform the dynamic network clock synchronization simulation method of the foregoing method embodiments.
Referring now to fig. 5, a schematic diagram of an electronic device 50 suitable for use in implementing embodiments of the present disclosure is shown. The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and the like, and stationary terminals such as digital TVs, desktop computers, and the like. The electronic device shown in fig. 5 is merely an example and should not be construed to limit the functionality and scope of use of the disclosed embodiments.
As shown in fig. 5, the electronic device 50 may include a processing means (e.g., a central processing unit, a graphics processor, etc.) 501, which may perform various appropriate actions and processes according to a program stored in a Read Only Memory (ROM) 502 or a program loaded from a storage means 508 into a Random Access Memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the electronic device 50 are also stored. The processing device 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input/output (I/O) interface 505 is also connected to bus 504.
In general, the following devices may be connected to the I/O interface 505: input devices 506 including, for example, a touch screen, touchpad, keyboard, mouse, image sensor, microphone, accelerometer, gyroscope, etc.; an output device 507 including, for example, a Liquid Crystal Display (LCD), a speaker, a vibrator, and the like; storage 508 including, for example, magnetic tape, hard disk, etc.; and communication means 509. The communication means 509 may allow the electronic device 50 to communicate with other devices wirelessly or by wire to exchange data. While an electronic device 50 having various means is shown, it should be understood that not all of the illustrated means are required to be implemented or provided. More or fewer devices may be implemented or provided instead.
In particular, according to embodiments of the present disclosure, the processes described above with reference to flowcharts may be implemented as computer software programs. For example, embodiments of the present disclosure include a computer program product comprising a computer program embodied on a computer readable medium, the computer program comprising program code for performing the method shown in the flowcharts. In such an embodiment, the computer program may be downloaded and installed from a network via the communication means 509, or from the storage means 508, or from the ROM 502. The above-described functions defined in the methods of the embodiments of the present disclosure are performed when the computer program is executed by the processing device 501.
It should be noted that the computer readable medium described in the present disclosure may be a computer readable signal medium or a computer readable storage medium, or any combination of the two. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples of the computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this disclosure, a computer-readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. In the present disclosure, however, the computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, with the computer-readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to: electrical wires, fiber optic cables, RF (radio frequency), and the like, or any suitable combination of the foregoing.
The computer readable medium may be contained in the electronic device; or may exist alone without being incorporated into the electronic device.
The computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to perform the relevant steps of the method embodiments described above.
Or the computer readable medium carries one or more programs which, when executed by the electronic device, cause the electronic device to perform the relevant steps of the method embodiments described above.
Computer program code for carrying out operations of the present disclosure may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
The units involved in the embodiments of the present disclosure may be implemented by means of software, or may be implemented by means of hardware.
It should be understood that portions of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the disclosure are intended to be covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.
Claims (8)
1. The dynamic network clock synchronous simulation method is characterized by comprising the following steps of:
Obtaining topology model parameters, topology structure variation and noise random distribution characteristics of a dynamic network to be tested;
Generating a topological structure diagram and a noise distribution histogram according to the topological model parameters, the topological structure variation and the noise random distribution characteristics;
Acquiring motion parameters and clock parameters of each node in the dynamic network to be tested according to the topological structure diagram;
Generating a motion process of each node in a preset period according to the motion parameters, and generating an offset of an actual clock and a comparison clock of each node according to the clock parameters;
Substituting the noise distribution histogram, the motion process and the offset into an algorithm updating formula to obtain a simulation result of the dynamic network to be tested.
2. The method according to claim 1, wherein the step of obtaining topology model parameters, topology variation and noise random distribution characteristics of the dynamic network to be measured comprises:
obtaining the topology type of the dynamic network to be tested;
Judging whether the topology type belongs to a preset type or not;
if the topology type belongs to the preset type, calculating the topology model parameter, the topology structure variation and the noise random distribution characteristic according to a network parameter;
And if the topology type does not belong to the preset type, calculating the topology model parameters, the topological structure variation and the noise random distribution characteristics according to a preset adjacency matrix.
3. The method according to claim 1, wherein the motion parameters include an initial position and a motion velocity of each of the nodes, and the step of generating a motion profile of each of the nodes within a preset period according to the motion parameters includes:
establishing a Cartesian coordinate system;
and calculating a corresponding movement process of each node in the preset period according to the initial position and the movement speed of each node in the Cartesian coordinate system.
4. The method of claim 1, wherein the algorithm update formula comprises a relative rate estimation formula, a logic clock rate compensation formula, and a logic clock offset compensation formula.
5. The method of claim 4, wherein the step of substituting the noise distribution histogram, the motion process, and the offset into an algorithm update formula to obtain a simulation result of the dynamic network under test comprises:
Substituting the noise distribution histogram, the motion process and the offset into the relative rate estimation formula, the logic clock rate compensation formula and the logic clock deviation compensation formula respectively, and forming the simulation result according to a calculation result.
6. A dynamic network clock synchronous simulation system, comprising:
the first acquisition module is used for acquiring topology model parameters, topology structure variation and noise random distribution characteristics of the dynamic network to be detected;
The first generation module is used for generating a topological structure diagram and a noise distribution histogram according to the topological model parameters, the topological structure variation and the noise random distribution characteristics;
The second acquisition module is used for acquiring the motion parameters and the clock parameters of each node in the dynamic network to be tested according to the topological structure diagram;
The second generation module is used for generating a motion process of each node in a preset period according to the motion parameters and generating an offset of an actual clock and a comparison clock of each node according to the clock parameters;
And the simulation module is used for substituting the noise distribution histogram, the motion process and the offset into an algorithm updating formula to obtain a simulation result of the dynamic network to be tested.
7. An electronic device, the electronic device comprising:
at least one processor; and
A memory communicatively coupled to the at least one processor; wherein,
The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the dynamic network clock synchronization simulation method of any one of the preceding claims 1-5.
8. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the dynamic network clock synchronization simulation method of any one of the preceding claims 1-5.
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