CN113946279B

CN113946279B - Data reading method and device for host performance acceleration mode

Info

Publication number: CN113946279B
Application number: CN202011086743.7A
Authority: CN
Inventors: 施伯宜
Original assignee: Silicon Motion Inc
Current assignee: Silicon Motion Inc
Priority date: 2020-07-16
Filing date: 2020-10-12
Publication date: 2025-01-21
Anticipated expiration: 2040-10-12
Also published as: CN113946278B; TW202205097A; CN113946277B; TWI760884B; TWI761983B; TW202205098A; TW202225979A; CN113946278A; CN113946279A; CN113946277A; TWI873412B; TWI795680B; TW202205099A

Abstract

The present invention relates to a data reading method and device in a host performance acceleration mode, wherein the method is executed by a host end, and comprises: searching a host performance acceleration buffer in a system memory to obtain a logical-physical comparison record associated with a logical block address; issuing a switch command to a flash memory controller, for requesting the flash memory controller to start a host performance acceleration function, but not starting a function to obtain a logical-physical comparison table; issuing a write-multiple-block command to the flash memory controller, for writing a data block to the flash memory controller, the data block including a logical-physical comparison record; and issuing a read-multiple-block command to the flash memory controller, for obtaining data corresponding to the logical-physical comparison record from the flash memory controller. The present invention enables the host end to send a read command with a logical-physical comparison record to the flash memory controller through the setting of a host performance acceleration buffer, for reducing the time and computing resources spent by the flash memory controller on the logical-physical comparison conversion.

Description

Data reading method and device for host efficiency acceleration mode

Technical Field

The present invention relates to a memory device, and more particularly, to a method and apparatus for reading data in a host performance acceleration mode.

Background

Flash memory is generally classified into NOR flash memory and NAND flash memory. The NOR flash memory is a random access device, and a central processing unit (Host) can provide any address accessing the NOR flash memory on an address pin, and timely obtain data stored on the address from a data pin of the NOR flash memory. In contrast, NAND flash memory is not random access, but serial access. NAND flash memory, like NOR flash memory, cannot access any random addresses, but instead the cpu needs to write serial byte values into the NAND flash memory for defining the type of Command (Command) (e.g., read, write, erase, etc.), and the address used on the Command. The address may point to one page (the smallest block of data for a write operation in flash) or one block (the smallest block of data for an erase operation in flash).

In order to improve the data writing and reading performance of the flash memory module, the device side performs data writing and reading in parallel through a plurality of channels. In order to achieve the purpose of parallel processing, a continuous segment of data is stored in a distributed manner in a flash memory unit connected to a plurality of channels, and a Logical-to-physical (L2P Mapping Table) is used to record the correspondence between the Logical address (managed by the host) and the physical address (managed by the flash memory controller) of the user data. However, in a memory device of an embedded multimedia card (e-MMC), as the capacity of the device increases rapidly, the length of the logical-physical lookup table grows multiple times, making the conventional management method performed by the device end burdensome. Even though the use of hierarchical sub-regions to manage the logically-physical mapping table can increase the performance of the logically-physical mapping, it takes much longer than the time (tR) to transfer data from the flash array of the flash memory module to the data registers of the flash memory controller. Therefore, the present invention provides a method and apparatus for data reading in a host performance acceleration mode, which are used for improving the data reading performance of a memory device of an embedded multimedia card.

Disclosure of Invention

In view of this, how to alleviate or eliminate the above-mentioned drawbacks of the related art is a real problem to be solved.

The invention relates to a data reading method of a host efficiency acceleration mode, which is executed by a host end and comprises the steps of searching a host efficiency acceleration buffer area in a system memory to obtain a logic physical comparison record associated with a logic block address, sending a switching command to a flash memory controller, requesting the flash memory controller to start a host efficiency acceleration function but not starting an obtaining function of the logic physical comparison table, sending a writing multi-block command to the flash memory controller, writing a data block to the flash memory controller, wherein the data block comprises the logic physical comparison record, and sending a reading multi-block command to the flash memory controller, and obtaining data corresponding to the logic physical comparison record from the flash memory controller.

The invention also relates to a data reading method of the host efficiency acceleration mode, which is executed by the flash memory controller and comprises the steps of receiving a switching command from a host end, requesting the flash memory controller to start the host efficiency acceleration function but not start the acquisition function of the logic physical comparison table, entering a default state according to the switching command, receiving a writing multi-block command from the host end during entering the default state, acquiring a logic physical comparison record from a data block received by the host end according to the writing multi-block command, and reading data corresponding to the logic physical comparison record from the flash memory device, receiving the reading multi-block command from the host end during entering the default state, and transmitting the data corresponding to the logic physical comparison record to the host end according to the reading multi-block command.

The invention also relates to a device for reading data in the host efficiency acceleration mode, which comprises a host interface, a flash memory interface and a processing unit. The processing unit receives a switching command from the host end through the host interface for requesting the device to start the host efficiency acceleration function but not to start the acquisition function of the logical physical comparison table, enters a default state according to the switching command, receives a write-in multi-block command from the host end through the host interface during the default state, acquires the logical physical comparison record from a data block received by the host end through the host interface according to the write-in multi-block command, and reads data corresponding to the logical physical comparison record from the flash memory device through the flash memory interface, receives a read multi-block command from the host end through the host interface during the default state, and transmits the data corresponding to the logical physical comparison record to the host end through the host interface according to the read multi-block command.

The host side and the flash memory controller communicate with each other using an embedded multimedia card communication protocol, and each logical physical control records information of a physical address where data for storing the logical address is actually stored.

One of the advantages of the above embodiment is that the host side can send the read command with the logical-physical comparison record to the flash memory controller through the setting of the host performance acceleration buffer as described above, so as to reduce the time spent by the flash memory controller and the operation resources for performing the logical-physical comparison conversion.

Other advantages of the present invention will be explained in more detail in connection with the following description and accompanying drawings.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application.

Fig. 1 is a system architecture diagram of an electronic device according to an embodiment of the invention.

FIG. 2 is a schematic diagram of a flash memory device according to an embodiment of the invention.

FIG. 3 is a diagram illustrating the association between a high-level lookup table and a logical-physical lookup table according to an embodiment of the present invention.

FIG. 4 is a diagram illustrating the association between a logical-physical control sub-table and a physical page according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating the establishment and utilization of a host performance acceleration (Host Performance Acceleration, HPA) buffer in accordance with one embodiment of the present invention.

Fig. 6 is a sequence diagram illustrating the operation of HPA buffer initialization according to an embodiment of the present invention.

Fig. 7 and 8 are operation sequence diagrams of HPA reading according to an embodiment of the present invention.

Fig. 9 is a sequence diagram illustrating an operation of an HPA buffer update according to an embodiment of the present invention.

Fig. 10 is a flowchart of a method for executing a handover command according to an embodiment of the invention.

FIG. 11 is a flow chart of a method for executing a write multi-block command according to an embodiment of the invention.

Wherein the symbols in the drawings are briefly described as follows:

10 electronic device, 110 host side, 130 flash memory controller, 131 host interface, 132 bus, 134 processing unit, 135 read-only memory, 136 random access memory, 137 register, 139 flash interface, 150 flash memory device, 151 interface, 153#0-153#15 NAND flash memory unit, CH#0-CH#3 channel, CE#0-CE#3 start signal, 310 high order lookup table, 330#0-330#15L 2P lookup table, 400L 2P lookup record, 410 logical block address information, 430 physical block address information, 430-0 logical unit number and physical block number, 430-1 physical page number, 440 physical block, 450 physical page, 450#2 physical block, 500 HPA buffer, 610-655, 711-755, 835-839, 915, 931, 955 operation, S1010S 1060, S1110-S7 method steps.

Detailed Description

Embodiments of the present invention will be described below with reference to the accompanying drawings. In the drawings, like reference numerals designate identical or similar components or process flows.

It should be understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, values, method steps, operation processes, components, and/or groups, but do not preclude the addition of further features, values, method steps, operation processes, components, groups, or groups of the above.

In the present invention, terms such as "first," "second," "third," and the like are used for modifying elements of the claims, and are not intended to denote a prior order, a first order, or a sequence of steps of a method, for example, for distinguishing between elements having the same name.

It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. Other words used to describe the relationship between components may also be interpreted in a similar fashion, such as "between" versus "directly between," or "adjacent" versus "directly adjacent," etc.

Reference is made to fig. 1. The electronic device 10 includes a host device (also referred to as a host side) 110, a flash controller 130, and a flash device 150, and the flash controller 130 and the flash device 150 may be collectively referred to as a device side (DEVICE SIDE). The electronic device 10 may be implemented in an electronic product such as a personal computer, a notebook computer (Laptop PC), a tablet computer, a mobile phone, a digital camera, a digital video camera, and the like. The Host device 110 and a Host Interface (Host Interface) 131 of the flash Controller 130 may communicate with each other in an embedded multimedia card (e-MMC/eMMC) communication protocol. Flash interface 139 of flash controller 130 and flash device 150 may communicate with each other in a Double Data Rate (DDR) communication protocol, such as an Open NAND flash interface (Open NAND FLASH INTERFACE, ONFI), a Double Data Rate switch (DDR Toggle), or other communication protocol. The flash controller 130 includes a processing unit 134 that may be implemented in a variety of ways, such as using general-purpose hardware (e.g., a micro-control unit, a central processing unit, a multiprocessor having parallel processing capabilities, a graphics processor, or other processor having arithmetic capabilities), and provides the functionality described below when executing software and/or firmware instructions. The processing unit 134 receives eMMC commands through the host interface 131 and executes the commands. The flash controller 130 includes random access memory (Random Access Memory, RAM) 136, which may be implemented as dynamic random access memory (Dynamic Random Access Memory, DRAM), static random access memory (Static Random Access Memory, SRAM), or a combination of both, for configuring space as a data buffer. The RAM 136 may also store data, such as variables, tables of data, etc., that are needed during execution. The flash controller 130 includes a Read Only Memory (ROM) 135 for storing program codes that need to be executed when the device is turned on. Flash interface 139 includes a NAND flash Controller (NAND FLASH Controller, NFC) that provides the functions required when accessing flash device 150, such as command serializer (Command Sequencer), low density parity (Low DENSITY PARITY CHECK, LDPC), and the like.

The flash controller 130 includes a register 137 for storing a wide variety of parameter values. In the eMMC specification (e.g., eMMC electrical standard 5.1 published in july 2014), the register 137 contains a 32-bit operation status register (Operation Condition Register, OCR), a 128-bit Device identification register (Device IDentification, CID Register), a 128-bit Device-specific data register (Device-SPECIFIC DATA, CSD REGISTER), a 512-byte Extended Device-specific data register (Extended CSD REGISTER, which may be abbreviated as an ext_csd register), and the like. The ext_csd register defines device attributes (Device Properties) and a Selected mode (Selected Modes), the most significant 320 bytes of which are attribute segments (Properties Segment) for defining the capabilities of the device and cannot be modified by the host side 110, and the other less significant 192 bytes are mode segments (Modes segments) defining the settings that the device is currently running. The host 110 can change these modes by a SWITCH command (CMD 6). The eMMC specification reserves a number of parts in the ext_csd register that can be used freely by the manufacturer of the device to perform the function of host performance acceleration Mode (Host Performance Acceleration, HPA Mode).

A Bus Architecture (Bus Architecture) 132 may be configured in the flash memory controller 130 for coupling components to each other for transferring data, addresses, control signals, etc., the components including a host interface 131, a processing unit 134, a ROM 135, a RAM136, registers 137, a flash memory interface 139, etc. In some embodiments, host interface 131, processing unit 134, ROM 135, RAM136, registers 137, and flash interface 139 may be coupled to each other by a single bus. In other embodiments, a high-speed bus may be configured in flash controller 130 for coupling processing unit 134, ROM 135, RAM136, and registers 137 to each other, and a low-speed bus may be configured for coupling processing unit 134, host interface 131, and flash interface 139 to each other. The bus includes parallel physical lines that connect two or more components in the flash controller 130.

Flash memory device 150 provides a large amount of storage space, typically hundreds of gigabytes (Gigabytes, GB), and even multiple terabytes (Terabytes, TB), for storing large amounts of user data, such as high-resolution pictures, movies, and the like. The flash memory device 150 includes a control circuit and a memory array, wherein the memory cells in the memory array may be configured as a single-layer cell (SINGLE LEVEL CELLS, SLCS), a multi-layer cell (Multiple LEVEL CELLS, MLCS), a triple-layer cell (TRIPLE LEVEL CELLS, TLCS), a Quad-layer cell (Quad-LEVEL CELLS, QLCS), or any combination thereof. The processing unit 134 writes user data to a specified address (destination address) in the flash memory device 150 through the flash memory interface 139, and reads the user data and a specified portion in the L2P lookup table from the specified address (source address) in the flash memory device 150. The flash interface 139 coordinates Data and command transfer between the flash controller 130 and the flash device 150 using a plurality of electronic signals, including a Data Line (Data Line), a Clock Signal (Clock Signal) and a Control Signal (Control Signal). The data lines may be used to transfer commands, addresses, read and Write data, and the control signal lines may be used to transfer control signals such as Chip Enable (CE), address fetch Enable (ADDRESS LATCH Enable, ALE), command fetch Enable (Command Latch Enable, CLE), write Enable (WE), etc.

Referring to fig. 2, the interface 151 in the flash memory device 150 may include four input/output channels (I/O channels, hereinafter referred to as channels) ch#0 to ch#3, each of which connects four NAND flash memory units, for example, the channel ch#0 connects the NAND flash memory units 153#0, 153#4, 153#8, and 153#12. Each NAND flash memory cell may be packaged as a separate chip (die). The flash interface 139 may activate the NAND flash units 153#0 to 153#3, 153#4 to 153#7, 153#8 to 153#11, or 153#12 to 153#15 by issuing one of the activation signals ce#0 to ce#3 through the interface 151, and then read user data from or write user data to the activated NAND flash units in parallel.

Since a continuous segment of data (i.e., a continuous segment of Logical block addresses, logical Block Addresses, LBAs) is stored in a distributed manner to NAND flash memory units to which a plurality of channels are connected, the flash memory controller 130 records a correspondence between Logical addresses (managed by the host device 110) and physical addresses (managed by the flash memory controller 130) of user data using a Logical-block-address to Physical-block-address (L2P Mapping Table). The L2P comparison table contains a plurality of records, and stores information of which physical address the user data of each logical address is actually stored in according to the order of the logical addresses. The data of a segment of contiguous LBAs can be segmented into multiple parts (Regions) identified by part numbers, and each part can be segmented into multiple Sub-Regions (Sub-Regions) identified by part numbers. For example, 128GB of data addressed using LBAs may be divided into 16 8GB portions, and each 8GB portion may be further divided into 256 32MB sub-regions. In the eMMC specification, each LBA is associated with (or points to) 512 Bytes (Bytes) of data. However, since the RAM 136 cannot provide enough space to store the entire L2P lookup table for the processing unit 134 to quickly search for future data reading operations, the entire L2P lookup table can be used to cut out multiple sub-tables according to the partial and sub-region division and respectively store the sub-tables in different physical addresses of the nonvolatile flash memory device 150, so that the corresponding sub-tables can be read from the flash memory device 150 to the RAM 136 at the future data reading operations. Referring to FIG. 3, the entire L2P lookup table may be cut into sub-tables 330#0-330#15. The processing unit 134 also maintains a High-level lookup Table (High-LEVEL MAPPING Table) 310 containing a plurality of records storing physical address information of the sub-Table associated with each LBA segment in the order of logical addresses. For example, the association sub-table 330#0 of the 0 th through 4095 th LBAs is stored in the 0 th physical page in the particular physical block of the particular logical unit number (Logical Unit Number, LUN) (the letter "Z" may represent the number of LUNs and physical blocks), the association sub-table 330#1 of the 4096 th through 8191 th LBAs is stored in the 1 st physical page in the particular physical block of the particular LUN, and so on. Although only 16 sub-tables are included in fig. 3, those skilled in the art may set more sub-tables according to the capacity of the flash memory device 150, and the present invention is not limited thereto.

To accommodate the physical configuration of the flash device 150, the flash controller 130 may associate (or point to) a physical block address (Physical Block Address, PBA) with (or point to) 4KB, 8KB, or 16KB of data that is greater than the length of the data associated with one LBA of the eMMC specification (512B). Because the LBAs are not consistent with the data lengths associated with the PBAs, each record in each sub-table contains information of logical addresses and physical addresses for precisely indicating the addresses in flash memory device 150. Referring to fig. 4, the sub-table 330#0 sequentially stores addressing information from lba#0 to lba#4095 (ADDRESSING INFORMATION). Addressing information may be represented in eight bytes, four bytes representing LBAs and the other four bytes representing PBAs. For example, record 400 associated with LBA#2 in sub-table 330#0 stores LBA 410 and PBA 430 information. Two bytes 430-0 in PBA 430 record the logical unit Number and physical block Number (Physical Block Number), and the other two bytes 430-1 record the physical page Number (PHYSICAL PAGE Number). Therefore, the physical address information 400 corresponding to LBA#2 may point to a specific Sector (Sector) 450#2 in the physical page 450 of the physical block 440.

To solve the problem that the flash memory controller 130 spends too much time on the logical-to-physical conversion, embodiments of the present invention add a new function of the HPA on the basis of the Host device communication architecture (Host-Device Communications Architecture) of the current eMMC specification. HPA converts the workload of the logical-physical comparison conversion, which is originally implemented by the flash memory controller 130 and needs a lot of time, to the host 110, thereby improving the random reading performance of short-length data, which can be from 512B to 32 KB. Referring to fig. 5, the host 110 configures a space in its System Memory (System Memory) as an HPA buffer 500 for temporarily storing information of an L2P lookup table maintained and managed by the device. HPA buffer 500 stores a plurality of L2P control records (L2P Mapping Records) received from the device side, each L2P control record recording addressing information corresponding to one LBA. Then, the host 110 may issue a command carrying the L2P reference record to the device for obtaining the user data of the specified LBA. The flash controller 130 can directly drive the flash interface 139 to read the user data of the specified LBA from the flash memory device 150 according to the information in the L2P comparison record, without taking time and computing resources to read the corresponding sub-table from the flash memory device 150 and performing the logical-physical address conversion as before to read the user data of the specified LBA from the flash memory device 150. For the establishment and utilization of HPA cache 500, three phases may be distinguished:

Stage I (HPA initialization) the host side 110 reads the value of the register 137 in the flash controller 130, checks whether the eMMC memory device (or device side, including at least the flash controller 130 and the flash device 150) supports HPA functions. If so, the host side 110 configures space in the system memory as an HPA L2P look-up table region.

Phase II (HPA lookup table management) if the eMMC memory device supports HPA functions, the host side 110 issues a series of commands for requesting the flash memory controller 130 to read the L2P lookup table. In response to the series of commands, flash controller 130 transmits all or a portion of the L2P lookup Table to host 110, and causes host 110 to store the obtained lookup Table in the HPA L2P lookup Table region (this may be referred to as a mirrored L2P lookup Table, mirrored L P Mapping Table). When the actual L2P table corresponding to the mirrored L2P table is changed due to the data writing, data pruning (DATA TRIMMING), garbage collection (Garbage Collection, GC), wear leveling (WEAR LEVELING), etc., the flash controller 130 notifies the host 110 that all or a corresponding portion of the L2P table in the system memory of the host 110 needs to be updated.

Stage III (HPA read) the host 110 issues a series of commands with L2P reference records to the eMMC memory device to request the retrieval of data of a specific LBA (especially small block length of discontinuous data, such as 512B to 32KB of discontinuous data), wherein the L2P reference records are searched from the mirrored L2P reference table. Then, the flash controller 130 reads the data of the specified LBA from the PBA of the flash memory device 150 according to the content of the L2P reference record, and replies the read data to the host 110, so that the eMMC storage device can save the time of reading and searching the L2P reference table for performing the logical-physical reference conversion.

In the eMMC specification, ext_CSD [160] (also referred to as PARTITIONING _SUPPORT [160 ]) defines SUPPORT section properties (Supported Partition Features), where Bits [7:3] are reserved for free use by the manufacturer of the eMMC memory device. The 3 rd Bit (ext_csd [160], bit [3 ]) of the 160 th byte of the ext_csd register may be used to define whether the eMMC memory device supports the HPA function, and is set to "1" if supported, and is set to "0" if turned off. During the initialization of the eMMC memory device, the processing unit 134 may set the Ext_CSD [160], bit [3] in the register 137 to "1". Although the embodiment of the present invention describes the technical scheme of defining whether the eMMC memory device supports HPA function with the Ext_CSD [160], the Bit [3], those skilled in the art can change the design to use other reserved bits in the Ext_CSD register, such as Ext_CSD[511:506]、Ext_CSD[485:309]、Ext_CSD[306]、Ext_CSD[233]、Ext_CSD[227]、Ext_CSD[204]、Ext_CSD[195]、Ext_CSD[193]、Ext_CSD[190]、Ext_CSD[188]、Ext_CSD[186]、Ext_CSD[184]、Ext_CSD[182]、Ext_CSD[180]、Ext_CSD[176]、Ext_CSD[172]、Ext_CSD[170]、Ext_CSD[135]、Ext_CSD[129:128]、Ext_CSD[127:64]、Ext_CSD[28:27]、Ext_CSD[14:0], etc., the present invention is not limited thereto.

In addition, the flash controller 130 may use the pair of ext_csd registers to record the information of the specified local and sub-areas that need to be updated in the L2P lookup table cached by the host 110. For example, the 64 th byte (Ext_CSD [64 ]) and the 66 th byte (Ext_CSD [66 ]) of the Ext_CSD register are paired to indicate the 0 th local (Region # 0) and the 160 th sub-Region (SubRegion # 160), respectively. The 65 th byte (Ext_CSD [65 ]) and 67 th byte (Ext_CSD [67 ]) of the Ext_CSD register are another pair for indicating the 0 th local (Region # 0) and 18 th sub-Region (SubRegion # 18), respectively.

In the eMMC specification, a switch command (CMD 6) is issued by the host 110 for switching the operating mode of the selected device or modifying the value of the ext_csd register, while Bits 26 to 31 (Bits [31:26 ]) of the parameters are reserved Bits. The host 110 may set the 26 th Bit of CMD6 (CMD 6, bit 26) to indicate whether the HPA function is activated, and set to "1" if activated and "0" if deactivated. Although the embodiment of the present invention describes the technical scheme that CMD6, bit [26] defines whether to activate the HPA function, those skilled in the art can change the design to use other reserved bits in the parameters of CMD6, and the present invention is not limited thereto. The host 110 may set the 27 th Bit (CMD 6, bit [27 ]) of CMD6 to indicate whether the L2P table acquisition function is started, and set to "1" if started and set to "0" if closed. Although the embodiment of the present invention describes the technical scheme that CMD6, bit [27] defines whether to start the acquisition function of the L2P lookup table, those skilled in the art can change other reserved bits in the parameters designed to use CMD6, and the present invention is not limited thereto.

In the eMMC specification, a set block count command (CMD 23) is issued by the host side 110 for indicating the number of blocks of a subsequent packed write command, or the number of blocks of a Header (Header) of a subsequent packed read command. When CMD23 is associated with a subsequent packed write command, the 30 th Bit (Bit [30 ]) in the parameter is set to "0b1", and the 0 th to 15 th Bits (Bits [15:0 ]) in the parameter of CMD23 are used to represent the number of blocks. When CMD23 is associated with a subsequent packed write command or packed read command, the 30 th Bit (Bit 30) in the parameter is set to "0b1". Bits 0 to 15 (Bits [15:0 ]) in the parameters of CMD23 are used to represent the number of blocks.

In the eMMC specification, a write multi-block command (CMD 25) is issued by the host 110 for writing data blocks to the eMMC memory device until a STOP transfer command (stop_ TRANSMISSION Command, CMD 12) is issued or the requested number of data blocks have been written. The host 110 may send the information specifying the local and the sub-area in the L2P lookup table via CMD23 and CMD25, and request the flash memory controller 130 to prepare the L2P lookup record specifying the local and the sub-area. In addition, the host 110 can send the L2P control record via CMD23 and CMD25 to request the flash memory controller 130 to prepare data for future reading. Bits 0 to 31 (Bits [31:0 ]) in the parameters of CMD25 represent the data address.

In the eMMC specification, a read multi-block Command (CMD 18) is issued by the host 110 for continuously reading data blocks from the eMMC memory device until the requested number of data blocks have been read out or interrupted by a Stop Command (Stop Command). That is, the CMD18 requests the eMMC storage device to transmit the previously indicated number of data blocks to the host side 110. Bits 0 to 31 (Bits [31:0 ]) in the parameters of CMD18 represent the data address. The host 110 may request the flash controller 130 to transfer the L2P control record specifying the local and sub-area (defined in the previous CMD 25) through CMD23 and CMD 18. Referring to the example shown in fig. 4, the length of each L2P control record is 8B, so that each data block can carry a maximum of 32L 2P control records. In addition, the host 110 may request the flash controller 130 to transfer data corresponding to the L2P control record (defined in the previous CMD 25) through the CMD23 and the CMD 18.

In the eMMC specification, a normal reply command (Normal Response Command, R1) is issued by the flash controller 130 to tell the host side 110 specific information. The length of R1 is 48 Bits, of which Bits 40 to 45 (Bits [45:40 ]) record the index of the command to be replied to, and Bits 8 to 39 (Bits [39:8 ]) record the Device Status. When the 31 st Bit (Bit [31 ]) OF R1 is set to "0b1", it represents an ADDRESS exceeding RANGE (ADDRESS_OUT_OF_RANGE). When the 30 th Bit (Bit [30 ]) of R1 is set to "0b1", ADDRESS mismatch (ADDRESS_ MISALIGN) is represented. When the HPA function is started but the L2P lookup table acquisition function is not started, if some of the PBAs in the L2P lookup record carried in the CMD25 fail, the flash controller 130 may set the 31 st Bit (Bit 31) and the 30 th Bit (Bit 30) of R1 of the CMD18 after the reply to "0b1" to indicate that the cached L2P lookup record in the host 110 needs to be updated.

For the establishment of the HPA L2P look-up table region (also may be referred to as HPA buffer) in phase I and phase II, after the eMMC memory device is initialized, the host side 110 first reads the L2P look-up table from the device side and stores it to the HPA buffer. Table 1 describes exemplary command order details for initializing the HPA buffer:

TABLE 1

Referring to the operational sequence diagram of HPA buffer initialization as shown in FIG. 6, the following is described in detail:

Operation 611. The host 110 issues a command to the flash controller 130 requesting the flash controller 130 to obtain the value of the ext_csd register.

In response to the register read command received through the host interface 131, the processing unit 134 obtains the value of the ext_csd register in the registers 137 and replies to the host 110 through the host interface 131.

The host side 110 may check the value of the Ext_CSD register (e.g., ext_CSD [160], bit [3 ]) to determine if the eMMC memory device supports HPA functionality. If so, processing continues with operation 617. If not, the HPA function is not activated.

Operation 617. The host 110 issues a switch command (CMD 6) to the flash controller 130 to activate the HPA function and the L2P table acquisition function. For example, referring to the second row of table 1, the host 110 may set the parameter of CMD6 to "0x0C000000", that is, include Bit [26] = "0b1" and Bit [27] = "0b1", for instructing the flash memory controller 130 to start the two functions.

Operation 619 after receiving the switch command as described above, the flash controller 130 enters an HPA mapping_ READ STATE state for preparing to transmit a part of the L2P Mapping table to the host 110.

In operation 631, the host 110 allocates space in the system memory to the HPA buffer, and determines the local and sub-area L2P reference records to be obtained from the eMMC memory device according to the requirements of the operating system, the drivers, the applications, etc.

Operation 633, the host 110 issues a set block count command (CMD 23) to the flash controller 130 for informing the flash controller 130 how many data blocks to transfer. For example, referring to the third row of table 1, the host 110 can set the parameter of CMD23 to "0x40000001", i.e. including Bit [30] = "0b1" and Bit [15:0] = "0x0001", indicating that a data block will be written to the flash memory controller 130 afterwards. Then, the host 110 issues a write multi-block command (CMD 25) to the flash controller 130 for continuously writing data blocks to the flash controller 130 until the requested number of data blocks have been written. For example, referring to the fourth row of table 1, the host 110 can set the parameter of CMD25 to "0x01E2A3E0" representing a specific data address. Each data block may be divided into 32 Packets (Packets), and each packet has a length of 16B. The 2 bytes in each packet may indicate the number of a particular part, while the remaining 14 bytes may indicate the numbers of a number of particular subregions. For example, when a packet contains information of { region#0, sub region#1, sub region#2, sub region#3}, a specified portion representing the L2P lookup table is associated with the 0 th to 3 rd sub-regions in the 0 th part. Then, the host 110 issues a set block count command (CMD 23) to the flash controller 130 for informing the flash controller 130 how many data blocks will be received. For example, referring to the fourth row of table 1, the host 110 can set the parameter of CMD23 to "0x40000020", i.e. including Bit [30] = "0b1" and Bit [15:0] = "0x0020", which means that 32 data blocks, i.e. at most 1024L 2P control records, will be read from the flash memory controller 130. Then, the host 110 issues a read multi-block command (CMD 18) to the flash controller 130 for continuously reading the data blocks from the flash controller 130 until the requested number of data blocks have been read. For example, referring to the fifth row of table 1, the host 110 can set the parameter of CMD18 to "0x01E2A3E0" to represent a specific data address.

Operation 635, since the HPA look-up table read state has been entered, when the flash controller 130 receives a data block corresponding to CMD25 from the host side 110, it is known that each packet therein carries information of the specified portion of the L2P look-up table, and the requested L2P look-up record can be read from the flash memory device 150 accordingly. In addition, when the flash controller 130 receives the CMD18 from the host 110, it is known that it can start transmitting the L2P reference record of the specified portion to the host 110. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transferred by the flash memory controller 130 is the L2P reference record of the designated portion read from the flash memory device 150 according to the contents of the data block written by the previous CMD 25.

The flash controller 130 organizes the requested L2P control record into a plurality of packets in a specified number of data blocks, operation 651.

In operation 653, the flash controller 130 continues to transfer the organized data blocks to the host 110 until the designated number of data blocks are transferred. Next, when receiving the packed read completed information from the host side 110, the HPA lookup table read state is left and the transfer state of the eMMC specification is entered (TRANSFER STATE).

Operation 655 the host side 110 receives the L2P control record carried in each packet and stores it in the HPA buffer. After storing the L2P comparison record carried in the last packet, the host 110 issues a send_status command (CMD 13) to the flash memory controller 130, which includes information about the completion of the package read.

For phase III data reads, table 2 describes example command order details for reading data using the HPA function:

TABLE 2

Referring to the operational sequence diagram of HPA reading as shown in FIG. 7, the following is explained in detail:

Operation 711 the host side 110 finds that random reading of short length data is about to occur.

Operation 713, host 110 issues a switch command (CMD 6) to flash controller 130 to initiate the HPA function. For example, referring to the second row of table 2, the host 110 may set the parameter of CMD6 to "0x04000000", that is, include Bit [26] = "0b1" and Bit [27] = "0b0", for indicating that the flash memory controller 130 only activates the HPA function.

Operation 715 is to enter an HPA read state (hpa_ READ STATE) when the flash controller 130 receives the switch command as described above.

Operation 731. The host side 110 searches the mirrored L2P lookup table in the HPA buffer to obtain L2P lookup records corresponding to the plurality of LBAs.

In operation 733, the host 110 issues a set block count command (CMD 23) to the flash controller 130 for informing the flash controller 130 how many data blocks to transfer. For example, referring to the third row of table 2, the host 110 can set the parameter of CMD23 to "0x40000001", i.e. including Bit [30] = "0b1" and Bit [15:0] = "0x0001", indicating that a data block will be written to the flash memory controller 130 afterwards. Then, the host 110 issues a write multi-block command (CMD 25) to the flash controller 130 for continuously writing data blocks to the flash controller 130 until the requested number of data blocks have been written. For example, referring to the fourth row of table 2, the host 110 may set the parameter of CMD25 to "0x01521182" representing a specific data address. Each data block may be divided into 32 Packets (Packets), and each packet has a length of 16B. Each packet is associated with a pair of LBA and PBA information, 8 bytes of which may indicate a particular LBA and the remaining 8 bytes may indicate a particular PBA. Then, the host 110 issues a set block count command (CMD 23) to the flash controller 130 for informing the flash controller 130 how many data blocks will be received. For example, referring to the fifth line of table 2, the host 110 can set the parameter of CMD23 to "0x40000020", i.e. including Bit [30] = "0b1" and Bit [15:0] = "0x0020", which indicates that 32 data blocks, i.e. data of at most 1024 LBAs, are to be read from the flash memory controller 130. Then, the host 110 issues a read multi-block command (CMD 18) to the flash controller 130 for continuously reading the data blocks from the flash controller 130 until the requested number of data blocks have been read. For example, referring to the sixth row of table 2, the host side 110 can set the parameter of CMD18 to "0x01521182" representing a specific data address.

Operation 735, since the HPA read state has been entered, when the flash controller 130 receives a data block corresponding to CMD25 from the host side 110, it is known that each packet therein carries information of paired LBAs and PBAs for one data read, and the requested data can be read from the flash memory device 150 accordingly. In addition, when the flash controller 130 receives the CMD18 from the host 110, it is known that it can start transmitting the specified data to the host 110. Since the parameters of CMD18 are set to be the same as those of CMD25, the data transferred by flash controller 130 is the data of the specified LBA read from flash memory device 150 according to the contents of the data block written by CMD25 previously.

Operation 751 the flash controller 130 organizes the requested data into a plurality of packets in a specified number of data blocks.

Operation 753 flash controller 130 continues to transfer the organized data blocks to host 110 until the designated number of data blocks are transferred. Next, when receiving the packed read completed information from the host side 110, the HPA read state is left and the transfer state of the eMMC specification is entered.

Operation 755 the host side 110 receives the data carried in each packet and stores it in a data buffer of the system memory. After storing the data carried in the last packet, the host 110 issues a transfer status command (CMD 13) to the flash controller 130, which includes information about the completion of the package read.

For the update of the HPA buffer in phase II, during the device side operation, the host side 110 may request the flash controller 130 to perform operations such as data writing, data pruning (DATA TRIMS), block erasing (Block Erases), etc., and the flash controller 130 may actively perform procedures such as garbage collection (Garbage Collection, GC), wear leveling (WEAR LEVELING, WL), etc., so that part of the contents of the L2P lookup table is changed. Therefore, the contents of the HPA buffer (i.e., the mirrored L2P look-up table) need to be updated according to the changed contents of the L2P look-up table. Referring to the operation sequence diagram of the HPA read as shown in fig. 8, the technical solutions of operations 711 to 733 and operations 751 to 753 are the same as fig. 7, and the remaining operations are described in detail as follows:

Operation 835 knows that each packet therein carries information of paired LBAs and PBAs for one data read when the flash controller 130 receives a data block corresponding to CMD25 from the host side 110 because the HPA read state has been entered, and checks whether the LBA reference record of the LBA data to be read is changed (i.e., invalidated). If so, the flash controller 130 ignores the information carried in the data block and instead reads the data from the flash device 150 according to the changed corresponding LBA comparison record. When the flash controller 130 receives the CMD18 from the host 110, it is known that the transfer of the specified data to the host 110 can begin. Since the parameters of CMD18 are set to be the same as the parameters of CMD25, the data transferred by flash memory controller 130 is the data of the specified LBA read from flash memory device 150 according to the content of the data block written by CMD25 previously or according to the content of the corresponding LBA control record after the change. In addition, when the LBA reference record of the LBA data to be read is invalid, the flash controller 130 sets the associated Ext_CSD register to store the information of the local and sub-areas to be updated in the HPA buffer of the host 110.

In operation 837, the flash controller 130 sends R1 to reply CMD18, wherein the 31 st Bit (Bit 31) and the 30 th Bit (Bit 30) are set to "0b1" to indicate that the mirror L2P table in the host 110 needs to be updated.

After the host 110 receives the information that the mirrored L2P lookup table needs to be updated from the device, the host 110 obtains the information of the local and sub-areas that need to be updated from the device, and accordingly reads the L2P lookup record of the specified portion of the L2P lookup table from the device, and updates the corresponding contents in the HPA buffer. Table 3 describes example command order details for updating the HPA buffer:

TABLE 3 Table 3

Referring to the operational sequence diagram of the HPA buffer update shown in FIG. 9, the technical solution of operations 611, 613, 617, 619, 633, 635, 651, and 653 are the same as those of FIG. 6, and the remaining operations are described in detail as follows:

operation 915 the host side 110 obtains the information of the local and sub-areas that need to be updated from the value of the ext_csd register (e.g., ext_csd 67: 64).

In operation 931, the host 110 determines the local and sub-area L2P control records to be retrieved from the eMMC memory device according to the information retrieved from the flash controller 130.

Operation 955 the host side 110 receives the L2P control record carried in each packet and updates the corresponding portion of the content in the HPA buffer. After updating the L2P comparison record carried in the last packet, the host 110 sends CMD13 to the flash memory controller 130, which includes the information of the completion of the package read.

For details regarding execution of CMD6 in command processing operations 619,715, reference is made to a flowchart of a method as shown in fig. 10, which is implemented by the processing unit 134 when loading and executing associated software or firmware program code, and further described below:

Step S1010, a handover command (CMD 6) is received from the host side 110 through the host interface 131.

Step S1020, judging whether the reserved bit of CMD6 contains information for starting the HPA function and the acquisition function of the L2P comparison table. If so, the flow continues with the process of step S1030. Otherwise, the flow continues the process of step S1040.

Step 1030, the RAM 136 stores the information of the read state of the HPA comparison table, so that the information can be used as the basis for judging the current device state when the CMD25 is received later.

Step S1040, determining whether the reserved bit of CMD6 contains information for starting the HPA function. If so, the flow continues with the process of step S1050. Otherwise, the flow continues the process of step S1060.

In step S1050, the RAM 136 stores the information of entering into the HPA read state, so that the CMD25 can be used as a basis for judging the current device state when it is received later.

Step S1060, a conventional handover procedure is performed. For example, switching the operation mode of the device side, modifying the value of the ext_csd register, and so on.

Details of execution of CMD25 in command processing operations 635, 735, and 835 are provided with reference to a method flow diagram as shown in fig. 11, which is implemented by processing unit 134 when loading and executing associated software or firmware program code, as further described below:

step S1110, a write multi-block command (CMD 25) and the following data block are received from the host side 110 through the host interface 131.

Step S1121, judge whether to enter HPA comparison table read state or HPA read state according to the information stored in RAM 136. If so, the flow continues with a further determination of step S1131. Otherwise, the flow proceeds to the process of step S1123.

In step S1123, a conventional package writing Procedure (PACKED WRITE process) is performed to drive the flash interface 139 to write multiple packets of data to the flash device 150.

Step S1131, judge whether to enter HPA comparison table reading state according to the information stored in RAM 136. If so, the flow proceeds to the process of step S1133. Otherwise (i.e., enter the HPA read state), the flow proceeds to the judgment of step S1141.

In step S1133, the flash memory interface 139 is driven to read the L2P reference record of the specified portion of the L2P reference table from the flash memory device 150 according to the information carried in the data block (i.e. the information of the specific local area and the specific sub-area).

In step S1135, the L2P control record is stored in the multi-packet format as described above in the RAM 136, so that the L2P control record can be transferred to the host 110 in the multi-packet format after receiving the CMD 18.

In step S1141, it is determined whether the LBA reference record associated with the LBA data to be read has been changed. If so, the flow proceeds to the process of step S1145. Otherwise, the flow proceeds to the process of step S1143.

In step S1143, the flash memory interface 139 is driven to read the data of the specified LBA from the flash memory device 150 according to the information carried in the data block (i.e. the information recorded by the L2P reference).

In step S1145, the drive flash interface 139 reads the data of the specified LBA from the flash memory device 150 according to the changed corresponding LBA comparison record.

Step S1147 is to store the LBA-specific data in the multi-packet format as described above in RAM 136, so that the LBA-specific data can be transferred to host 110 in the multi-packet format in the future after receiving CMD 18.

All or part of the steps in the methods described herein may be implemented by a computer program, such as a firmware translation layer (Firmware Translation Layer, FTL) in a storage device, a hardware-specific driver, or a software program. In addition, other types of programs as shown above may also be implemented. Those skilled in the art will appreciate that the methodologies of the embodiments of the present invention are capable of being written as program code and that these are not described in the interest of brevity. A computer program implemented according to a method of an embodiment of the invention may be stored on a suitable computer readable storage medium, such as a DVD, CD-ROM, U-disk, hard disk, or may be located on a network server accessible via a network, such as the internet, or other suitable medium.

Although the components described above are included in fig. 1-2, it is not excluded that many more additional components may be used to achieve a better technical result without violating the spirit of the invention. In addition, although the flowcharts of fig. 10 and 11 are executed in the order specified, the order among these steps may be modified by those skilled in the art without departing from the spirit of the invention, and therefore, the present invention is not limited to using only the order described above. Furthermore, one skilled in the art may integrate several steps into one step or perform more steps in addition to these steps, sequentially or in parallel, and the invention should not be limited thereby.

The above description is only of the preferred embodiments of the present application, but not limited thereto, and any person skilled in the art can make further modifications and variations without departing from the spirit and scope of the present application, and the scope of the present application is defined by the appended claims.

Claims

1. The data reading method of the host efficiency acceleration mode is executed by a host end and is characterized by comprising the following steps:

Searching a host performance acceleration buffer in a system memory to obtain a first logical physical comparison record associated with a logical block address;

A first switching command is sent to a flash memory controller and used for requesting the flash memory controller to start a host efficiency acceleration function but not to start a logic physical comparison table acquisition function, wherein the host side and the flash memory controller are communicated with each other through an embedded multimedia card communication protocol;

Issuing a first write multi-block command to the flash memory controller for writing a first data block to the flash memory controller, the first data block comprising the first logical physical control record for storing information of a physical address at which data of a logical address is actually stored, and

And issuing a first read multi-block command to the flash memory controller for retrieving data corresponding to the first logical physical control record from the flash memory controller.

2. The method of claim 1, wherein the first logical physical control record comprises a logical block address and a physical block address, the logical block address being associated with data of a first length, the physical block address being associated with data of a second length, the second length being greater than the first length.

3. The method for data reading in a host performance acceleration mode of claim 2, wherein the first length is 512 bytes.

4. The method for reading data in a host performance acceleration mode of claim 1, further comprising:

Receiving a normal reply command from the flash memory controller corresponding to the first read multi-block command, indicating that the contents of the host performance acceleration buffer need to be updated;

After receiving the normal reply command, acquiring information of a part to be updated in the host efficiency acceleration buffer area from the flash memory controller;

Sending a second switching command to the flash memory controller, wherein the second switching command is used for requesting the flash memory controller to start the host efficiency acceleration function and the acquisition function of the logical physical comparison table;

Issuing a second write multi-block command to the flash memory controller for writing a second data block to the flash memory controller, wherein the second data block comprises a local number and a subarea number of a part to be updated;

issuing a second read multi-block command to the flash memory controller for retrieving a plurality of second logical physical control records corresponding to the local number and the sub-region number from the flash memory controller, and

And updating the corresponding part of content in the host efficiency acceleration buffer into the second logical physical control record.

5. The data reading method of the host efficiency acceleration mode is executed by a flash memory controller and is characterized by comprising the following steps:

receiving a switching command from a host end, wherein the switching command is used for requesting the flash memory controller to start a host efficiency acceleration function, but not to start a logic physical comparison table acquisition function, and the host end and the flash memory controller are communicated with each other through an embedded multimedia card communication protocol;

entering a state according to the switching command;

receiving a write multi-block command from the host side during entering the state;

Obtaining a logical physical comparison record from a data block received by the host according to the writing multi-block command, and reading data corresponding to the logical physical comparison record from a flash memory device, wherein the logical physical comparison record is used for storing information of a physical address in which data of a logical address is actually stored;

receiving a read multi-block command from the host side during entering the state, and

And transmitting data corresponding to the logical physical comparison record to the host side according to the read multi-block command.

6. The method of claim 5, wherein the first reserved bit in the switch command includes information to activate the host performance acceleration function, and the second reserved bit in the switch command includes information to not activate the get function of the logical-physical lookup table.

7. The method for reading data in the host performance acceleration mode of claim 5, further comprising:

When the logical-physical comparison record is detected to be invalid, a normal reply command corresponding to the read multi-block command is sent to indicate that the content in the host efficiency acceleration buffer in the system memory needs to be updated.

8. The method of claim 5, wherein the write multi-block command is used to allow the host to write data blocks to the flash memory controller until a default number of data blocks have been written.

9. The method of claim 5, wherein the read multi-block command is used to allow the host side to continuously read data blocks from the flash memory controller until a default number of data blocks have been read.

10. A data reading apparatus in a host performance acceleration mode, comprising:

A host interface coupled to the host end;

A flash memory interface coupled to the flash memory device, and

The processing unit is coupled to the host interface and the flash memory interface, receives a switch command from the host end through the host interface, and is used for requesting the device to start a host performance acceleration function, but not start a logic physical comparison table acquisition function, wherein the host end and the device communicate with each other through an embedded multimedia card communication protocol, enter a state according to the switch command, receive a write multi-block command from the host end through the host interface during the state is entered, acquire a logic physical comparison record from a data block received from the host end through the host interface according to the write multi-block command, and read data corresponding to the logic physical comparison record from the flash memory device through the flash memory interface, wherein the logic physical comparison record is used for storing information of a physical address where the data of a logic address is actually stored, receive a read multi-block command from the host end through the host interface during the state is entered, and transmit the data corresponding to the logic physical comparison record to the host end through the host interface according to the read multi-block command.

11. The device for reading data in a host performance acceleration mode of claim 10, wherein a first reserved bit in the switch command includes information to activate the host performance acceleration function, and a second reserved bit in the switch command includes information to not activate the get function of the logical-to-physical lookup table.

12. The data reading apparatus according to claim 10, wherein the logically physical control record comprises a logical block address and a physical block address, the logical block address being associated with data of a first length, the physical block address being associated with data of a second length, the second length being greater than the first length.

13. The data reading apparatus according to claim 12, wherein the first length is 512 bytes.

14. The device for reading data in a host performance acceleration mode of claim 10, wherein the processing unit sends a normal reply command corresponding to the read multi-block command via the host interface indicating that the contents of the host performance acceleration buffer in the system memory need to be updated when the logical-physical-reference record is detected as invalid.

15. The device of claim 10, wherein the write multi-block command is configured to allow the host side to write data blocks to the device until a default number of data blocks have been written.

16. The device of claim 10, wherein the read multi-block command is configured to allow the host side to continue reading data blocks from the device until a default number of data blocks have been read.