CN113947051B - A method, system and device for allocating registers of memory pins - Google Patents
A method, system and device for allocating registers of memory pins Download PDFInfo
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Abstract
The application discloses a register allocation method, a system and a device of a memory pin under a built-in self test of a memory. The application allocates the same register for the memory pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values on the chip, thereby greatly reducing the number of the registers allocated for the memory pins on the chip, further reducing the area and cost of the chip, reducing the programming workload and programming error rate of the RTL design of the chip, realizing a full-automatic process, and reducing the labor cost and the artificial error probability.
Description
Technical Field
The present invention relates to the field of memories, and in particular, to a method, a system, and an apparatus for allocating registers of a memory pin.
Background
In MBIST (MemoryBuilt-INSELFTEST, memory built-in self-test) design of a memory, a corresponding controller needs to be provided to the memory in order to control the behavior of the memory in MBIST test.
Currently, pins of a memory need to be initialized before MBIST testing to adjust the memory to a test state, i.e., external circuitry needs to be set to initialize the pins of the memory. Based on the connection between the controller and the test pins related to MBIST test on the memory, these test pins are usually initialized by the controller, but besides these test pins, some pins not connected to the controller on the memory need to be initialized, such as power consumption control pins and timing adjustment pins, otherwise, the MBIST test effect of the memory is affected, and these pins to be initialized are configured by adding TDR (TEST DATA REGISTER ), specifically, a TDR register is connected to one pin, and the initialization configuration value corresponding to the pin is written into the connected register.
However, in a large SOC (System on Chip) Chip, there may be hundreds or even more memories, which together may have thousands of pins that require registers to be configured, resulting in a larger number of registers, and thus a larger Chip area and higher cost. In addition, the RTL (REGISTER TRANSFER LEVEL, register conversion level circuit) design of the SOC chip is a manual writing of hardware description language to describe the circuit structure and circuit function, which can be a very heavy and complex task if so many registers are manually written in the RTL design; moreover, manually writing so many registers in an RTL design introduces a high probability of errors, thereby increasing the cost of making errors.
Therefore, how to provide a solution to the above technical problem is a problem that a person skilled in the art needs to solve at present.
Disclosure of Invention
The invention aims to provide a register allocation method, a system and a device for memory pins, which are based on built-in self-test of a memory, so that the number of registers allocated to the memory pins on a chip is greatly reduced, the area and the cost of the chip are reduced, the programming workload and the programming error rate of RTL design of the chip are reduced, a full-automatic process is realized, and the labor cost and the artificial error probability are reduced.
In order to solve the above technical problems, the present invention provides a method for allocating registers of memory pins, based on built-in self-test of memory, comprising:
classifying all memories on a chip according to the types of the memories to obtain memories of the same type on the chip;
determining a target pin which is required to be configured by a register on the same type of memory according to the pin initialization requirement of the same type of memory;
Determining the initialization configuration value of a target pin on each memory of the same type according to the preset corresponding relation between the memory parameters and the pin initialization configuration values of the same type;
and allocating the same register for the target pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values, so as to finish the register allocation of the target pins on each memory.
Optionally, a preset process of the correspondence between the memory parameter and the pin initialization configuration value under the same type includes:
According to the type, depth, bit width and column multiplexing selector and voltage threshold value of each memory, an initialization configuration value is defined for each pin needing to be configured by a register on each memory, so as to obtain the corresponding relation between the memory parameters and the pin initialization configuration values under the same type.
Optionally, allocating the same register to the target pins which are located on different memories of the same type and have identical pin bit widths and initialization configuration values, includes:
Distributing registers for target pins on each memory one by one;
and merging the registers allocated by the target pins which are positioned on different memories of the same type and consistent in pin bit width and initialization configuration values.
Optionally, allocating the same register to the target pins which are located on different memories of the same type and have identical pin bit widths and initialization configuration values, includes:
Dividing target pins which are positioned on different memories of the same type and have consistent pin bit widths and initialization configuration values into the same group of target pins;
and allocating the same register for the same group of target pins.
Optionally, the register allocation method of the memory pin further includes:
And according to the register allocation condition of the target pins on each memory, automatically generating an RTL file for describing the connection relation between the target pins and the registers of each memory.
Optionally, according to the register allocation situation of the target pin on each memory, autonomously generating an RTL file for describing the connection relation between the target pin and the register of each memory includes:
according to the register allocation situation of the target pins on each memory, an EDA tool is utilized to autonomously generate a configuration file for representing the connection relation between the target pins of each memory and the registers;
And converting the configuration file into an ICL file, and converting the ICL file into an RTL file.
Optionally, the register allocation method of the memory pin further includes:
According to the initialization configuration values of the target pins on the memories, determining the initialization configuration values corresponding to each register connected with the memories;
and autonomously generating a PDL file representing the initialization configuration value corresponding to each register for each register so as to realize the configuration of each register based on the PDL file.
In order to solve the above technical problem, the present invention further provides a register allocation system for memory pins, based on a built-in self-test of a memory, including:
The memory classification module is used for classifying all memories on a chip according to the memory types to obtain memories of the same type on the chip;
the pin determining module is used for determining a target pin which is required to be configured by a register on the memory of the same type according to the pin initializing requirement of the memory of the same type;
the configuration value determining module is used for determining the initialization configuration value of the target pin on each memory of the same type according to the corresponding relation between the preset memory parameters of the same type and the pin initialization configuration values;
and the register allocation module is used for allocating the same register to the target pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values so as to finish the register allocation of the target pins on each memory.
Optionally, the register allocation system of the memory pin further includes:
And the file generation module is used for autonomously generating an RTL file for describing the connection relation between the target pins and the registers of the memories according to the register allocation situation of the target pins on the memories.
In order to solve the above technical problem, the present invention further provides a register allocation device for a memory pin, based on a built-in self-test of a memory, including:
a memory for storing a computer program;
a processor for implementing the steps of any of the memory pin register allocation methods described above when executing the computer program.
The application provides a register allocation method of memory pins, which classifies memories on a chip according to memory types based on built-in self-test of the memories to obtain memories of the same type on the chip; determining a target pin which needs to be configured by a register on the same type of memory according to the pin initialization requirement of the same type of memory; determining the initialization configuration value of a target pin on each memory of the same type according to the preset corresponding relation between the memory parameters and the pin initialization configuration values of the same type; the same register is allocated for the target pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values, so that the register allocation of the target pins on each memory is completed. Therefore, the application allocates the same register for the memory pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values on the chip, thereby greatly reducing the number of the registers allocated for the memory pins on the chip, further reducing the area and cost of the chip, reducing the programming workload and programming error rate of RTL design of the chip, realizing a full-automatic process, and reducing the labor cost and the artificial error probability.
The invention also provides a register allocation system and a register allocation device for the memory pins, which have the same beneficial effects as the register allocation method based on the built-in self test of the memory.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a method for allocating registers of a memory pin according to an embodiment of the present invention;
FIG. 2 is a flowchart of a method for allocating registers of a memory pin according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an MBIST test of a memory according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a register allocation system for memory pins according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a register allocation method, a system and a device for memory pins, which are based on built-in self-test of a memory, so that the number of registers allocated to the memory pins on a chip is greatly reduced, the area and the cost of the chip are reduced, the programming workload and the programming error rate of RTL design of the chip are reduced, a full-automatic process is realized, and the labor cost and the artificial error probability are reduced.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart of a method for allocating registers of a memory pin according to an embodiment of the invention.
The register allocation method of the memory pin is based on the built-in self test of the memory and comprises the following steps:
Step S1: and classifying the memories on the chip according to the memory types to obtain the memories of the same type on the chip.
In particular, in large chip designs, internal memory requirements are increasing such that the memory area on the chip is typically over 50% and the number of memories is significant. Among the many memories of the chip, the types of memories are more than one, and some are even more than ten, including a high-performance single-port memory, a high-density dual-port memory, a high-density read-only memory and the like.
Considering that pins of memories of different types to be initialized before MBIST test are different, the application classifies all memories on a chip according to the memory types to obtain memories of the same type on the chip, namely, all memories of each type on the chip are counted according to the memory types, and all memories of each type on the chip can be correspondingly stored in a corresponding list of each type.
Step S2: and determining a target pin which needs to be configured by adopting a register on the same type of memory according to the pin initialization requirement of the same type of memory.
Specifically, pins that need to be initialized before MBIST testing are the same for the same type of memory, i.e., the pin initialization requirements (referring to which pins of the memory need to be initialized) are the same for the same type of memory; the pins that need to be initialized before MBIST testing are different for different types of memories, i.e., the pin initialization requirements are different for different types of memories.
Taking a memory of a target type as an example, the application determines a pin to be initialized on the memory of the target type on a chip according to the pin initialization requirement of the memory of the target type. Since the test pins related to MBIST test on the memory of the target type (which are connected based on the controller and the test pins related to test on the memory, so that the initialization is realized by the controller) are known, the application removes the test pins to be initialized on the memory of the target type on the chip by the controller, and the rest is the target pins (common power consumption control pins and time sequence adjustment pins) which need to be configured by the register on the memory of the target type, so that the target pins which need to be configured by the register on each memory after classification are counted.
Step S3: and determining the initialization configuration value of the target pin on each memory of the same type according to the preset corresponding relation between the memory parameters and the pin initialization configuration values of the same type.
Specifically, the application sets the corresponding relation between the parameters of the memory and the initializing configuration values of the pins under the same type in advance, namely, the parameters of the memory of the same type are different, the initializing configuration values of the pins on the memory are different, and the parameters and the initializing configuration values of the pins have a certain corresponding relation. It should be noted that, under each memory type, the corresponding relationship between the memory parameter and the pin initialization configuration value is set.
Taking a memory of a target type as an example, the method firstly acquires the memory parameters of all memories of the target type, and then can determine the initialization configuration value of the target pin needing to be configured by adopting a register on each memory of the target type according to the corresponding relation between the memory parameters and the pin initialization configuration value under the preset target type.
Step S4: the same register is allocated for the target pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values, so that the register allocation of the target pins on each memory is completed.
Specifically, considering that there are target pins with consistent pin bit widths and initialization configuration values on different memories of the same type, the target pins can share the same register (the registers which are referred to as the pin allocation of the memories in the application are all referred to as TDR registers), so the application allocates the same register for the target pins which are positioned on different memories of the same type and consistent in pin bit widths and initialization configuration values, thereby completing the register allocation of the target pins on all memories on a chip.
Therefore, the application allocates the same register for the memory pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values on the chip, thereby greatly reducing the number of the registers allocated for the memory pins on the chip, further reducing the area and cost of the chip, reducing the programming workload and programming error rate of RTL design of the chip, realizing a full-automatic process, and reducing the labor cost and the artificial error probability.
Based on the above embodiments:
as an optional embodiment, the presetting process of the correspondence between the memory parameter and the pin initialization configuration value under the same type includes:
According to the type, depth, bit width and column multiplexing selector and voltage threshold value of each memory, an initialization configuration value is defined for each pin needing to be configured by a register on each memory, so as to obtain the corresponding relation between the memory parameters and the pin initialization configuration values under the same type.
Specifically, the application can define an initialization configuration value for each pin needing to be configured by a register on each memory according to the type, depth (WD), bit width (IO, depth multiplied by bit width is equal to capacity of the memory), column multiplexing selector (mux, related to a coding circuit of the memory) and voltage threshold (VT, representing storage speed of the memory, including ULVT (Ultra Low Voltage Threshold, ultra-low voltage threshold), LVT (Low Voltage Threshold ) and SVT (Standard Voltage Threshold, standard voltage threshold)).
As shown in table 1 below, the correspondence between memory parameters and the initialization configuration values of the timing adjustment pins WTSEL for a certain type is described:
TABLE 1
If the parameters of one memory are: depth wd=64, bit width io=32, column multiplexer selector mux=8, and voltage threshold LVT, the initialization configuration value of the timing adjust pin WTSEL of the memory is 11.
It should be noted that, the application can write a function algorithm to cover the configuration table of each type of memory pins, so as to automatically determine the initialization configuration value of the pins according to the parameters of the memory, and improve the working efficiency.
As an alternative embodiment, allocating the same register to a target pin located on a different memory of the same type and having a consistent pin bit width and initialization configuration value, includes:
allocating registers for target pins on each memory one by one;
and merging the registers allocated by the target pins which are positioned on different memories of the same type and consistent in pin bit width and initialization configuration values.
Specifically, the first register allocation manner of the target pins on each memory of the chip is as follows: 1) Registers are allocated to all target pins on the memory of the chip one by one, namely one register is allocated to one target pin; 2) And merging the registers allocated by the target pins which are positioned on different memories of the same type and have consistent pin bit widths and initialization configuration values, namely sharing the same register by the target pins which are positioned on different memories of the same type and have consistent pin bit widths and initialization configuration values.
For example, the timing adjust pins WTSEL of three memories are combined to be controlled by a TDR register sri_tdr_ wtsel:
Tdr(sri_tdr_wtsel){
DataOutPorts{port_name:wtsel；
Connection(1:0):memory1/WTSEL；
Connection(1:0):memory2/WTSEL；
Connection(1:0):memory3/WTSWL；}
}
where sri_tdr_ wtsel is the name of the TDR register.
DataOutPorts port _name wtsel means that the output port name of the TDR register is wtsel.
Connection (1:0) memory1/WTSEL; connection (1:0) memory2/WTSEL; connection (1:0) memory3/WTSEL describes memory1, memory2 and memory3 pins WTSEL have a bit width of 2, the TDR register output port wtsel also has a bit width of 2, and the TDR register output port wtsel is connected to three memory pins WTSEL simultaneously, thereby achieving the purpose of combining TDR registers.
As an alternative embodiment, allocating the same register to a target pin located on a different memory of the same type and having a consistent pin bit width and initialization configuration value, includes:
Dividing target pins which are positioned on different memories of the same type and have consistent pin bit widths and initialization configuration values into the same group of target pins;
The same register is allocated for the same set of target pins.
Specifically, the second register allocation manner of the target pins on each memory of the chip is as follows: 1) Dividing target pins which are positioned on different memories of the same type and have consistent pin bit widths and initialization configuration values into the same group of target pins, namely, each target pin in the same group of target pins is respectively positioned on different memories of the same type, and the pin bit widths and the initialization configuration values of all the target pins in the same group of target pins are consistent; 2) The same register is allocated for the same group of target pins, namely, all target pins in the same group of target pins share the same register.
The first register allocation mode and the second register allocation mode of the target pins on each memory of the chip are selected.
As an alternative embodiment, the register allocation method of the memory pin further includes:
And according to the register allocation condition of the target pins on each memory, autonomously generating an RTL file for describing the connection relation between the target pins and the registers of each memory.
Further, considering that the TDR register is written in the RTL design of the chip manually at present, time and labor are wasted, and errors can be possibly introduced due to human participation, the application autonomously generates the RTL file for describing the connection relation between the target pins and the registers of each memory according to the register allocation condition of the target pins on each memory of the chip, thereby being integrated in the whole RTL design of the chip, greatly saving labor cost and reducing error probability.
It should be noted that in integrated circuit designs, RTL is an abstraction level used to describe the operation of synchronous digital circuits. At the RTL level, the chip is made up of a set of registers and logical operations between registers. This is so because most circuits can be seen as storing binary data by registers, completing the processing of the data by logical operations between registers, the flow of the data processing being controlled by a sequential state machine, these processes and controls being described in a hardware description language.
As an alternative embodiment, autonomously generating an RTL file for describing a connection relationship between a target pin and a register of each memory according to a register allocation condition of the target pin on each memory includes:
According to the register allocation situation of the target pins on each memory, automatically generating a configuration file for representing the connection relation between the target pins and the registers of each memory by using an EDA tool;
The configuration file is converted to an ICL file, and the ICL file is converted to an RTL file.
Specifically, the RTL file generation flow of the application is as follows: 1) According to the register allocation situation of the target pins on each memory of the chip, an EDA (Electronics Design Automation, electronic design automation) tool (such as Tessent) is utilized to autonomously generate a configuration file for representing the connection relation between the target pins and the registers of each memory; 2) Automatically converting the configuration file into an ICL (Instrument Connectivity Language, instrument connection language) file recognizable by the ijag (Internal Joint Test Action Group, IEEE1687 standard) network (describing the connection of the ijag network to connect the TDR register into the ijag network); 3) The ICL file is automatically converted into a circuit implementable RTL file.
As an alternative embodiment, the register allocation method of the memory pin further includes:
according to the initialization configuration value of the target pin on each memory, determining the initialization configuration value corresponding to each register connected with each memory;
a PDL file characterizing the initialization configuration values corresponding to each register is autonomously generated for each register to enable configuration of each register based on the PDL file.
Further, according to the initialization configuration values of the target pins on the memories of the chip, the application can also determine the initialization configuration value corresponding to each register connected to the memories of the chip, for example, if the initialization configuration value of the timing adjustment pin WTSEL of one memory is 11, the initialization configuration value corresponding to the register connected to the timing adjustment pin WTSEL of the memory is 11. Then, the present application autonomously generates a PDL (Procedural Description Language, process description language) file (PDL file example describing configuration initialization: write data function→write data function assign initialization configuration value to output terminal of TDR register→write data function call by each TDR register) characterizing the initialization configuration value corresponding to each register for each register of each memory connection of the chip, so as to realize quick configuration of TDR registers based on PDL file.
In addition, the application can also generate an IJTAG network of the circuit containing the target pin connection register of each memory based on the ICL file, and then correspondingly write the initialization configuration value of the PDL file into the register in the IJTAG network so as to realize the initialization configuration of the target pin on each memory in the IJTAG network. Specifically, the configuration procedure of the TDR register may be specifically set as follows: the value to be configured of the pin of the memory connected with the TDR register is scanned into the TDR register through the TDI pin (TDI: test data input pin) of the TAP (TEST ACCESS Port ) controller, and then part of the control end pins of the memory are initialized through the TDR register.
In summary, as shown in fig. 2, the present application provides a method for quickly extracting pins of a memory required to be configured, quickly configuring and connecting TDR registers, and finally integrating into an RTL design, where the steps in fig. 2 may be packaged into a set of relatively complete program to implement, so that when an MBIST test circuit is developed, a designer only needs to run the program to add corresponding TDR registers to pins of all memories required to be configured in the whole chip, and integrate into the RTL design, thereby avoiding repeated manual work, reducing error probability, and improving working efficiency.
In addition, as shown in fig. 3, the MBIST test principle of the memory is:
in fig. 3, SRAM (Static Random-Access Memory) is a Memory under test; an MBIST controller is a controller for controlling the behavior of a memory under test during MBIST testing and includes an FSM (FINITE STATE MACHINE ) and MBIST comparison circuitry (compiler). For memories, the input pins are nothing Address (Address), data (Data), control (Control) pins. In MBIST testing, a selector is added to each input pin of the memory to determine whether it is a functional Logic (Logic) input or an MBIST input, and the selection signal of the selector is controlled by an MBIST controller. The outputs of the memory are respectively to the functional logic and MBIST comparison circuit. The MBIST controller generates the test vector and also generates the expected observed value to be input to the comparator to compare the expected observed value with the real output of the memory, and if the real output of the memory is the same as the expected observed value, the memory is perfect, so that no problem exists.
Referring to fig. 4, fig. 4 is a schematic diagram of a register allocation system for memory pins according to an embodiment of the invention.
The memory pin register allocation system is based on memory built-in self-test, comprising:
The memory classification module 1 is used for classifying all memories on the chip according to the memory types to obtain memories of the same type on the chip;
the pin determining module 2 is used for determining a target pin which needs to be configured by adopting a register on the same type of memory according to the pin initializing requirement of the same type of memory;
The configuration value determining module 3 is configured to determine an initialization configuration value of a target pin on each memory of the same type according to a preset correspondence between memory parameters and pin initialization configuration values of the same type;
The register allocation module 4 is configured to allocate the same register to the target pins that are located in different memories of the same type and have identical pin bit widths and initialization configuration values, so as to complete the register allocation of the target pins on each memory.
As an alternative embodiment, the register allocation system of the memory pin further includes:
and the file generation module is used for autonomously generating an RTL file for describing the connection relation between the target pins and the registers of each memory according to the register allocation situation of the target pins on each memory.
The description of the register allocation system provided by the present application refers to the embodiment of the above register allocation method, and the disclosure is not repeated here.
The application also provides a register allocation device of the memory pin, which is based on the built-in self test of the memory and comprises the following steps:
a memory for storing a computer program;
A processor for implementing the steps of any of the memory pin register allocation methods described above when executing a computer program.
The description of the register allocation apparatus provided by the present application refers to the embodiment of the register allocation method, and the disclosure is not repeated here.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A method for allocating registers of a memory pin based on a built-in self test of a memory, comprising:
classifying all memories on a chip according to the types of the memories to obtain memories of the same type on the chip;
determining a target pin which is required to be configured by a register on the same type of memory according to the pin initialization requirement of the same type of memory;
Determining the initialization configuration value of a target pin on each memory of the same type according to the preset corresponding relation between the memory parameters and the pin initialization configuration values of the same type;
Allocating the same register for target pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values, so as to finish the register allocation of the target pins on each memory;
The presetting process of the corresponding relation between the memory parameter and the pin initialization configuration value under the same type comprises the following steps:
According to the type, depth, bit width and column multiplexing selector and voltage threshold value of each memory, an initialization configuration value is defined for each pin needing to be configured by a register on each memory, so as to obtain the corresponding relation between the memory parameters and the pin initialization configuration values under the same type.
2. The method of memory pin register allocation according to claim 1, wherein allocating the same register to a target pin which is located on a different memory of the same type and whose pin bit width and initialization configuration value are identical, comprises:
Distributing registers for target pins on each memory one by one;
and merging the registers allocated by the target pins which are positioned on different memories of the same type and consistent in pin bit width and initialization configuration values.
3. The method of memory pin register allocation according to claim 1, wherein allocating the same register to a target pin which is located on a different memory of the same type and whose pin bit width and initialization configuration value are identical, comprises:
Dividing target pins which are positioned on different memories of the same type and have consistent pin bit widths and initialization configuration values into the same group of target pins;
and allocating the same register for the same group of target pins.
4. A memory pin register allocation method according to any one of claims 1-3, further comprising:
And according to the register allocation condition of the target pins on each memory, automatically generating an RTL file for describing the connection relation between the target pins and the registers of each memory.
5. The method for allocating registers to pins of a memory according to claim 4, wherein autonomously generating an RTL file describing a connection relationship between the pins of the memory and the registers according to the allocation of registers to the pins of the memory comprises:
according to the register allocation situation of the target pins on each memory, an EDA tool is utilized to autonomously generate a configuration file for representing the connection relation between the target pins of each memory and the registers;
And converting the configuration file into an ICL file, and converting the ICL file into an RTL file.
6. The memory pin register allocation method of claim 4, wherein the memory pin register allocation method further comprises:
According to the initialization configuration values of the target pins on the memories, determining the initialization configuration values corresponding to each register connected with the memories;
and autonomously generating a PDL file representing the initialization configuration value corresponding to each register for each register so as to realize the configuration of each register based on the PDL file.
7. A memory pin based register allocation system based on memory built-in self-test, comprising:
The memory classification module is used for classifying all memories on a chip according to the memory types to obtain memories of the same type on the chip;
the pin determining module is used for determining a target pin which is required to be configured by a register on the memory of the same type according to the pin initializing requirement of the memory of the same type;
the configuration value determining module is used for determining the initialization configuration value of the target pin on each memory of the same type according to the corresponding relation between the preset memory parameters of the same type and the pin initialization configuration values;
the register allocation module is used for allocating the same register to the target pins which are positioned on different memories of the same type and have consistent pin bit width and initialization configuration values so as to finish the register allocation of the target pins on each memory;
The presetting process of the corresponding relation between the memory parameter and the pin initialization configuration value under the same type comprises the following steps:
According to the type, depth, bit width and column multiplexing selector and voltage threshold value of each memory, an initialization configuration value is defined for each pin needing to be configured by a register on each memory, so as to obtain the corresponding relation between the memory parameters and the pin initialization configuration values under the same type.
8. The memory pin register allocation system of claim 7, wherein said memory pin register allocation system further comprises:
And the file generation module is used for autonomously generating an RTL file for describing the connection relation between the target pins and the registers of the memories according to the register allocation situation of the target pins on the memories.
9. A memory pin based register allocation apparatus based on memory built-in self-test, comprising:
a memory for storing a computer program;
A processor for implementing the steps of the register allocation method of a memory pin according to any of claims 1-6 when executing said computer program.
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