CN113964120B - A power semiconductor device and a method for manufacturing the same - Google Patents

Abstract

The present invention discloses a power semiconductor device and a manufacturing method thereof. The device comprises a silicon carbide N-type substrate, an N-type epitaxial layer is provided on the silicon carbide N-type substrate, a P-base region is provided on the N-type epitaxial layer, an N+ source region and a P+ source region are formed in the P-base region to form an intermediate device, an insulating dielectric material layer and a gate dielectric material layer are deposited on the surface of the intermediate device, polysilicon is deposited on the insulating dielectric material layer and the gate dielectric material layer, an ohmic contact layer is formed on the surface of the N+ source region and the P+ source region, a Schottky contact layer is formed on the surface of the N-type epitaxial layer between the P+ source region and the P+ source region, a source electrode is provided on the ohmic contact layer and the Schottky contact layer, a gate electrode is provided on the polysilicon, and a drain electrode is provided on the back of the silicon carbide N-type substrate. The present invention has the advantages of reducing gate-drain charge, improving chip utilization, reducing anti-parallel diode loss, and improving the surge capacity of the anti-parallel diode.

Description

A power semiconductor device and a method for manufacturing the same

Technical Field

The present invention mainly relates to the field of semiconductor technology, and in particular to a power semiconductor device and a manufacturing method thereof.

Background Art

In switching applications, power MOSFET devices must overcome gate charge to regulate the transistor to a specific voltage, and the switching speed of the transistor is significantly reduced at a larger gate charge. In addition, the transistor is affected by higher gate charge and the failure rate increases. The gate-drain charge is the main part of the gate charge, and due to the Miller effect, applying the switching voltage to the gate amplifies the gate-drain capacitance. Therefore, it is desirable to minimize the gate-drain capacitance to reduce the gate charge and improve the switching speed, efficiency and failure rate of the transistor.

In power electronic systems, power MOSFET devices usually need to be used with free wheeling diodes (FWD) to ensure the safety and stability of the system. Therefore, in traditional power MOSFET modules or single-tube devices, FWD is usually connected in reverse parallel with it. This solution not only increases the number of devices, the size of the module and the production cost, but also the increase in the number of solder joints during the packaging process will affect the reliability of the device. The parasitic effects generated by the metal connection also affect the overall performance of the device.

The device cell structure currently used in commercial products of SiC planar gate MOSFET is shown in Figure 1. Low channel mobility is the key factor for the high on-resistance of SiC planar gate MOSFET. At the same time, SiC can only be implanted by ion implantation. The N+ source region and P-type well PW of planar gate MOSFET are registered by two layers of photolithography. Due to the easy misalignment, the overlay deviation will cause the channel length of the two half cells (as shown in 31 and 32 in Figure 1) to be asymmetric, resulting in the on-current of the device selecting the shorter channel to flow to the drain, and the half cell with the longer channel is not used.

In summary, current power MOSFET devices have defects such as large gate-drain charge, low silicon carbide chip utilization, and large freewheeling diode losses.

Summary of the invention

In view of the problems existing in the prior art, the present invention provides a power semiconductor device and a manufacturing method thereof which can reduce gate-drain charge, improve chip utilization, reduce anti-parallel diode loss, and improve the surge capability of the anti-parallel diode.

In order to solve the above technical problems, the technical solution proposed by the present invention is:

A power semiconductor device comprises a silicon carbide N-type substrate, an N-type epitaxial layer is provided on the silicon carbide N-type substrate, a P-base region is provided on the N-type epitaxial layer, an N+ source region and a P+ source region are formed in the P-base region to form an intermediate device, an insulating dielectric material layer and a gate dielectric material layer are deposited on the surface of the intermediate device, polysilicon is deposited on the insulating dielectric material layer and the gate dielectric material layer, an ohmic contact layer is formed on the surface of the N+ source region and the P+ source region, a Schottky contact layer is formed on the surface of the N-type epitaxial layer between the P+ source region and the P+ source region, a source electrode is provided on the ohmic contact layer and the Schottky contact layer, a gate electrode is provided on the polysilicon, and a drain electrode is provided on the back side of the silicon carbide N-type substrate.

As a further improvement of the above technical solution:

The N-type epitaxial layer, part of the P-base region, the ohmic contact layer, and the Schottky contact layer form a JBS or an MPS.

The part of the P base region, the P+ source region, the insulating dielectric material layer and the polysilicon form a P-type MOS capacitor.

The silicon carbide N-type substrate, the N-type epitaxial layer, the gate dielectric material layer and the polysilicon form an N-type MOS capacitor.

The P-type MOS capacitor and the N-type MOS capacitor are connected in series.

The area of the polysilicon may vary.

The present invention also discloses a method for manufacturing the power semiconductor device as described above, comprising the steps of:

Step 1: Using an epitaxial process, an N-type epitaxial layer is formed on a silicon carbide N-type substrate;

Step 2: Using photolithography and ion implantation processes, a P base region is formed above the N-type epitaxial layer, an N+ source region and a P+ source region are formed in the P base region, and impurities in the above implanted regions are activated by high temperature annealing;

Step 3: Using deposition, photolithography and etching processes, a layer of insulating dielectric material is deposited on the surface of the device, and the excess insulating dielectric material layer is removed by etching;

Step 4: Using a thermal oxidation process, a gate dielectric material layer is formed on the surface of the device;

Step 5: Using deposition, photolithography and etching processes, a layer of polysilicon is deposited on the surface of the device, and excess polysilicon material is removed by etching;

Step 6: Using deposition, photolithography and etching processes, a layer of insulating dielectric material is deposited on the surface of the device, and excess dielectric material is removed by etching;

Step 7: Using deposition, alloying, photolithography and etching processes to form an ohmic contact layer on the device surface;

Step 8: Using deposition, alloying, photolithography and etching processes to form a Schottky contact layer on the device surface;

Step 9: Use deposition, photolithography and etching processes to form the source and gate respectively;

Step 10: Use laser annealing, metal thickening and deposition processes to form the drain on the back of the device, and finally produce a silicon carbide MOSFET device.

As a further improvement of the above technical solution:

In step 1, the doping concentration of the N-type epitaxial layer is 5e14-5e16 cm ^-3 .

In step 2, the junction depth of the P base region is 0.6-1.5 um, and the peak doping concentration is 1e18-5e19 cm ^-3 .

In step 3, the thickness of the insulating dielectric material layer is 0.05-2 μm.

Compared with the prior art, the advantages of the present invention are:

In the power MOSFET structure of the present invention, half of the MOSFET cell is used to integrate the MPS, thereby improving chip utilization, reducing the loss of the external anti-parallel diode and the device volume, avoiding the bipolar degradation effect of the MOSFET parasitic body diode, ensuring that the body diode has the same level of withstand voltage as the MOSFET, avoiding the turn-on loss of the PiN diode, and also improving the surge capacity of the anti-parallel diode; wherein, a part of the integrated MPS is used to form a PMOS capacitor, and is connected in series with the NMOS gate-drain capacitor of the MOSFET. It can be known from the C-V curve theory that when the gate-source voltage of the MOSFET is close to the platform voltage, the depletion region of the N-type semiconductor drift region of the NMOS capacitor is shrinking, and its capacitance is increased, while the depletion region of the P-type region of the PMOS capacitor is expanding, and its capacitance is reduced. The two capacitors are connected in series, and the total capacitance depends on the smaller capacitor, thereby reducing the gate-drain charge; at the same time, the insulating dielectric material layer of the PMOS capacitor is thicker than the gate dielectric material layer of the NMOS gate-drain capacitor, further reducing the gate-drain charge.

The present invention has the following three advantages by improving the structural design of the power MOSFET device: 1. reducing gate-drain charge; 2. improving chip utilization; 3. integrating a hybrid PiN Schottky diode, reducing the loss of the anti-parallel diode, improving the surge capability of the anti-parallel diode, and enhancing its robustness.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic cross-sectional view of a conventional power MOSFET device structure.

FIG. 2 is a schematic cross-sectional view of a power MOSFET device structure in Embodiment 1 of the present invention.

FIG3 is a cross-sectional view of a power MOSFET device according to an embodiment of the present invention after step 2.

FIG. 4 is a schematic cross-sectional view of a power MOSFET device after step 3 in the first embodiment of the present invention.

FIG5 is a schematic cross-sectional view of a power MOSFET device after step 5 in the first embodiment of the present invention.

FIG6 is a schematic cross-sectional view of the power MOSFET device after step 7 in the first embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a power MOSFET device after step 8 in the first embodiment of the present invention.

FIG8 is a schematic cross-sectional view of the power MOSFET device structure in the second embodiment of the present invention.

Legend: 1. N-type substrate; 2. N-type epitaxial layer; 3. P base region; 4. N+ source region; 5. P+ source region; 6. Insulating dielectric material layer; 7. Gate dielectric material layer; 8. Polysilicon; 9. Interlayer dielectric layer; 10. Ohmic contact layer; 11. Schottky base contact layer; 12. Source; 13. Gate; 14. Drain; 100. MPS; 101. PMOS capacitor; 102. Gate-drain capacitor.

DETAILED DESCRIPTION

The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

As shown in FIG2 , the power semiconductor device of the present embodiment comprises a silicon carbide N-type substrate 1, an N-type epitaxial layer 2 is provided on the silicon carbide N-type substrate 1, a P-base region 3 is provided on the N-type epitaxial layer 2, specifically three locations on the left, middle and right, an N+ source region 4 and a P+ source region 5 are formed in the P-base region 3 (wherein the N+ source region 4 and the P+ source region 5 are formed in the P-base regions 3 on both sides, and the P+ source region 5 is formed in the middle P-base region 3) to form an intermediate device; an insulating dielectric material layer 6 and a gate dielectric material layer 7 are deposited on the surface of the intermediate device (wherein the insulating dielectric layer 6 is in two locations on the left and the left location is located in the area where the P+ source region 5 is not formed in the middle P-base region 3; wherein the gate dielectric material layer 7 is in two locations on the left and the right, wherein the left location is located on the left P-base region 3, the corresponding N+ source region 4 and the N-type epitaxial layer 2, and the right location is located on the right P-base region 3, the corresponding N+ On the N+ source region 4 and the N-type epitaxial layer 2), polysilicon 8 (with a variable area) is deposited on the insulating dielectric material layer 6 and the gate dielectric material layer 7, an ohmic contact layer 10 is formed between the N+ source region 4 and the P+ source region 5 (specifically, three locations, one on the left is on the N+ source region 4 and the P+ source region 5 of the left P base region 3, one in the middle is on the P+ source region 5 of the middle P base region 3, and one on the right is on the N+ source region 4 and the P+ source region 5 of the right P base region 3), a Schottky contact layer 11 is formed between the P+ source region 5 and the P+ source region 5 (located between the middle ohmic contact layer 10 and the right ohmic contact layer 10), a source 12 is provided on the ohmic contact layer 10 and the Schottky contact layer 11 (specifically, two locations, as shown in FIG. 2), a gate 13 is provided on the polysilicon 8, and a drain 14 is provided on the back side of the silicon carbide N-type substrate 1.

In the power MOSFET structure of the present invention, half of the MOSFET cell is used to integrate MPS100 (composed of a regional silicon carbide N-type substrate 1, an N-type epitaxial layer 2, a P base region 3, a P+ source region 5, an ohmic contact layer 10, a Schottky contact layer 11, a source 12 and a drain 14), thereby improving chip utilization, reducing the loss and device volume of the external anti-parallel diode, avoiding the bipolar degradation effect of the MOSFET parasitic body diode, ensuring that the body diode and the MOSFET have the same level of withstand voltage, avoiding the turn-on loss of the PiN diode, and also improving the surge capacity of the anti-parallel diode; wherein, a PMOS capacitor 101 (composed of a regional P base region 3, a P+ source region 5, an insulating dielectric material layer 6, a polysilicon 8, The ohmic contact layer 10 and the source 12 are formed), and are connected in series with the NMOS gate-drain capacitor 102 of the MOSFET (composed of a regional silicon carbide N-type substrate 1, an N-type epitaxial layer 2, a gate dielectric material layer 7, polysilicon 8 and a drain 14) through a metal 13. From the C-V curve theory, it can be seen that when the gate-source voltage of the MOSFET is close to the platform voltage, the depletion region of the N-type semiconductor drift region of the NMOS capacitor is shrinking, and its capacitance increases, while the depletion region of the P-type region of the PMOS capacitor is expanding, and its capacitance decreases. The two capacitors (PMOS capacitor and NMOS capacitor) are connected in series, and the total capacitance depends on the smaller capacitor, thereby reducing the gate-drain charge. At the same time, the insulating dielectric material layer 6 of the PMOS capacitor is thicker than the gate dielectric material layer 7 of the NMOS gate-drain capacitor, further reducing the gate-drain charge.

The present invention also discloses a method for manufacturing the power semiconductor device as described above, comprising the steps of:

Step 1: using an epitaxial process to form an N-type epitaxial layer 2 on a silicon carbide N-type substrate 1;

Step 2: Using photolithography and ion implantation processes, a P base region 3 is formed on the N-type epitaxial layer 2, an N+ source region 4 and a P+ source region 5 are formed in the P base region 3, and impurities in the above implanted regions are activated by high temperature annealing;

Step 3: using deposition, photolithography and etching processes, deposit a layer of insulating dielectric material 6 on the surface of the device, and remove the excess insulating dielectric material layer by etching;

Step 4: using a thermal oxidation process to form a gate dielectric material layer 7 on the surface of the device;

Step 5: using deposition, photolithography and etching processes, deposit a layer of polysilicon 8 on the surface of the device, and remove excess polysilicon material by etching;

Step 6: using deposition, photolithography and etching processes, deposit an interlayer dielectric layer 9 (insulating dielectric material) on the surface of the device, and remove excess insulating dielectric material by etching;

Step 7: Using deposition, alloying, photolithography and etching processes, an ohmic contact layer 10 is formed on the surface of the device;

Step 8: Using deposition, alloying, photolithography and etching processes to form a Schottky contact layer 11 on the surface of the device;

Step 9: using deposition, photolithography and etching processes to form the source 12 and the gate 13 respectively;

Step 10: Use laser annealing, metal thickening and deposition processes to form the drain 14 on the back of the device, and finally obtain a silicon carbide MOSFET device.

The present invention has the following three advantages by improving the structural design of the power MOSFET device: 1. reducing gate-drain charge; 2. improving chip utilization; 3. integrating a Merged PiN Schottky (MPS) diode, reducing the loss of the anti-parallel diode and improving the surge capacity of the anti-parallel diode.

The present invention is further described below in conjunction with two specific embodiments:

Embodiment 1:

Step 1: using an epitaxial process to form an N-type epitaxial layer 2 on a silicon carbide N-type substrate 1, wherein the resistivity of the N-type substrate 1 is 0.01-0.03Ω.cm, the thickness is 200-400μm, and the doping concentration of the N-type epitaxial layer 2 is 5e14-5e16cm ^-3 ;

Step 2: using photolithography and ion implantation processes, a P base region 3 is formed on the N-type epitaxial layer 2, wherein the junction depth of the P base region 3 is 0.6-1.5um, and the peak doping concentration is 1e18-5e19cm ^-3 , an N+ source region 4 is formed in the P base region 3, wherein the junction depth is 0.2-0.5um, and the peak doping concentration is 5e18-5e20cm ^-3 , a P+ source region 5 is formed in the P base region 3, wherein the junction depth is 0.2-0.5um, and the doping concentration is 5e18-5e20cm ^-3 , and the impurities in the above implanted regions are activated by high temperature annealing, as shown in FIG3 ;

Step 3: using deposition, photolithography and etching processes, deposit a layer of insulating dielectric material 6 on the device surface with a thickness of 0.05 to 2 μm, and remove excess dielectric material 6 by etching, as shown in FIG4 ;

Step 4: Using a thermal oxidation process, a layer of gate dielectric material 7 is formed on the surface of the device;

Step 5: using deposition, photolithography and etching processes, deposit a layer of polysilicon 8 on the surface of the device, and remove excess polysilicon material by etching, as shown in FIG5 ;

Step 6: using deposition, photolithography and etching processes, deposit an interlayer dielectric layer 9 (such as insulating dielectric material) on the surface of the device, and remove excess dielectric material by etching;

Step 7: Using deposition, alloying, photolithography and etching processes, an ohmic contact 10 is formed on the surface of the device, as shown in FIG6 ;

Step 8: Using deposition, alloying, photolithography and etching processes, a Schottky contact 11 is formed on the surface of the device, as shown in FIG7 ;

Step 9: Using deposition, photolithography and etching processes, a source electrode 12 and a gate electrode 13 are formed respectively, and the gate metal is shown for clarity of description;

Step 10: Laser annealing, metal thickening and deposition processes are used to form the drain 14 on the back of the device and the protective glue on the front, and finally a silicon carbide MOSFET device is obtained, as shown in FIG2 .

The dimensions in the figure (including lateral dimensions, layout dimensions, dielectric thickness, metal thickness, junction depth, etc.) do not represent actual dimensions, but are only used as examples of methods for forming structures, wherein the devices include but are not limited to planar MOSFET, planar IGBT, MPS, JBS; semiconductor materials include but are not limited to SiC, such as Si, etc.

Embodiment 2:

The same as the first embodiment is that the MPS is integrated by using the MOSFET half cell (the dotted box 200 in FIG8 ); the difference from the first embodiment is that the size of the working gate is reduced by removing a piece of polysilicon 8 (there is no polysilicon 8 in the dotted box 201 in FIG8 ), thereby reducing the gate charge, and the MPS part does not form a PMOS capacitor, as shown in FIG8 .

The above are only preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (6)

1. A power semiconductor device, characterized in that it comprises a silicon carbide N-type substrate (1), an N-type epitaxial layer (2) is provided on the silicon carbide N-type substrate (1), a P-base region (3) is provided on the N-type epitaxial layer (2), an N+ source region (4) and a P+ source region (5) are formed in the P-base region (3) to form an intermediate device, an insulating dielectric material layer (6) and a gate dielectric material layer (7) are deposited on the surface of the intermediate device, and the insulating dielectric material layer (6) and the gate dielectric material layer (7) having polysilicon (8) deposited thereon, an ohmic contact layer (10) formed on the surfaces of the N+ source region (4) and the P+ source region (5), a Schottky contact layer (11) formed on the surface of the N-type epitaxial layer between the P+ source region (5) and the P+ source region (5), a source electrode (12) being provided on the ohmic contact layer (10) and the Schottky contact layer (11), a gate electrode (13) being provided on the polysilicon (8), and a drain electrode (14) being provided on the back side of the silicon carbide N-type substrate (1); The N-type epitaxial layer (2), part of the P-base region (3), the ohmic contact layer (10), and the Schottky contact layer (11) form a JBS or an MPS; A portion of the P base region (3), the P+ source region (5), the insulating dielectric material layer (6) and the polysilicon (8) form a P-type MOS capacitor; The silicon carbide N-type substrate (1), the N-type epitaxial layer (2), the gate dielectric material layer (7) and the polysilicon (8) form an N-type MOS capacitor; The P-type MOS capacitor and the N-type MOS capacitor are connected in series. 2. The power semiconductor device according to claim 1, characterized in that the area of the polysilicon (8) is variable. 3. A method for manufacturing a power semiconductor device according to any one of claims 1 to 2, characterized in that it comprises the steps of: Step 1: using an epitaxial process to form an N-type epitaxial layer (2) on a silicon carbide N-type substrate (1); Step 2: using photolithography and ion implantation processes to form a P base region (3) on the N-type epitaxial layer (2), forming an N+ source region (4) and a P+ source region (5) in the P base region (3), and activating impurities in the implanted region by high temperature annealing; Step 3: using deposition, photolithography and etching processes to deposit a layer of insulating dielectric material (6) on the surface of the device, and etching away excess insulating dielectric material layer; Step 4: using a thermal oxidation process to form a gate dielectric material layer (7) on the surface of the device; Step 5: using deposition, photolithography and etching processes to deposit a layer of polysilicon (8) on the surface of the device, and etching to remove excess polysilicon material; Step 6: using deposition, photolithography and etching processes to deposit a layer of insulating dielectric material (9) on the surface of the device, and etching away excess dielectric material; Step 7: Using deposition, alloying, photolithography and etching processes to form an ohmic contact layer (10) on the device surface; Step 8: Using deposition, alloying, photolithography and etching processes to form a Schottky contact layer (11) on the device surface; Step 9: using deposition, photolithography and etching processes to form a source electrode (12) and a gate electrode (13) respectively; Step 10: Using laser annealing, metal thickening and deposition processes, a drain (14) is formed on the back side of the device, and finally a silicon carbide MOSFET device is obtained. 4. The method for manufacturing a power semiconductor device according to claim 3, characterized in that, in step 1, the doping concentration of the N-type epitaxial layer (2) is 5e14-5e16 cm ^-3 . 5. The method for manufacturing a power semiconductor device according to claim 4, characterized in that, in step 2, the junction depth of the P base region (3) is 0.6-1.5 um, and the peak doping concentration is 1e18-5e19 cm ^-3 . 6. The method for manufacturing a power semiconductor device according to claim 3, characterized in that, in step 3, the insulating dielectric material layer (6) has a thickness of 0.05-2 μm.