CN113964141A - Array substrate, method for making the same, and reflective liquid crystal display panel - Google Patents
Array substrate, method for making the same, and reflective liquid crystal display panel Download PDFInfo
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- CN113964141A CN113964141A CN202111302574.0A CN202111302574A CN113964141A CN 113964141 A CN113964141 A CN 113964141A CN 202111302574 A CN202111302574 A CN 202111302574A CN 113964141 A CN113964141 A CN 113964141A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/441—Interconnections, e.g. scanning lines
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/01—Manufacture or treatment
- H10D86/021—Manufacture or treatment of multiple TFTs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Abstract
The invention discloses an array substrate, a manufacturing method thereof and a reflection-type liquid crystal display panel, wherein the array substrate comprises: a substrate; the source electrode and the data line are arranged on the substrate, and the source electrode is electrically connected with the data line; an active layer disposed on the source electrode and the substrate; a drain electrode on the active layer; the orthographic projection of the drain electrode on the substrate is at least partially overlapped with the orthographic projection of the source electrode on the substrate, and the active layer is positioned between the drain electrode and the source electrode and is electrically connected with the drain electrode and the source electrode; a first insulating layer covering the drain electrode and the substrate; the grid electrode and the scanning line are arranged on the first insulating layer, and the grid electrode is electrically connected with the scanning line; a second insulating layer covering the gate and the first insulating layer; a planarization layer covering the second insulating layer; a reflective electrode covering the flat layer and electrically connected with the drain electrode; the orthographic projection of the drain electrode, the active layer and the source electrode on the substrate is positioned in the orthographic projection of the reflecting electrode on the substrate. The array substrate can effectively obtain ultrahigh resolution and ultrahigh aperture ratio.
Description
Technical Field
The invention relates to the technical field of display equipment, in particular to an array substrate, a manufacturing method thereof and a reflection type liquid crystal display panel.
Background
At present, in a conventional reflective display, the improvement of resolution has a difficulty of material limitation, and particularly in a small-sized reflective display, due to the insufficient resolution, the display effect is greatly reduced, and even some required graphics cannot be displayed. In addition, the TFT with the conventional BCE channel (back channel) structure is covered with a metal layer, which makes the semiconductor layer of the TFT susceptible to deteriorate the TFT characteristics. Therefore, the TFT on the conventional reflective display is not covered with the reflective electrode. Therefore, when natural light is irradiated to the TFT region, reflection of light is not achieved, and the aperture ratio is reduced.
Disclosure of Invention
In view of this, the present invention provides an array substrate, which can effectively obtain an ultrahigh resolution and an ultrahigh aperture ratio.
An array substrate, comprising:
a substrate;
the source electrode and the data line are arranged on the substrate, and the source electrode is electrically connected with the data line;
an active layer disposed on the source electrode and the substrate;
a drain electrode on the active layer;
the orthographic projection of the drain electrode on the substrate is at least partially overlapped with the orthographic projection of the source electrode on the substrate, and the active layer is positioned between the drain electrode and the source electrode and is electrically connected with the drain electrode and the source electrode;
a first insulating layer covering the drain electrode and the substrate;
the grid electrode and the scanning line are arranged on the first insulating layer, and the grid electrode is electrically connected with the scanning line;
a second insulating layer covering the gate and the first insulating layer;
a planarization layer covering the second insulating layer;
a reflective electrode covering the flat layer and electrically connected with the drain electrode;
the orthographic projection of the drain electrode, the active layer and the source electrode on the substrate is positioned in the orthographic projection of the reflecting electrode on the substrate.
In an embodiment of the invention, a surface of the flat layer, which is matched with the reflective electrode, is provided with a first rough structure.
In an embodiment of the invention, a second rough structure is disposed on a side of the reflective electrode facing away from the planarization layer.
In an embodiment of the invention, the second roughness structure is a plurality of protrusions, and the height of each protrusion is
In an embodiment of the invention, the material of the reflective electrode is molybdenum or aluminum.
The invention also provides a reflection type liquid crystal display panel, which comprises the array substrate, and the reflection type liquid crystal display panel also comprises a color film substrate opposite to the array substrate, wherein the color film substrate comprises a substrate, and one side of the substrate facing the array substrate is covered with a common electrode.
The invention also provides a manufacturing method of the array substrate, which comprises the following steps:
providing a substrate;
forming a first metal layer on a substrate, and etching and patterning the first metal layer to form a source electrode and a data line on the first metal layer, wherein the source electrode is electrically connected with the data line;
forming an oxide semiconductor layer on the source electrode and the substrate, and etching and patterning the oxide semiconductor layer to form an active layer on the oxide semiconductor layer;
forming a second metal layer on the active layer, and etching and patterning the second metal layer to form a drain electrode on the second metal layer;
the orthographic projection of the drain electrode on the substrate is at least partially overlapped with the orthographic projection of the source electrode on the substrate, and the active layer is positioned between the drain electrode and the source electrode and is electrically connected with the drain electrode and the source electrode;
forming a first insulating layer covering the source electrode, the active layer and the drain electrode on the substrate;
forming a third metal layer on the first insulating layer, and etching and patterning the third metal layer to form a grid electrode and a scanning line which are electrically connected;
forming a second insulating layer covering the gate electrode on the first insulating layer;
forming a planarization layer on the second insulating layer;
forming a fourth metal layer on the flat layer, and etching and patterning the fourth metal layer to form a reflecting electrode on the fourth metal layer, wherein the reflecting electrode is electrically connected with the drain electrode;
the orthographic projection of the drain electrode, the active layer and the source electrode on the substrate is positioned in the orthographic projection of the reflecting electrode on the substrate.
In an embodiment of the present invention, the manufacturing method further includes: and when the flat layer is formed on the second insulating layer, a first rough structure is formed on the surface of the flat layer matched with the reflecting electrode.
In an embodiment of the present invention, the manufacturing method further includes: and etching and patterning the fourth metal layer to form a second rough structure on one side of the reflecting electrode, which faces away from the flat layer, when the reflecting electrode is formed on the fourth metal layer.
In an embodiment of the invention, a dry etching process is used when the second metal layer is etched and patterned to form the drain electrode.
The array substrate of the invention is designed to be a vertical channel structure (namely, the source electrode and the drain electrode are positioned on the same layer and are horizontally separated from each other) by designing the horizontal channel structure (namely, the source electrode and the drain electrode are positioned on the upper and lower different layers and are at least partially overlapped, and the active layer is clamped between the source electrode and the drain electrode) of the TFT (thin Film transistor). Therefore, the occupied area of the TFT on the array substrate is reduced, the channel length of a vertical channel structure of the TFT is reduced, the conductivity of the TFT is improved, and power consumption is reduced. The array substrate effectively avoids the problem that the top end of a traditional BCE (back channel etch) type channel cannot cover metal by utilizing the self-shielding effect of a vertical channel structure, so that the reflecting electrode can cover the upper area (namely a TFT (thin film transistor) area) of a source electrode, an active layer and a drain electrode, and the TFT area can also be used as a reflecting area. Meanwhile, the aspect ratio of the TFT vertical channel structure can be adjusted by adjusting the thickness of the active layer and the shape curve of the edge of the active layer. By strictly calculating, taking the S0291 AA area (effective display area) 29056 × 66896um as an example, the resolution can be increased from 128 × 296 to 1937 × 4459 or even higher by applying this design.
Drawings
FIG. 1 is a schematic cross-sectional view illustrating a method for fabricating an array substrate according to the present invention;
FIG. 2 is a schematic view of a partial plan structure of an array substrate according to the present invention;
FIG. 3 is a schematic cross-sectional view of the array substrate shown in FIG. 2 along the A-A direction;
FIG. 4 is a schematic view of a partial plan structure of an array substrate according to the present invention;
FIG. 5 is a schematic cross-sectional view of the array substrate shown in FIG. 4 along the direction B-B;
FIG. 6 is a schematic cross-sectional view illustrating a method for fabricating an array substrate according to the present invention;
FIG. 7 is a schematic view of a partial plan structure of an array substrate according to the present invention;
FIG. 8 is a schematic cross-sectional view of the array substrate shown in FIG. 7 along the direction C-C;
fig. 9 to 10 are schematic cross-sectional views illustrating a manufacturing method of an array substrate according to the present invention;
FIG. 11 is a schematic view of a partial plan structure of an array substrate according to the present invention;
FIG. 12 is a schematic cross-sectional view of the array substrate shown in FIG. 11 taken along the direction D-D;
fig. 13 is a schematic cross-sectional view of a reflective liquid crystal display panel according to the present invention.
Detailed Description
In order to facilitate understanding of those skilled in the art, the present application provides a specific implementation process of the technical solution provided by the present application through the following embodiments.
Referring to fig. 1 to 13, the present invention provides a method for manufacturing an array substrate, including:
as shown in fig. 1, a substrate 11 is provided, wherein the substrate 11 may be made of glass, quartz, acrylic or polycarbonate.
As shown in fig. 1 and 2, a first metal layer is formed on a substrate 11, and the first metal layer is etched and patterned, so that a source electrode 12a and a data line 12 are formed in the first metal layer, wherein the source electrode 12a and the data line 12 are both formed by the first metal layer through a one-step patterning process, and the source electrode 12a is electrically connected to the data line 12, or the source electrode 12a is a portion of the data line 12. In this embodiment, the first metal layer may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo).
As shown in fig. 1 to 3, an oxide semiconductor layer covering the source electrode 12a and the data line 12 is formed on the substrate 11, and the oxide semiconductor layer is etched and patterned so that the oxide semiconductor layer forms an active layer 13, and the active layer 13 at least partially overlaps the source electrode 12 a. The oxide semiconductor layer is Indium Gallium Zinc Oxide (IGZO), and the amorphous oxide IGZO is used as a material of the semiconductor layer, so that the problem of overheating of transistor leakage current caused by the adoption of traditional silicon oxide can be effectively reduced. In the present embodiment, the active layer 13 includes a first connection portion 131 and a second connection portion 132 connected to the first connection portion 131, the first connection portion 131 is located above the source 12a and overlaps the source 12a, and an orthogonal projection of the first connection portion 131 on the substrate 11 is located within an orthogonal projection of the source 12a on the substrate 11; the second connection portion 132 is located on the substrate 11 and is arranged side by side with the source electrode 12 a.
As shown in fig. 4 and 5, a second metal layer covering the active layer 13 is formed on the substrate 11, and the second metal layer is patterned by etching, so that the second metal layer forms the drain electrode 14, and the drain electrode 14 is located above the active layer 13 and at least partially overlaps or completely overlaps the active layer 13, and in the present embodiment, the drain electrode 14 completely overlaps the active layer 13, but is not limited thereto. Wherein, the second metal layer can be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al). In addition, when the drain electrode 14 is formed by etching and patterning the second metal layer, the active layer 13 may be prevented from being corroded by using a dry etching process.
As shown in fig. 6, a first insulating layer 15 covering the source electrode 12a, the data line 12, the active layer 13, and the drain electrode 14 is formed on the substrate 11, and the first insulating layer 15 is, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
As shown in fig. 7 and 8, a third metal layer is formed on the first insulating layer 15, and the third metal layer is etched and patterned, so that the third metal layer forms a gate electrode 16a and a scan line 16, wherein both the gate electrode 16a and the scan line 16 are formed by the third metal layer through a one-step patterning process, the gate electrode 16a is electrically connected with the scan line 16, or the gate electrode 16a is a part of the scan line 16. In this embodiment, the third metal layer may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al).
As shown in fig. 9, a second insulating layer 17 covering the gate electrode 16a and the scan line 16 is formed on the first insulating layer 15, and the second insulating layer 17 is, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
As shown in fig. 10, a planarization layer 18 is formed on the second insulating layer 17, and a via hole 101 penetrating the planarization layer 18, the second insulating layer 17, and the first insulating layer 15 is formed at a position corresponding to the drain electrode 14, so that the drain electrode 14 is exposed through the via hole 101.
As shown in fig. 11 to 12, a fourth metal layer is formed on the planarization layer 18, and the fourth metal layer is patterned by etching, so that the fourth metal layer forms a reflective electrode 19, and the reflective electrode 19 fills the via hole 101 and is electrically connected to the drain electrode 14. Wherein, the orthographic projection of the drain electrode 14, the active layer 13 and the source electrode 12a on the substrate 11 is positioned in the orthographic projection of the reflective electrode 19 on the substrate 11. In the present embodiment, the material of the reflective electrode 19 is an inert and highly reflective metal, such as molybdenum or aluminum.
Further, when the planarization layer 18 is formed on the second insulating layer 17, the first roughness 181 is formed on the surface of the planarization layer 18 that cooperates with the reflective electrode 19 at the same time. In this embodiment, an imprinting process may be used to form the rugged first rough structure 181 on the outer surface of the planarization layer 18, specifically, by designing an optimal imprinting pattern, and imprinting the pattern with a corresponding material of the planarization layer 18 (the material of the planarization layer 18 may use a dedicated imprinting photoresist) before uncured, and curing the photoresist after imprinting, thereby forming the first rough structure 181. Due to the existence of the first rough structure 181, after the fourth metal layer is formed on the outer surface of the planarization layer 18 having the first rough structure 181, the second rough structure 191 is correspondingly formed on the outer surface of the fourth metal layer on the side opposite to the planarization layer 18, and then the fourth metal layer is etched and patterned to form the reflective electrode 19 having the second rough structure 191, so as to achieve the effect of diffuse reflection.
The present invention also provides an array substrate, including:
as shown in fig. 1, a substrate 11, wherein the substrate 11 may be made of glass, quartz, acrylic or polycarbonate.
As shown in fig. 1 and 2, a source 12a and a data line 12 are disposed on a substrate 11, and the source 12a is electrically connected to the data line 12, wherein the source 12a and the data line 12 are both formed by a single patterning process, or the source 12a is a portion of the data line 12, and in this embodiment, the source 12a and the data line 12 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo).
As shown in fig. 1 to 3, the active layer 13 is disposed on the source electrode 12a and the substrate 11, and the active layer 13 at least partially overlaps the source electrode 12 a. The active layer 13 is Indium Gallium Zinc Oxide (IGZO), and the amorphous oxide IGZO is used as a material of the semiconductor layer, so that the problem of overheating of the transistor leakage current caused by the conventional silicon oxide can be effectively reduced. In the present embodiment, the active layer 13 includes a first connection portion 131 and a second connection portion 132 connected to the first connection portion 131, the first connection portion 131 is located above the source 12a and overlaps the source 12a, and an orthogonal projection of the first connection portion 131 on the substrate 11 is located within an orthogonal projection of the source 12a on the substrate 11; the second connection portion 132 is located on the substrate 11 and is arranged side by side with the source electrode 12 a.
As shown in fig. 3 to 5, the drain electrode 14 on the active layer 13 is covered, and the drain electrode 14 is at least partially overlapped or completely overlapped with the active layer 13; the drain 14 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al), among others. In the present embodiment, the drain electrode 14 and the active layer 13 are completely overlapped, but not limited thereto. Specifically, the drain electrode 14 includes a third connection portion 141 and a fourth connection portion 142 connected to the third connection portion 141, the third connection portion 141 is disposed above the first connection portion 131 in an overlapping manner, and the fourth connection portion 142 is disposed above the second connection portion 132 in an overlapping manner, wherein thicknesses of the third connection portion 141 and the fourth connection portion 142 may be selected according to actual requirements, and particularly, it is optimal that a total thickness of the source electrode 12a, the first connection portion 131, and the third connection portion 141 is equal to a total thickness of the second connection portion 132 and the fourth connection portion 142.
As shown in fig. 6, a first insulating layer 15 is formed on the source electrode 12a, the data line 12, the active layer 13 and the drain electrode 14, and the first insulating layer 15 is, for example, silicon oxide (SiOx), silicon nitride (SiNx) or a combination thereof.
As shown in fig. 7 and 8, a gate electrode 16a and a scan line 16 are disposed on the first insulating layer 15, and the gate electrode 16a is electrically connected to the scan line 16, wherein the third metal layer may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al).
As shown in fig. 9, a second insulating layer 17 is formed on the gate electrode 16a and the first insulating layer 15, and the second insulating layer 17 is, for example, silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
As shown in fig. 9 to 12, the planarization layer 18 covering the second insulating layer 17, and the reflective electrode 19 covering the planarization layer 18 are electrically connected to the drain 14, and specifically, as shown in fig. 10 and 11, the array substrate further has a via hole 101 penetrating through the planarization layer 18, the second insulating layer 17, and the first insulating layer 15, and the reflective electrode 19 is electrically connected to the drain 14 after filling the via hole 101. Wherein, the orthographic projection of the drain electrode 14, the active layer 13 and the source electrode 12a on the substrate 11 is positioned in the orthographic projection of the reflective electrode 19 on the substrate 11. In the present embodiment, the material of the reflective electrode 19 is molybdenum or aluminum.
The array substrate of the present invention is formed by designing a horizontal channel structure (i.e., the source electrode 12a and the drain electrode 14 are located at the same layer and horizontally spaced apart from each other) of a tft (thin Film transistor) into a vertical channel structure (i.e., the source electrode 12a and the drain electrode 14 are located at different layers above and below and at least partially overlap, and the active layer 13 is sandwiched between the source electrode 12a and the drain electrode 14). Therefore, the occupied area of the TFT on the array substrate is reduced, the channel length of a vertical channel structure of the TFT is reduced, the conductivity of the TFT is improved, and power consumption is reduced. The array substrate effectively avoids the problem that the top end of a conventional BCE (back channel) type channel cannot be covered with metal by utilizing the self-shielding effect of the vertical channel structure, so that the reflective electrode 19 can also cover the upper regions (namely the TFT region 40 in fig. 7) of the source electrode 12a, the active layer 13 and the drain electrode 14, and the TFT region can also be used as a reflective region, thereby increasing the reflective area of the reflective electrode 19.
Specifically, as shown in fig. 13, when the incident light irradiates the TFT area, the incident light can be reflected back by the reflective electrode 19 corresponding to the TFT area to achieve the display effect, so that the aperture ratio is greatly improved. Meanwhile, the aspect ratio of the TFT vertical channel structure can be adjusted by adjusting the thickness of the active layer 13 and the shape curve of the edge of the active layer 13, for example, by designing the shape of the edge of the active layer 13 into an irregular pattern to adjust the aspect ratio. By strictly calculating, taking the S0291 AA area (effective display area) 29056 × 66896um as an example, the resolution can be improved from the original 12a8 × 296 to 1937 × 4459 and even higher by applying the design.
Further, as shown in fig. 10 and 12, a first rough structure 181 is disposed on a surface of the flat layer 18, which is matched with the reflective electrode 19, a second rough structure 191 is disposed on a side of the reflective electrode 19, which faces away from the flat layer 18, and the second rough structure 191 and the first rough structure 181 are corresponding in shape and size. The second roughness 191 enables the reflective electrode 19 to be diffusely reflected. In the present embodiment, an imprint process may be used to form the rugged first roughness 181 on the surface of the planarization layer 18. Specifically, by designing an optimal imprint pattern, the pattern is imprinted with a corresponding material of the planarization layer 18 (the material of the planarization layer 18 may be a dedicated imprint resist) before the pattern is uncured, and the resist is cured after the imprint. Due to the existence of the first rough structure 181, after the reflective electrode 19 is deposited on the surface of the planarization layer 18 on which the first rough structure 181 is formed, the second rough structure 191 is formed on the side of the reflective electrode 19 opposite to the planarization layer, and then the fourth metal layer is etched and patterned to form the reflective electrode 19 with the second rough structure 191, so as to achieve the effect of diffuse reflection.
Further, as shown in fig. 12, the first roughness 181 and the second roughness 191 are, for example, a plurality of protrusionsA raised part with a height of
Preferably, the slope angle is 15-25 degrees. The plurality of protrusions together form a first rough structure 181 or a second rough structure 191 having a peak-valley shape.
As shown in fig. 13, the present invention further provides a reflective liquid crystal display panel, which includes the array substrate, a color filter substrate opposite to the array substrate, and a liquid crystal layer 30 located between the array substrate and the array substrate. The color filter substrate includes a substrate 21, a common electrode 22 covers a side of the substrate 21 facing the array substrate, and the common electrode 22 is made of transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO), for example. In this embodiment, when natural light is incident from the color filter substrate side toward the array substrate, an electric field for controlling the deflection of the liquid crystal layer 30 is formed by applying the pixel voltage to the reflective electrode 19 and the common voltage Vcom to the common electrode 22, so as to finally realize the display effect of the reflective liquid crystal display panel.
In this document, the terms of upper, lower, left, right, front, rear and the like are used to define the positions of the structures in the drawings and the positions of the structures relative to each other, and are only used for the sake of clarity and convenience in technical solution. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It is also to be understood that the terms "first" and "second," etc., are used herein for descriptive purposes only and are not to be construed as limiting in number or order.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
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