CN1248303C - Method for forming metal capacitor by damascene process and product thereof - Google Patents

Abstract

Before forming metal film capacitor, the copper mosaic process is first used to make the lower inner connecting wire, one insulating layer is then deposited to form opening, the first metal layer, dielectric layer and the second metal layer are deposited successively, and the chemical mechanical grinding process is then performed to eliminate the excessive first metal layer, dielectric layer and second metal layer outside the opening until the insulating layer below the opening is exposed to form the capacitor in the opening. After the capacitor is completed, the copper damascene process is continued to form the interconnect thereon. The size of the integrated circuit with the embedded capacitor can be easily reduced, the required photoetching steps are reduced, the manufacturing cost of the integrated circuit with the embedded capacitor is reduced, and the height difference between the capacitor area and the non-capacitor area is reduced.

Description

Method for forming metal capacitor by damascene process and product thereof

technical field

The invention relates to an integrated circuit for forming a capacitor, in particular to a method for forming a metal capacitor by using a damascene process and its product.

Background technique

It is well known that capacitors can be integrated with various integrated circuits. For example, they can be used as decoupling capacitors to improve voltage regulation and provide noise immunity for power distribution. It can also be applied in analog/logic circuit, analog-digital converter, mixed signal (mixedsignal), or radio frequency (radiofrequency) circuit operation, etc.

FIG. 1-FIG. 4 show a conventional method of manufacturing a semiconductor device including a capacitor 20 .

As shown in FIG. 1 , an aluminum metal layer is deposited on the insulating layer 12 , followed by a photolithographic etching process to form aluminum metal layers 14 a and 14 b. The insulating layer 12 includes some elements (not shown) formed on and in the silicon substrate.

Next, as shown in FIG. 2, an insulating layer 16 is formed on the aluminum metal layers 14a and 14b and the insulating layer 12, and a tungsten plug (tungstenplug; W-plug) 18 and the aluminum metal layer 14a are formed in the insulating layer 16. Electrically connected, after that, deposit metal layer/dielectric layer/metal layer sequentially on the tungsten plug 18 and the insulating layer 16, and after performing photolithographic etching, a first conductive plate 21, a dielectric layer 22 and a second conductive plate 21 are formed. The conductive plate 23 thus constitutes the capacitor 20 . Wherein, the first conductive plate 21 (ie, the lower electrode) is connected to the aluminum metal layer 14a via the tungsten plug 18 .

Continue to deposit another insulating layer 26 over the capacitor 20 and the insulating layer 16 , and simultaneously form tungsten plugs 28 a and 28 b in the insulating layer 26 and the insulating layer 16 below it, as shown in FIG. 3 .

Continue to deposit another aluminum metal layer on the insulating layer 26 and the tungsten plugs 28 a and 28 b, and perform photolithography and etching process to form aluminum metal layers 34 a and 34 b, as shown in FIG. 4 . The aluminum metal layer 34a is electrically connected to the first conductive plate 23 (ie, the upper electrode) through the tungsten plug 28a, and the aluminum metal layer 34b is electrically connected to the lower aluminum metal layer 14b through the tungsten plug 28b. Its main flaws are:

In the above process, an additional photolithography step is required to form the capacitor 20 to integrate the capacitor 20 into an integrated circuit, thus increasing the cost of the entire semiconductor process. In such a process, if the capacitance of the panel capacitor 20 is to be increased, the layout area of the panel capacitor 20 must be increased. However, such a method will sacrifice the space between the capacitor 20 and its adjacent wires, and will not effectively reduce the size of the entire integrated circuit.

In US Pat. No. 6,025,226, a method for forming a capacitor while forming a damascene via is disclosed. In this method, when depositing the conductive layer as the bottom electrode, the opening of the capacitor and the opening of the via are filled at the same time. Its main flaws are:

1. The conductive layer must be thick enough to fill the opening of the via window, and cannot fill the opening of the capacitor, which is quite difficult in process control.

2. In addition, due to the increasing integration of components and the trend of increasing data transmission speed, wires made of aluminum metal can no longer meet the requirements for speed. Therefore, metal copper with high conductivity is used as wires to reduce RC delay. (RC delay) is the current development trend. However, copper metal cannot be used to define patterns by dry etching. The reason is that the copper chloride (CuCl.) formed by the reaction of copper metal and chlorine plasma gas has a very high boiling point (about 1500 ° C), and the production of copper wires requires It is performed by a damascene process. Also for this reason, the present invention applies the copper process to the process of integrated circuits containing capacitors.

Contents of the invention

The main object of the present invention is to provide a method for forming a metal capacitor by using a damascene process. The metal capacitor is formed by using a damascene process. Before forming a film capacitor, a first copper wire and a second copper wire are formed in a first insulating layer, and the The first and second copper wires are surrounded by the barrier layer and the first sealing layer. By overcoming the drawbacks of the prior art, the size of the integrated circuit containing the capacitor can be easily reduced.

The second object of the present invention is to provide a method for forming metal capacitors by using a damascene process, so as to reduce the required photolithography and etching steps when manufacturing integrated circuits containing capacitors.

The third object of the present invention is to provide a method for forming a metal capacitor by using a damascene process, so as to reduce the manufacturing cost of an integrated circuit containing a capacitor.

The fourth object of the present invention is to provide a method for forming a metal capacitor by using a damascene process, so as to reduce the height difference between the capacitor area and the non-capacitor area.

The fifth object of the present invention is to provide a metal capacitor product formed by a damascene process to achieve the purpose of having a copper damascene structure of a metal capacitor.

The purpose of the present invention is achieved in that a method for forming a metal capacitor utilizing a damascene process is characterized in that it at least includes the following steps:

(1) providing a first insulating layer;

(2) forming a first copper wire and a second copper wire in the first insulating layer;

(3) forming a first sealing layer on the first and second copper wires;

(4) forming a second insulating layer on the first sealing layer;

(5) forming an opening in the second insulating layer and the first sealing layer, exposing the first copper wire;

(6) conformally forming a first metal layer in the opening;

(7) conformally forming a dielectric layer on the first metal layer;

(8) conformally forming a second metal layer on the dielectric layer;

(9) removing the first metal layer, the dielectric layer and the second metal layer to expose the second insulating layer;

(10) forming a third insulating layer on the second insulating layer and the second metal layer;

(11) forming a plurality of dual damascene patterns in the third insulating layer and the second insulating layer, the dual damascene patterns comprising a plurality of trenches and a plurality of via holes;

(12) Form a third copper wire and a fourth copper wire in the trench, and form a third, a copper plug, a fourth, and a second copper plug in the via hole, wherein the second metal layer The third and first copper plugs are electrically connected to the third copper wire, and the fourth copper wire is electrically connected to the second copper wire through the fourth and second copper plugs;

(13) Forming a second sealing layer on the third and fourth copper wires.

The material of the first metal layer is at least one selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum, or aluminum-copper alloy. The material of the dielectric layer is at least one selected from silicon nitride, silicon oxynitride, silicon carbide, tantalum oxide, zirconium oxide, hafnium oxide or aluminum oxide. The material of the second metal layer is at least one selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum, or aluminum-copper alloy. The method for removing the first metal layer, the dielectric layer and the second metal layer to expose the second insulating layer is chemical mechanical polishing. The thickness of the first metal layer is between 100 angstroms and 2000 angstroms. The thickness of the dielectric layer is between 100 angstroms and 1200 angstroms. The thickness of the second metal layer is between 200 angstroms and 2000 angstroms.

The present invention also provides a metal capacitor with a damascene structure, which is characterized in that it includes the following structure: the first copper wire and the second copper wire are arranged in the first insulating layer; the second insulating layer is arranged in the first insulating layer On the second insulating layer, there is an opening on the first copper wire; the first metal layer is conformably disposed in the opening and is in contact with the surface of the first copper conductor; the dielectric layer is conformably disposed on the first metal layer in the opening; a second metal layer is conformably disposed on the dielectric layer in the opening; a third insulating layer is disposed on the second insulating layer and the second metal layer; The first copper damascene structure and the second copper damascene structure are disposed in the second insulating layer and the third insulating layer, the first copper damascene structure is composed of the third copper wire and the first copper plug, and the first copper damascene structure is composed of the third copper wire and the first copper plug. The second copper damascene structure is composed of the fourth copper wire and the second copper plug, the second metal layer is electrically connected with the third copper wire through the first copper plug, and the fourth copper wire is connected through the first copper plug. Two copper plugs are electrically connected with the second copper wire; the first sealing layer is configured between the second copper wire and the second insulating layer; the second sealing layer is configured on the third and fourth copper wires.

The material of the first metal layer is at least one selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum, or aluminum-copper alloy. The material of the dielectric layer is at least one selected from silicon nitride, silicon oxynitride, silicon carbide, tantalum oxide, zirconium oxide, hafnium oxide or aluminum oxide. The material of the second metal layer is at least one selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum, or aluminum-copper alloy. The thickness of the first metal layer is between 100 angstroms and 2000 angstroms. The thickness of the dielectric layer is between 100 angstroms and 1200 angstroms. The thickness of the second metal layer is between 200 angstroms and 2000 angstroms.

The following describes in detail in conjunction with preferred embodiments and accompanying drawings.

Description of drawings

1 to 4 are schematic cross-sectional views of the traditional process of integrating capacitors into integrated circuits.

5-14 are schematic cross-sectional flow charts of the method of the present invention.

Detailed ways

The method of the present invention provides a method for manufacturing metal capacitors using a damascene process and its product, and is combined with a copper damascene process. Before the metal film capacitor is formed, the copper metal damascene process is used to make the underlying interconnection, then an insulating layer is deposited, and the capacitor opening is formed in it, and then the first conformal metal layer, the dielectric layer, and the dielectric layer are sequentially deposited. layer and the second metal layer, and then remove the redundant first metal layer, dielectric layer and second metal layer by chemical mechanical polishing process. After the capacitor is formed in the capacitor opening in the insulating layer, the copper damascene process is used to fabricate the interconnection thereon.

Referring to FIG. 5-FIG. 14 , it is a schematic cross-sectional structure diagram of a method for forming a metal capacitor using a damascene process combined with a copper process in a preferred embodiment of the present invention.

Referring to FIG. 5 , an insulating layer 102 is firstly provided, and the insulating layer 102 may include other interconnections, and the insulating layer 102 includes components formed on and in the substrate. In order to clearly describe the content of the present invention, these underlying circuit elements are not shown in the figure. Another insulating layer 106 is formed on the insulating layer 102 with a thickness of about 2000-6000 angstroms.

As shown in FIG. 6 , openings are formed in the insulating layer 106 by photolithographic etching.

Referring to FIG. 7 , a conformable barrier layer 103 is formed on the insulating layer 106 and the surface of the opening therein. Then copper metal is filled into the opening, and chemical mechanical polishing is performed to remove excess copper metal and the barrier layer 103 , and form copper wires 104 a and 104 b in the insulating layer 106 . Then at least the sealing layer 108 is formed on the copper wires 104a and 104b. In the figure, the comprehensive sealing layer 108 is taken as an example, its thickness is about 100-400 angstroms, and its material can be silicon nitride (SiN) or Silicon carbide (SiC).

Referring to FIG. 8 , an insulating layer 110 is formed on the sealing layer 108 .

Referring to FIG. 9, an opening 112 is formed in the insulating layer 110 and the sealing layer 108, and the opening 112 exposes the surface of the copper wire 104a to be in contact with the bottom electrode, and the opening 112 is defined to form a capacitor. The height of the insulating layer 110 and the area of the opening 112 control the capacitance of the capacitor. Using this method to increase the capacitance will not sacrifice the space of the capacitor and adjacent wires. Therefore, the size of the integrated circuit including the capacitor can be easily reduced.

Referring to FIG. 10 , a conformable first metal layer 114 , a dielectric layer 116 and a second metal layer 118 are formed on the surface of the insulating layer 110 and the opening 112 . Wherein the first metal layer 114 is used to form the lower electrode, and its thickness is about 100-2000 angstroms; the thickness of the dielectric layer 116 is about 100-1200 angstroms, but the actual thickness still depends on the application of the capacitor and its thickness. It depends on the required capacitance; the second metal layer 118 will be used to form the upper electrode, and its thickness is about 100-2000 angstroms. The material of the first metal layer 114 and the second metal layer 118 can be titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), aluminum, aluminum copper alloy (AlCu) and the like. The material of the dielectric layer 116 can be silicon nitride, silicon oxynitride, silicon carbide (SiC), tantalum oxide (TaO ₂ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ), aluminum oxide (Al ₂ O ₃ )wait.

Referring to FIG. 11 , a chemical mechanical polishing process is performed to remove the redundant first metal layer 114 , dielectric layer 116 and second metal layer 118 until the insulating layer 110 underneath is exposed. The first metal layer 114 left in the opening 112 acts as a lower electrode, the dielectric layer 116 left in the opening 112 acts as a capacitor dielectric layer, and the second metal layer 118 left in the opening 112 acts as an upper electrode, thus forming a capacitor 140. The bottom electrode 114 is in electrical contact with the copper wire 104a.

According to the formation steps of the capacitor 140 described above, only an additional photolithography etching step is required to define the opening 112 for forming the embedded capacitor 140 , and a CMP process is required to define the capacitor 140 . Accordingly, the number of photolithographic etch steps required to fabricate an integrated circuit incorporating capacitor 140 is reduced. Furthermore, a difference in surface height between the capacitor area and the non-capacitor area can be avoided.

As shown in FIG. 12 , an insulating layer 120 is formed on the capacitor 140 and the insulating layer 110 .

Referring to FIGS. 13 and 14 , a dual damascene process is then performed to form a dual damascene pattern in the insulating layer 120 and the insulating layer 110 , and the pattern is composed of trenches 124 a and 124 b and via holes 122 a and 122 b. The via 122b exposes the surface of the copper wire 104b , and the via 122a exposes the surface of the top electrode 118 .

As shown in FIG. 14, a compliant barrier layer 126 is formed on the surfaces of the insulating layers 120 and 110, the trenches 124a and 124b, and the via holes 122a and 122b, and filled with copper metal, followed by chemical mechanical polishing. , to remove excess copper metal to form copper traces 130a and 130b and copper plugs 128a and 128b in the dual damascene pattern. Afterwards, at least a sealing layer is formed on the surface of the copper wires 130a and 130b. In this embodiment, the comprehensive sealing layer 132 is taken as an example, and its material can be silicon nitride or silicon carbide. Therefore, the upper electrode 118 is electrically connected to the copper wire 130a through the copper plug 128a, and the wire 104b is electrically connected to the copper wire 130b through the copper plug 128b.

Subsequent copper manufacturing process continues until the manufacture of the entire interconnection is completed. Since it is prior art, it will not be restated.

The material of the above-mentioned insulating layers 102, 106, 110 and 120 can be a low dielectric constant material, such as doped or undoped silicon oxide, spin-on polymer low dielectric constant material (such as FLARE, Si4C, PAE -II, etc.) or chemical vapor deposition type low dielectric constant material, etc. (such as blackdiamond, BD, Coral, Greendot, Aurora).

The present invention utilizes the damascene structure with metal capacitors fabricated by the above method, as shown in FIG. The insulating layer 110 is disposed on the insulating layer 106 , wherein the insulating layer 110 has an opening 112 located on the copper wire 104 a. The metal layer 114 is conformably disposed in the opening 112 and is in contact with the surface of the copper wire 104a.

The dielectric layer 116 is conformally disposed on the metal layer 114 in the opening 112 . The metal layer 118 is conformably disposed on the dielectric layer 116 in the opening 112 . The insulating layer 120 is disposed on the insulating layer 110 and the metal layer 118 . The first copper damascene structure and the second copper damascene structure are disposed in the insulating layers 110 and 120, wherein the first copper damascene structure is composed of copper wire 130a and copper plug 128a, and the second copper damascene structure is composed of copper wire 130b and copper plug 128a. The metal layer 118 is electrically connected to the copper wire 130a through the copper plug 128b, and the copper wire 130b is electrically connected to the copper wire 104b through the copper plug 128b. The sealing layer 108 is disposed between the copper wire 104 b and the insulating layer 110 . The sealing layer 132 is disposed on the copper wires 130a and 130b.

Although the present invention is disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any changes and modifications made by those skilled in the art without departing from the spirit and scope of the present invention belong to the present invention. within the scope of protection.

Claims (15)

1. A method for forming a metal capacitor using a damascene process, characterized in that it at least includes the following steps: (1) providing a first insulating layer; (2) forming a first copper wire and a second copper wire in the first insulating layer; (3) forming a first sealing layer on the first and second copper wires; (4) forming a second insulating layer on the first sealing layer; (5) forming an opening in the second insulating layer and the first sealing layer, exposing the first copper wire; (6) conformally forming a first metal layer in the opening; (7) conformally forming a dielectric layer on the first metal layer; (8) conformally forming a second metal layer on the dielectric layer; (9) removing the first metal layer, the dielectric layer and the second metal layer to expose the second insulating layer; (10) forming a third insulating layer on the second insulating layer and the second metal layer; (11) forming a plurality of dual damascene patterns in the third insulating layer and the second insulating layer, the dual damascene patterns comprising a plurality of trenches and a plurality of via holes; (12) Form a third copper wire and a fourth copper wire in the trench, and form a third, a copper plug, a fourth, and a second copper plug in the via hole, wherein the second metal layer The third and first copper plugs are electrically connected to the third copper wire, and the fourth copper wire is electrically connected to the second copper wire through the fourth and second copper plugs; (13) Forming a second sealing layer on the third and fourth copper wires. 2. The method for forming a metal capacitor using a damascene process according to claim 1, wherein the material of the first metal layer is selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum, or an aluminum-copper alloy at least one of the . 3. The method for forming a metal capacitor using a damascene process according to claim 1, wherein the material of the dielectric layer is selected from silicon nitride, silicon oxynitride, silicon carbide, tantalum oxide, zirconium oxide, hafnium oxide or at least one of alumina. 4. The method for forming a metal capacitor using a damascene process according to claim 1, wherein the material of the second metal layer is selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum, or an aluminum-copper alloy at least one of the . 5. The method of forming a metal capacitor using a damascene process according to claim 1, characterized in that: removing the first metal layer, the dielectric layer and the second metal layer to expose the second insulating layer For the chemical mechanical polishing method. 6. The method for forming a metal capacitor by using a damascene process according to claim 1, wherein the thickness of the first metal layer is between 100 angstroms and 2000 angstroms. 7. The method for forming a metal capacitor using a damascene process according to claim 1, wherein the thickness of the dielectric layer is between 100 angstroms and 1200 angstroms. 8. The method for forming a metal capacitor using a damascene process as claimed in claim 1, wherein the thickness of the second metal layer is between 200 angstroms and 2000 angstroms. 9. A metal capacitor with a damascene structure formed by the method according to any one of claims 1-8, characterized in that it comprises the following structure: the first copper wire and the second copper wire are arranged in the first insulating layer ; the second insulating layer is disposed on the first insulating layer, and an opening in the second insulating layer is located on the first copper wire; the first metal layer is conformably disposed in the opening, and is connected to the first copper wire The surface contact of the wire; the dielectric layer is conformably disposed on the first metal layer in the opening; the second metal layer is conformably disposed on the dielectric layer in the opening; the third insulating layer is disposed on the On the second insulating layer and the second metal layer; a first copper damascene structure and a second copper damascene structure are disposed in the second insulating layer and the third insulating layer, and the first copper damascene structure is composed of the third copper damascene structure wire and a first copper plug, the second copper damascene structure is composed of a fourth copper wire and a second copper plug, and the second metal layer passes through the first copper plug and the third copper wire Electrically connected, the fourth copper wire is electrically connected to the second copper wire through the second copper plug; the first sealing layer is configured between the second copper wire and the second insulating layer; the second sealing layer configured on the third and fourth copper wires. 10. The metal capacitor with a damascene structure according to claim 9, characterized in that: the material of the first metal layer is selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum, or aluminum-copper alloy. at least one. 11. The metal capacitor with a mosaic structure according to claim 9, characterized in that: the material of the dielectric layer is selected from silicon nitride, silicon oxynitride, silicon carbide, tantalum oxide, zirconium oxide, hafnium oxide or oxide at least one of aluminum. 12. The metal capacitor with a damascene structure according to claim 9, characterized in that: the material of the second metal layer is selected from titanium, titanium nitride, tantalum, tantalum nitride, aluminum, or aluminum-copper alloy. at least one. 13. The metal capacitor with a damascene structure as claimed in claim 9, wherein the thickness of the first metal layer is between 100 angstroms and 2000 angstroms. 14. The metal capacitor with a damascene structure according to claim 9, wherein the thickness of the dielectric layer is between 100 angstroms and 1200 angstroms. 15. The metal capacitor with a damascene structure as claimed in claim 9, wherein the thickness of the second metal layer is between 200 angstroms and 2000 angstroms.

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