CN1260893C - Integrated RF phase-locked loop frequency synthesizer - Google Patents

Abstract

The invention belongs to the technical field of wireless communication equipment, and relates to an integrated radio frequency phase-locked loop frequency synthesizer. It is composed of a digital unit unit integrated on a chip using a CMOS process, an analog unit unit and a loop filter realized by off-chip components, wherein the digital unit unit includes; R programmable counter, P programmable counter, S programmable A programming counter, a three-wire serial interface circuit, a shift register and a power consumption controller; the analog unit includes: a frequency and phase detector, a dual-mode prescaler, a voltage-controlled oscillator, a charge pump and a constant transconductance source; the present invention The reference frequency, output frequency and the current of the charge pump can be controlled through the three-wire serial interface, and it also realizes the functions of internal voltage-controlled oscillator and external voltage-controlled oscillator selection, power consumption control, etc., making the frequency synthesizer It has great adaptability and can be applied to various communication systems.

Description

Integrated RF phase-locked loop frequency synthesizer

Technical Field The present invention belongs to the technical field of wireless communication equipment, and in particular relates to the structural design of a frequency synthesizer.

Background Art A phase-locked loop frequency synthesizer is a component that is widely used in wireless communications. Its output can be used as a local oscillator signal for various transceivers, and can also perform functions such as modulation, demodulation, and carrier recovery. However, it is difficult to realize an integrated phase-locked loop frequency synthesizer. It includes high-frequency modules, low-frequency modules and digital circuits, and is a very complex digital/analog/RF hybrid system.

At present, the phase-locked loop frequency synthesizer is generally composed of a system composed of discrete modules. The entire system includes modules such as voltage-controlled oscillators, dual-mode prescalers, programmable counters, frequency and phase detectors, and loop filters. , each module is a separate chip. Although this can avoid the coupling between the various modules, thus providing higher performance. However, the system built with discrete modules is large in size and high in cost, and more modules will inevitably reduce the stability of the system.

Summary of the invention In order to overcome the deficiencies of the prior art, the present invention proposes an integrated radio frequency phase-locked loop frequency synthesizer, which adopts a cheap CMOS process and integrates a constant transconductance source (bias circuit), a voltage-controlled oscillator, and a dual-mode The prescaler, frequency and phase detector, charge pump, various digital counters, shift registers and control circuits, as well as the three-wire serial interface with the baseband circuit are integrated on the same chip. The reference frequency, output frequency and charge pump current of the frequency synthesizer can be controlled through the three-wire serial interface, and also realize the selection of internal voltage-controlled oscillator and external voltage-controlled oscillator, power consumption control and other functions, making The frequency synthesizer has great adaptability and can be applied in various communication systems.

An integrated radio frequency phase-locked loop frequency synthesizer proposed by the present invention is composed of digital unit parts integrated on a chip using CMOS technology, analog unit parts and a loop filter realized by off-chip components, wherein the digital The unit components include: R programmable counter, P programmable counter, S programmable counter, three-wire serial interface circuit, shift register and power consumption controller; the analog unit includes: frequency discrimination phase detector, dual-mode prescaler device, voltage-controlled oscillator, charge pump and constant transconductance source; the connection relationship of each device of the frequency synthesizer is: the output terminal of the said voltage-controlled oscillator is connected with the input terminal of the dual-mode prescaler, and the dual-mode The output terminal of the prescaler is connected with the input terminal of the programming P counter and the programmable S counter respectively, the output terminal of the S counter is connected with the input of the dual-mode prescaler, and the output terminal of the P counter is respectively connected with the input terminal of the S counter Connected to the input terminal of the frequency and phase detector, the input of the programmable R counter receives the crystal oscillator signal (RER_IN) input from the reference frequency source, and the output of the programmable R counter is connected to the input of the frequency and phase detector , the output end of the frequency and phase detector is connected with the input end of the charge pump, and the output end of the charge pump is connected with the input end of the said voltage controlled oscillator through the loop filter; the said shift register is connected with the three-wire serial The interface is connected to control the frequency division ratio of the three counters R, S and P and to control the working mode of the entire frequency synthesizer; the power management module provides enable signals for each sub-module, and the constant transconductance source provides Each analog unit component provides bias, and the final required signal is obtained from the output of the voltage-controlled oscillator.

Features and effects of the present invention

The present invention realizes a complete integrated RF phase-locked loop frequency synthesizer, which integrates a constant transconductance source (bias circuit), a voltage-controlled oscillator, a dual-mode prescaler, a frequency and phase detector, a charge pump, Various digital counters, shift registers and control circuits as well as a three-wire serial interface to the baseband circuit. The frequency synthesizer's reference frequency, output frequency and charge pump current can be controlled through the serial interface, and it also realizes the selection of internal voltage-controlled oscillator and external voltage-controlled oscillator, power consumption control and other functions, which are all The frequency synthesizer has great adaptability and can be applied in various communication systems.

The frequency synthesizer is implemented with 0.25um CMOS technology. The test results show that the frequency synthesizer can lock in a range of 1.82GHz to 1.96GHz, and the phase noise at 25MHz away from the center frequency can reach -119.25dBc/Hz. The analog part of the frequency synthesizer uses a supply voltage of 2.7V and consumes about 48mA of current.

Description of drawings

FIG. 1 is an overall block diagram of a phase-locked loop frequency synthesizer of the present invention.

FIG. 2 is a circuit diagram of an embodiment of the internal voltage-controlled oscillator circuit of the present invention.

FIG. 3 is a circuit diagram of an embodiment of an internal/external voltage-controlled oscillator mode selection circuit of the present invention.

FIG. 4 is a circuit diagram of an embodiment of the constant transconductance source circuit of the present invention.

FIG. 5( a ) is a block diagram of an embodiment of a dual-mode prescaler using dynamic circuit technology according to the present invention.

FIG. 5(b) is a circuit diagram of a D flip-flop (DFF) of this embodiment.

FIG. 5(c) is a circuit diagram of the NOR flip-flop (NOR_DFF) of this embodiment.

FIG. 6 is a schematic diagram of a structural embodiment of the charge pump of the present invention.

FIG. 7 is a circuit diagram of an embodiment of the loop filter circuit of the present invention.

FIG. 8 is a simple simulation model diagram of the phase-locked loop frequency synthesizer of the present invention.

FIG. 9 is an output spectrum diagram of this embodiment in a locked state.

FIG. 10 is the waveforms at the two input terminals of the frequency and phase detector of this embodiment observed with an oscilloscope in the locked state.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The phase-locked loop frequency synthesizer proposed by the present invention is described in detail in conjunction with the accompanying drawings and embodiments as follows:

The overall block diagram of the phase-locked loop frequency synthesizer of the present invention is as shown in Figure 1, is made up of the digital unit part that adopts CMOS technology to be integrated on a chip, the analog unit part and the loop filter that are realized by off-chip components, wherein , the digital unit components include; three programmable counters (R counter, P counter, S counter), three-wire serial interface circuit, shift register and power consumption controller; the analog unit includes: frequency and phase detector, dual Modulo Prescaler, Voltage Controlled Oscillator, and Constant Transconductance Source. The connection relationship of each module in the frequency synthesizer is:

The output of the voltage controlled oscillator is sent to the dual-mode prescaler for frequency division, and the result after frequency division is sent to the programmable P counter and programmable S counter for further frequency division, and the result of the S counter is fed back to the dual-mode prescaler The frequency divider controls its frequency division ratio, and the output of the P counter controls the reset operation of the S counter. At the same time, the output of the P counter is sent to the frequency and phase detector, and the crystal oscillator signal (RER_IN) from the reference frequency source is used in the frequency discrimination. Frequency discrimination and phase discrimination are carried out in the phase detector. The crystal oscillator signal (RER_IN) input by the reference frequency source needs to be divided by a programmable R counter. The output of the frequency and phase detector controls the switch of the charge pump, and the output of the charge pump After being filtered by the loop filter, the oscillation frequency of the voltage-controlled oscillator is controlled, and finally the required signal is obtained from the output of the voltage-controlled oscillator.

Among them, the R counter of the digital part divides the frequency of the signal given by the crystal oscillator to control the minimum frequency interval that the frequency synthesizer can achieve. Its frequency division ratio is controlled by a shift register and can vary from 3 to 255. The combination of P counter, S counter and the dual-mode prescaler of the analog part can realize the frequency division of the signal output by the voltage-controlled oscillator. These two counters are also programmable counters controlled by internal registers. When the frequency division mode of the dual-mode prescaler is 32/33, the frequency division ratio of the S counter can vary from 0 to 31, and the frequency division ratio of the P counter can vary from 3 to 511; when the dual-mode When the frequency division mode of the prescaler is 64/65, the frequency division ratio of the S counter can vary from 0 to 63, and the frequency division ratio of the P counter can vary from 3 to 255. In addition to controlling the frequency division ratio of the three counters R, S and P, the shift register also controls the working mode of the entire frequency synthesizer (dual-mode prescaler frequency division mode selection, charge pump current setting, VCO tuning characteristic selection (Positive tuning characteristics/negative tuning characteristics), multiplexing output LD control and test mode selection of the charge pump, etc.). The content of the internal register is written through the three-wire serial interface (CLK, DATA and LE), so that the work of the frequency synthesizer can be controlled by an external baseband processor. The power management module provides enable signals for each sub-module, and makes some sub-modules in an inactive state according to application requirements, so as to save system power consumption. The constant transconductance source provides bias for each analog unit component.

The frequency synthesizer integrates an on-chip voltage-controlled oscillator. Its circuit embodiment structure is shown in Figure 2. The mutually coupled NMOS transistor pair M1 and M2 compensate the loss of the LC resonant circuit, where the gate of M1 is connected to M2 The drain of M2 is connected to the on-chip inductor L2 and one pole of the diode D2 at the same time, the gate of M2 is connected to the drain of M1, and is connected to the on-chip inductor L1 and one pole of the diode D1 at the same time, and the diodes D1, D2 and the on-chip inductor L1, L2 forms a resonant tank, where the other poles of D1 and D2 are connected together and connected to the output Vctr1 of the loop filter, and the other poles of L1 and L2 are also connected together and connected to the PMOS tube as a current source The drain of M0 and one pole of the filter capacitor C0, the other pole of the filter capacitor C0 is connected to the power supply VDD, the gate of M0 is connected to the bias voltage VPB provided by the internal integrated constant transconductance source, and its source is also Connect to the power supply VDD. The on-chip voltage-controlled oscillator provides two differential signals L0+ and L0-, which are connected to the output of the on-chip voltage-controlled oscillator and also connected to the interface circuit with the dual-mode prescaler. The transconductance of the two NMOS tubes is mainly determined by the quality factor of the LC component. L1 and L2 are asymmetrical on-chip spiral inductors with 3.5 turns. They are all wound with the top layer of metal with a thickness of 1.5um. The length of the inner ring is 120um, the width of the metal wire is 10um, and the distance between the metal wires It is 2um, the inductance is about 3.740nH, the quality factor at 2GHz is about 7.4, and the quality factor at 1GHz is only 4.2.

D1 and D2 are capacitive reactance tubes formed by the P+ diffusion region and the N well. They work in the reverse cut-off region. The length of each finger PN junction is 0.58um, the width is 40um, and there are 15 fingers in total. When the reverse cut-off voltage changes from 3.0V to 0V, the capacitance of the capacitive reactance tube increases from 0.62pF to 1.02pF. M0 is a tail current source controlled by the bias voltage VPB. In order to reduce the influence of 1/f noise on the phase noise, M0 uses a long-channel PMOS transistor. The 10pF filter capacitor C0 provides a low-impedance channel for the high-order harmonics of the S node to the AC ground, which can attenuate the high-frequency noise components generated by the tail current source and improve the phase noise performance of the voltage-controlled oscillator. VPB is a bias voltage generated by a constant transconductance source. By using a constant transconductance source, the transconductance of M1 and M2 can be kept constant without being affected by temperature changes and power supply voltage changes, so that the negative resistance generated by the complementary coupling pair can also be kept constant, thereby reducing temperature changes and power supply voltage changes Effect on VCO output amplitude and phase noise. At the same time, VPB is also an enabling control terminal of the voltage-controlled oscillator, and when the voltage of VPB is VDD, the voltage-controlled oscillator will not work.

In order to expand the application range, the frequency synthesizer can also add an off-chip voltage-controlled oscillator, and the internal voltage-controlled oscillator does not work at this time. In this case, an internal/external VCO mode selection circuit is also required. By selecting a high-performance external voltage-controlled oscillator, this frequency synthesizer can be applied to some systems with higher performance requirements.

Figure 3 shows an embodiment of the selection circuit of the internal/external voltage-controlled oscillator mode. The selection circuit is composed of transistors MS1-MS16, DC blocking capacitors CS3, CS4, resistors RS5, RS6 and inductor LS1. Among them, transistors MS1 and Resistor RS5 constitutes a common-source amplifier, which amplifies the signal generated by the internal voltage-controlled oscillator in the first stage; transistors MS11, MS12 and resistor RS6 constitute another amplifier, which amplifies the oscillation signal generated from the external off-chip voltage-controlled oscillator Amplified, the two signals are then coupled together in the second-stage amplifier composed of transistors MS5~MS8; then the third-stage amplifier composed of transistors MS9, MS10 and inductor LS1 is finally amplified and then input to the dual-mode prescaler. The bias circuit is composed of transistors MS13~MS16; the connection relationship of each device is: the signal INT_VCO from the internal voltage-controlled oscillator is input to the gate of transistor MS1, the source of MS1 is grounded, and the drain is connected to the load resistor RS5 and the DC blocking capacitor One pole of CS3; the gate of transistor MS5 is connected to the power consumption control signal EN1B, the source is connected to the power supply VDD, the drain is connected to the source of transistor MS6, the gate of transistor MS6 and the other end of capacitor CS3, the drain of transistor MS6 , the drain of MS7, the gate of MS7, the gate of MS10, and one end of CS4 are connected; the source of MS7 is connected to the drain of MS8, the gate of MS8 is connected to the power consumption control signal EN1 and the gate of MS9, and the source of MS8 The drain of MS9 is connected to the source of MS10, the source of MS9 is grounded, one end of the inductor LS1 on the drain of MS10 and the interface Fdmp output to the dual-mode prescaler, the source of the transistor MS13 is grounded, and the drain The gate of MS11 is connected to the source of MS14, the drain of MS14 is connected to the gate of MS14, the gate of MS12 is connected to the drain of MS15, the gate of MS15 is connected to the bias signal VP2, and its source Connect to the drain of MS16, the gate of MS16 is connected to the control signal ENP, its source is connected to the power supply VDD, the drain of MS11 is connected to the external voltage-controlled oscillation signal EXT_VCO and the source of MS12, the source of MS11 is connected to ground, and the drain of MS12 is connected to One end of RS6 and one end of CS4, the other end of RS6 is connected to VDD.

EN1B, EN1 and ENP are power consumption control signals, which are generated by the power consumption control module, and VP2 is a bias signal generated by the on-chip constant transconductance source.

In Figure 3, CS3~CS4 are all on-chip DC blocking capacitors, which can prevent the DC operating points of each module from interfering with each other. The common-source amplifier composed of MS1 and RS5 amplifies the output signal of the internal voltage-controlled oscillator, and isolates the subsequent stage circuit from the internal voltage-controlled oscillator to avoid the influence of the latter stage circuit on the internal voltage-controlled oscillator. All three common source amplifiers are biased by constant transconductance sources. The signal of the external voltage-controlled oscillator enters from the source terminal of the transistor MS12 working in the common gate stage, and by adjusting the transconductance of MS12, the impedance matching of the input terminal of the signal of the external voltage-controlled oscillator can be realized. The bias circuit composed of constant transconductance source (controlling the level of VP2) and MS13-MS16 provides bias for MS11 and MS12. The oscillating signals from the internal voltage-controlled oscillator and the external voltage-controlled oscillator are combined to the same node through the output/input coupling inverter composed of MS5~MS8, and then amplified by the LC tuned amplifier composed of MS10 and on-chip inductor LS1 , the amplified signal is sent to the input of the dual-mode prescaler. The circuit also realizes the enable control, and controls the working status of each sub-circuit according to the enable signal and the logic level of the internal/external voltage-controlled oscillator selection signal, thereby reducing unnecessary power consumption and avoiding the gap between the signals. Interference between.

The frequency synthesizer uses an on-chip constant transconductance source to provide bias for each sub-module, so that the transconductance of each sub-module can be kept constant, reducing the impact of power supply voltage changes and temperature changes on the performance of each sub-module circuit. The circuit diagram of the constant transconductance source is shown in Figure 4. The self-bias network composed of transistors M7~M10 and resistor R0 is the core circuit of the constant transconductance source, where the source of the PMOS transistor M7 is connected to the power supply VDD, its gate is connected to the gate of M8, the drain of M8 and the Drain, the source of M8 is connected to the power supply VDD, the drain of M7 is connected to the drain of M9, the gate of M9 and the gate of M10, the source of M9 is grounded, the source of M10 is connected to one end of the resistor R0, and the other end of R0 One end is grounded.

The working principle of the constant transconductance source is explained as follows:

Assuming that M7 and M8 have the same size, the currents flowing through them are I ₁ and I ₂ respectively, ignoring the channel length modulation effect and the lining offset modulation effect, then:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}\frac{{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}}{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; VNB</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}\frac{{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 10</span>}}}{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 10</span>}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; VNB</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

Among them, μ _n is the mobility of the NMOS transistor, C _ox is the gate capacitance per unit area of the NMOS transistor, V _T is the threshold voltage of the NMOS transistor, R ₀ is the resistance value of the resistor R0, and V _VNB is the node voltage of the output node VNB. The relationship between I ₁ and the resistance value of resistor R0 can be deduced from formulas (1) and (2):

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="0"\; label="R"\; filenames="C20031010341800181.png"\; state="\{\{state\}\}">R</figure-callout></span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&mu;</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}\frac{{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}}{{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\sqrt{\frac{{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}}{{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 10</span>}}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

Then the transconductance of transistor M9 is:

${\mathrm{<span\; class="notranslate">\; g</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\sqrt{\frac{{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 9</span>}}}{{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; 10</span>}}<span\; class="notranslate">\; /</span>{\mathrm{<span\; class="notranslate">\; L</span>}}_{\mathrm{<span\; class="notranslate">\; 10</span>}}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

It can be seen from formula (4) that the current I ₁ flowing through M9 and the transconductance g _m of M9 are only related to the resistance value of resistor R0 and the sizes of M9 and M10. According to the current mirror principle, when the channel length modulation effect is ignored, the current and transconductance of each sub-module biased by the constant transconductance source are only related to the resistance value of R0 and the size of each transistor.

In order to avoid the influence of temperature change and process deviation on the constant transconductance source, resistor R0 adopts off-chip high-quality resistive elements. In the last realized constant transconductance source, the current flowing through M9 is about 100uA.

The dual-mode prescaler in the frequency synthesizer of the present invention has adopted dynamic circuit technology, and its embodiment circuit diagram is as shown in Figure 5 (a), and it is made of NOR gate flip-flop NOR_DFF1, NOR_DFF2 and D flip-flop DFF The synchronous 4/5 frequency divider (in the dotted line box in the figure), the asynchronous counter and the control logic are composed of three parts. When the internal node MD is logic high level, the frequency division ratio of the synchronous frequency divider is 4; when MD is logic low level, the frequency division ratio of the synchronous frequency divider is 5. The external control signal SW is used to select two frequency division ratios: 128 frequency division/129 frequency division or 64 frequency division/65 frequency division, and the Mode signal is between the two frequency division modes of the dual-mode prescaler. Choose between: N frequency division or N+1 frequency division (N is 128 or 64 depending on the SW control signal). Among them, CLK is a voltage-controlled oscillating signal, which is connected to the CLK input terminal of the NOR gate trigger NOR_DFF1, NOR_DFF2 and the CLK input terminal of the trigger DFF, and the output terminal Q+ of the trigger DFF is connected to D1 of the NOR gate trigger NOR_DFF1 The input terminal, the output terminal Q- is connected to the D1 input terminal of NOR_DFF2, the D2 input terminal of NOR_DFF1 is connected to the output terminal Q+ of NOR_DFF2, and its output terminal Q+ is connected to the input terminal D of DFF and the input terminal of the asynchronous counter, the input terminal of NOR_DFF2 D2 is connected to the output of the control logic, the output terminals Q- of NOR_DFF1 and NOR_DFF2 are suspended, the input of the control logic is provided by the asynchronous counter, and the asynchronous counter provides the frequency division signal Fout at the same time.

Synchronous 4/5 frequency divider is the most critical part of the entire dual-mode prescaler, its speed directly determines the highest operating frequency that the dual-mode prescaler can achieve, its power consumption It also determines the power consumption level of the whole circuit. At present, many researchers have done a lot of research on this part and proposed many methods, among which, coupling NAND gate and D flip-flop to form NAND flip-flop to realize dual-mode selection is the most commonly used method. However, when the synchronous frequency divider adopts the dynamic circuit technology of PMOS tube pre-charging, there are two NMOS tubes in series on the discharge channel, and the series connection of MOS tubes will increase the delay of the circuit, thereby reducing the working speed of the circuit.

Considering that the time delay of two parallel NMOS transistors must be shorter than that of two series connected NMOS transistors, the present invention proposes a new frequency divider structure that couples a NOR gate and a D flip-flop to form a NOR gate flip-flop to realize dual-mode selection. The circuit diagram of the D flip-flop (DFF) adopted in this embodiment is shown in Figure 5 (b), wherein, the clock CLK is connected to the gates of MP1, MP2, MN3, and MN5; the source of MP1 is connected to the power supply; the drain of MP1 is connected to The drain of MN1 and the gates of MN6, MP4 and MN2; the data terminal D is connected to the gate of MN1; the source of MN1 is grounded; the source of MP4 is connected to the power supply, and the drain is connected to the drain of MN6 and the gate of MN4; MN6 The source of MP2 is connected to the power supply, the drain is connected to the drain of MN2 and the gate of MP3; the source of MN2 is connected to the drain of MN3; the source of MN3 is grounded; the source of MP3 is connected to the power supply, and the drain Connect the gate of MP5 and MN7 and the drain of MN4, and connect the output terminal Q- at the same time; the source of MN4 is connected to the drain of MN5, and the source of MN5 is grounded; the source of MP5 is connected to the power supply, and the drain is connected to the drain of MN7 And the output terminal Q+; the source of MN7 is grounded. Its working principle is as follows: Transistors MP1 and MN1 form the input stage of the flip-flop, MP2, MN2 and MN3 form the second stage, while MP3, MN4 and MN5 form the output stage, and the inverter formed by MP5 and MN7 reverses the Q- , while the inverter composed of MP4 and MN6 controls the state of the MN4 tube. Its working principle is: when CLK is logic low level, the flip-flop is in the locked state, and the PMOS tube controlled by CLK charges the internal node; on the rising edge of CLK, the flip-flop evaluates, according to the input terminal D level to change its state. Compared with the flip-flop proposed by Qiuting Huang et al., the charging channel of the input stage and the discharging channel of the output stage of this flip-flop have one less transistor, thus changing the original static circuit into a dynamic circuit. This can reduce the capacitive load of the D input terminal and the second stage, shorten the charging and discharging time of the trigger, and improve the working speed of the synchronous frequency divider. Such advantages make it widely used in the field of radio frequency. Compared with the original circuit, the static power consumption of the flip-flop using the dynamic circuit is increased. Fortunately, for the application in the radio frequency field, the dynamic power consumption is the most important part of the power consumption, and the increased static power consumption accounts for the total power consumption. The ratio is small and will not significantly increase the power consumption of the entire circuit.

Figure 5(c) (NOR_DFF) shows the circuit diagram of the NOR gate flip-flop. Compared with DFF, only the input stage has been changed. Its input stage is composed of MP1, MN0 and MN1, and the discharge channel is composed of two parallel Composed of NMOS tubes. Compared with the scheme in the literature that consists of two NMOS tubes connected in series to form a discharge channel, this method can reduce the discharge time of the flip-flop and improve the working speed of the circuit. Coupling the NOR gate and the D flip-flop makes the logic gate and the fast storage element only introduce the same delay, so that the transmission delay of the synchronous frequency divider can be reduced and the working speed of the circuit can be improved. Compared with the traditional NAND trigger, the NOR trigger will have a smaller delay, which can further improve the working speed of the circuit.

The asynchronous counter is a flip-flop chain composed of five cascaded D flip-flops. Its working frequency is only 1/4 or 1/5 of the input frequency, and its speed requirement is reduced. To keep the overall circuit high performance, the asynchronous counter should have low power consumption, be glitch-free and have no restriction on the minimum input frequency. This embodiment adopts the universal fast TSPC D flip-flop proposed by Q.Huang et al.

The control logic controls the division ratio of the synchronous divider and selects the output frequency. Its function is to control the frequency division ratio of the synchronous 4/5 frequency divider and the output mode of the dual-mode prescaler, and it adopts the control logic structure usually used in the dual-mode prescaler.

The output signal of the crystal oscillator and the voltage-controlled oscillator is sent to the frequency and phase detector after frequency division to generate the control signal for controlling the charge pump switch. The frequency and phase detector of the present invention has adopted a traditional frequency and phase detector Circuit configuration.

The output of the frequency and phase detector generates the control signal of the charge pump through the logic control module. Since the charge pump uses switching circuit technology, the charge injection problem encountered by the switching circuit will also affect the performance of the frequency synthesizer. The frequency and phase detector used in the frequency synthesizer introduces a delay unit. Even in the case of locking, the output of the frequency and phase detector will appear low for a short time, causing the charge pump to switch periodically. , the resulting periodic charge injection will cause glitches in the output spectrum of the frequency synthesizer. In order to alleviate the glitches caused by charge injection, the frequency synthesizer adopts the structure of the charge pump embodiment shown in Figure 6. The charge pump is composed of four switches S1-S4, current sources and current sinks. One of the current sources One pole is connected to the power supply VDD, the other pole is connected to one end of the switches S2 and S3, the other end of the switch S2 is connected to the reference level Vref and one end of the switch S4, the other end of S4 is connected to the current sink, and the other end of S2 is connected to the loop filter and One end of the switch S1, the other end of S1 is connected to the current sink, one end of the current sink is connected to the switches S1 and S4, and the other end is connected to the ground, and the control signals of the switches S1-S4 are provided by the frequency and phase detector module.

The working process of the charge pump is: when the voltage of the voltage control terminal of the voltage controlled oscillator needs to increase, S2 and S4 are closed, S1 and S3 are opened, the current of the current source flows to the loop filter through S2, and the current of the current sink passes through the switch S4 is provided by the bias circuit connected to Vref; when the voltage at the voltage-controlled terminal of the voltage-controlled oscillator needs to be reduced, S1 and S3 are closed, S2 and S4 are opened, the current sink draws current from the loop filter through S1, and the current of the current source Flow through S3 to the bias circuit connected to Vref; when the voltage at the voltage control terminal of the voltage-controlled oscillator should remain constant, S1 and S2 are closed at the same time, S3 and S4 are opened at the same time, or, S1 and S2 are opened at the same time, S3 and S4 Closed at the same time, no current flows through the nodes Vref and Vout at this time. In this way, the current source and the current sink are always in the working state, which eliminates the extra delay introduced by the switching of the working state of the current source and the current sink and the interference related thereto. S1～S4 all adopt CMOS switch pair composed of PMOS tube and NMOS tube. By making the PMOS tube control signal and NMOS tube control signal of the same switch change to the opposite level at the same time, the charge injection of PMOS tube and the charge injection of NMOS tube The charge injections can cancel each other out, reducing the impact of clock feedthrough effects on the circuit. The two control signals of the same switch are obtained by inverting one of the control signals. In order to eliminate the delay introduced by the inversion operation, both control signals are added to the inverter chain, and the inverter of one of the control signals The chain has one more stage of inverter than the inverter chain of the other control signal. By adjusting the size of each inverter in the two sets of inverter chains, the delays introduced by the two sets of inverter chains can be equalized to avoid The charge injection problem occurs when the two control signals are not synchronized. In addition, S3 and S4 should be closed after the switches S1 and S2 are fully opened, and should be opened before S1 and S2 are closed, so that the corresponding switches of the two branches will not be in the closed state at the same time. This puts forward requirements on the timing between the switch control signals of the two branches, and these control signals with different timings can be realized by introducing inverter chains with unequal thresholds.

The current source and current sink can select one of four current values (I ₀ , 2I ₀ , 3I ₀ , 4I ₀ ) through two control signals M<1> and M<2>, where I ₀ is the reference current, The design value is 0.1mA, and M<1> and M<2> are controlled by internal registers, so that the baseband processor can control the current value of the current source and current sink through the three-wire serial interface, thereby controlling the phase-locked loop frequency synthesizer loop characteristics. When the linearity of the voltage-controlled oscillator tuning curve is not good, adjusting the current value of the charge pump in this way can also play a role in nonlinear processing.

In order to reduce the chip area, the embodiment of the loop filter of this frequency synthesizer is realized by off-chip components, as shown in Figure 7, including resistors R1, R2 and capacitors C1, C2 and C3; where, _Ip (t ) is the current from the charge pump, its input terminal is connected to one end of resistor R1 and one end of resistor R2 and one end of C2, the other end of R1 is connected to one end of C1, the other ends of C1 and C2 are grounded, and the loop filter The output controls the oscillation frequency of the voltage-controlled oscillator, and its output is connected to the other end of the resistor R2 and one end of C3, and the other end of C3 is grounded. The combination of the loop filter and the charge pump can form a fourth-order type II (four poles, two of which are at zero frequency) loop filter network.

I_P为电荷泵的电流；Kv/s是压控振荡器的传输函数，Kv为压控振荡器的调谐系数(即振荡频率随压控端电压的变化率)；1/N是分频器的传输函数。In order to understand the effect of the loop filter network on the noise and dynamic characteristics of the phase-locked loop frequency synthesizer of the present invention, the open-loop circuit gain of the frequency synthesizer must first be deduced. Fig. 8 shows a simple simulation model of the phase-locked loop frequency synthesizer of the present invention. In the figure, Kd is the gain factor of the phase detector, for the used frequency and phase detector, its gain factor is

I _P is the current of the charge pump; Kv/s is the transfer function of the voltage-controlled oscillator, and Kv is the tuning coefficient of the voltage-controlled oscillator (that is, the rate of change of the oscillation frequency with the voltage of the voltage-controlled terminal); 1/N is the frequency divider transfer function.

The noise source generated by the low frequency module in the circuit is also added in Fig. 8. Among them, din _p ² is the noise generated by the charge pump, which comes from the non-ideal characteristics of the charge pump, such as current source and current sink mismatch, charge injection caused by switching operations, etc., which will generate glitches at the output, and the current source A charge pump that does not match the current sink will inject charge into the loop filter and generate a frequency modulated signal at the output through the voltage controlled oscillator; di _R1 ² and di _R2 ² are the heat generated by the two resistors in the loop filter noise.

When various noise sources are not considered, the open-loop transfer function of the entire frequency synthesizer can be expressed as:

$\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; k</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; Kv</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; Kv</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

Among them, H(s) is the transfer function of the loop filter, which can be expressed as:

$\mathrm{<span\; class="notranslate">\; h</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; S</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; LF</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CenterDot;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

where Z _LF (s) is the impedance of the off-chip loop filter, which is:

${\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; LF</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; ]</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

Wherein, τ ₁ =R ₁ C ₁ , τ ₂ =R ₂ C ₃ .

Substituting (6) and (7) into (5), we can get:

$\mathrm{<span\; class="notranslate">\; G</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; Kv</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; [</span>{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; ]</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

From (8), it can be seen that the open-loop transfer function has one zero and four poles, two of which are at zero frequency.

Let |G(jω _c )|=1, the conditions that the loop bandwidth ω _c should meet can be obtained:

$\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; \&pi;</span>}}<span\; class="notranslate">\; \&CenterDot;</span>\frac{\mathrm{<span\; class="notranslate">\; Kv</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}<span\; class="notranslate">\; \&CenterDot;</span>\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; A</span>}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; +</span>{<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; B</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; )</span>{{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

in,

$\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; =</span>\frac{\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; =</span>\frac{\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}\frac{{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 10</span>}<span\; class="notranslate">\; )</span>$

The phase margin of the frequency synthesizer can be obtained from the argument of G(jω _c ):

$\mathrm{<span\; class="notranslate">\; PM</span>}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; the\; tan</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; the\; tan</span>}}^{<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; B</span>}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 11</span>}<span\; class="notranslate">\; )</span>$

Equation (11) takes the differential of _ωc and makes it equal to 0, and the condition that _ωc should satisfy when reaching the maximum phase margin can be obtained:

${\mathrm{<span\; class="notranslate">\; \&omega;</span>}}_{\mathrm{<span\; class="notranslate">\; c</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}\sqrt{\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; AB</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; A</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; +</span>\sqrt{{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; AB</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; A</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>\frac{\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; B</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; A</span>}<span\; class="notranslate">\; )</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 12</span>}<span\; class="notranslate">\; )</span>$

的函数。It can be seen from (11) that the phase margin of the frequency synthesizer has nothing to do with the absolute values of the resistors and capacitors in the loop filter, but only and

The function.

In order to ensure the stability of the loop, it is generally required that the phase margin is greater than 45 degrees, namely:

PM > 45° (13)

和 以及C₁和τ₁的值时，有两个自由度，可以尽量增大环路滤波网络对各种噪声的抑制作用而不影响该频率合成器的相位裕度和环路带宽。In actual design, the loop bandwidth is generally taken as about one tenth of the reference frequency. Under this condition, the values of C1~C3 and R1, R2 can be selected so that they meet the requirements of (9)~(13). Formulas (9)~(12) only provide three constraints, so that when selecting

and As well as the values of C ₁ and τ ₁ , there are two degrees of freedom, which can maximize the suppression effect of the loop filter network on various noises without affecting the phase margin and loop bandwidth of the frequency synthesizer.

Assuming that the noise currents generated by the current source and the current sink in the charge pump are di _n ² , in the case of the phase-locked loop locking, in each phase detection process, the current source and the current sink work simultaneously for a short period of time, assuming The proportion of this time period is α _p , then the noise current generated by the charge pump is:

di _np ² =2α _p di _n ² (14)

The transfer function from this noise source to the frequency synthesizer output can be derived from Figure 8:

$\frac{{\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{{\mathrm{<span\; class="notranslate">\; di</span>}}_{\mathrm{<span\; class="notranslate">\; np</span>}}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; LF</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; Kv</span>}}{\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; +</span>\frac{{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}\mathrm{<span\; class="notranslate">\; N\&pi;</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; LF</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CenterDot;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; Kv</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 15</span>}<span\; class="notranslate">\; )</span>$

For out-of-band phase noise, when the deviation frequency is much larger than the loop bandwidth ω _c , there are:

${\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; LF</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 16</span>}<span\; class="notranslate">\; )</span>$

Substituting formula (16) into (15), we can get:

$\frac{\mathrm{<span\; class="notranslate">\; \&theta;\; out</span>}}{\mathrm{<span\; class="notranslate">\; dinp</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; the\; s</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&ap;</span>\frac{\mathrm{<span\; class="notranslate">\; Kv</span>}}{{\mathrm{<span\; class="notranslate">\; the\; s</span>}}^{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 17</span>}<span\; class="notranslate">\; )</span>$

From formulas (14) and (17), the power spectral density of the SSB phase noise introduced by the charge pump can be obtained as:

${\mathrm{<span\; class="notranslate">\; \&Gamma;</span>}}_{\mathrm{<span\; class="notranslate">\; P</span>}}<span\; class="notranslate">\; \{</span>\mathrm{<span\; class="notranslate">\; \&Delta;\&omega;</span>}<span\; class="notranslate">\; \}</span><span\; class="notranslate">\; =</span>\frac{{{\mathrm{<span\; class="notranslate">\; \&theta;</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; \&Delta;\&omega;</span>}<span\; class="notranslate">\; )</span>}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&CenterDot;</span>{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; Kv</span>}}{{\mathrm{<span\; class="notranslate">\; \&Delta;\&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; 2</span>}{\mathrm{<span\; class="notranslate">\; \&alpha;</span>}}_{\mathrm{<span\; class="notranslate">\; p</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; d</span>}{{\mathrm{<span\; class="notranslate">\; i</span>}}_{\mathrm{<span\; class="notranslate">\; no</span>}}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 18</span>}<span\; class="notranslate">\; )</span>$

It can be seen from the formula (18) that to reduce the SSB phase noise introduced by the charge pump, the capacitor C2 and τ ₂ should be as large as possible.

Resistors R1 and R2 in the off-chip loop filter will generate thermal noise ${{\mathrm{dv}}_{R_{\mathrm{1,2}}}}^2=4k{\mathrm{TR}}_{\mathrm{1,2}}\&CenterDot;\mathrm{df},$ They also contribute to phase noise. Using a method similar to the derivation of the charge pump, the power spectral densities of the SSB phase noise introduced by the two resistors can be derived as:

${\mathrm{<span\; class="notranslate">\; \&Gamma;</span>}}_{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; \{</span>\mathrm{<span\; class="notranslate">\; \&Delta;\&omega;</span>}<span\; class="notranslate">\; \}</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; Kv</span>}}{{\mathrm{<span\; class="notranslate">\; \&Delta;\&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}{\mathrm{<span\; class="notranslate">\; \&tau;</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; kT</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 19</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; \&Gamma;</span>}}_{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; \{</span>\mathrm{<span\; class="notranslate">\; \&Delta;\&omega;</span>}<span\; class="notranslate">\; \}</span><span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>{<span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; Kv</span>}}{{\mathrm{<span\; class="notranslate">\; \&Delta;\&omega;</span>}}^{\mathrm{<span\; class="notranslate">\; 2</span>}}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span>\frac{\mathrm{<span\; class="notranslate">\; 4</span>}\mathrm{<span\; class="notranslate">\; kT</span>}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 20</span>}<span\; class="notranslate">\; )</span>$

It can be seen from equations (19) and (20) that in order to reduce the single-sideband phase noise introduced by resistors Rl and R2 in the loop filter, Rl and R2 should take as large a value as possible, and capacitors C2 and _τ2 should also be Should take as large a value as possible. In addition, equations (18) to (20) show that the SSB phase noise introduced by the charge pump and resistor R1 is inversely proportional to the sixth power of the deviation frequency Δω, while the SSB phase noise introduced by the resistor R2 is proportional to the deviation frequency The fourth power of Δω is inversely proportional, which means that resistor R2 will introduce greater phase noise.

Under the condition that the actual available component values are limited, the value of each component in the final realized loop filter is:

R ₁ =15KΩ, C ₁ =200pF, C ₂ =10pF, R ₂ =2KΩ, C ₃ =2pF, then the loop bandwidth is about 100kHz, and the phase margin is about 51 degrees. Substitute various parameters into formulas (18)~(20), and assume Kv=100MHz/V, T=300K, α _p =0.1, then:

Γ _P {3MHz}＝-114.38dBc/Hz

${\mathrm{\&Gamma;}}_{R_1}\left\{3\mathrm{MHz}\right\}=-115.17\mathrm{dBc}/\mathrm{Hz}$ (twenty one)

${\mathrm{<span\; class="notranslate">\; \&Gamma;</span>}}_{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; \{</span>\mathrm{<span\; class="notranslate">\; 3</span>}\mathrm{<span\; class="notranslate">\; MHz</span>}<span\; class="notranslate">\; \}</span><span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 114.90</span>}\mathrm{<span\; class="notranslate">\; dBc</span>}<span\; class="notranslate">\; /</span>\mathrm{<span\; class="notranslate">\; Hz</span>}$

The frequency synthesizer of this embodiment can be implemented using a 0.25um CMOS process, which provides five layers of metal wiring, wherein the chip area occupied by the analog part of the RF frequency synthesizer is about 0.7×1.5mm ² , and the chip uses 48 tubes Leg QFN (Quad Flat No-Lead) package.

In order to test the frequency synthesizer, an FPGA test board is designed. There are three SMA connectors on the test board of the RF frequency synthesizer, which are respectively connected to the output of the internal voltage-controlled oscillator and the output of the dual-mode prescaler. terminal and the input terminal of the external voltage-controlled oscillator. The programmable device used in this FPGA test board is the SPANTAN XL chip of Xilinx Company, and the normal working voltage is 3.3V. The FPGA test board controls the working mode and output frequency of the frequency synthesizer through a three-wire serial interface.

In this embodiment, a crystal oscillator of 11.0592 MHz is used as a reference frequency source. Since a channel bandwidth of about 1 MHz is to be obtained in this embodiment, the frequency source is internally divided by 11, and the actual reference frequency is 1.0053818 MHz. By controlling the count value of P counter and S counter, the output frequency of the frequency synthesizer can be adjusted. A low-frequency reference frequency source will introduce harmonics to the output spectrum of the RF frequency synthesizer and increase the phase noise of the oscillating signal. When the frequency synthesizer is applied to an actual system, the actual reference frequency should be selected as high as possible according to the channel bandwidth requirements (for example, in the IEEE802.11b system, the channel bandwidth is 22MHz, and the actual reference frequency should be set to 22MHz) .

The oscillation frequency of the internal voltage-controlled oscillator can vary within the range of 1.77GHz to 2.00GHz, but the locking range of the frequency synthesizer is only 1.82GHz to 1.96GHz. Figure 9 shows the output spectrum of the frequency synthesizer in a locked state. At this time, the output frequency is 1924MHz, and the output amplitude can reach -3.50dBm. It can be seen from the figure that there are many harmonics in the output spectrum of the frequency synthesizer, which are caused by the interference of the reference frequency. The harmonics with the largest energy appear at 11MHz on both sides of the center frequency, and the frequency synthesizer's rejection rate for these two harmonics is only -20dBc.

Figure 10 shows the waveforms at the two input terminals of the frequency and phase detector observed with an oscilloscope in this locked state. Among them, (a) is the waveform after frequency division of the voltage-controlled oscillator output signal, and (b) is the waveform of the crystal oscillator output signal after frequency division. Their frequencies are equal, indicating that the entire frequency synthesizer has entered a locked state.

In this locked state, when the deviation from the center frequency is greater than the loop bandwidth (about 100kHz) but less than 3MHz, the phase noise of the frequency synthesizer is mainly generated by the 1/f noise up-conversion of the internal voltage-controlled oscillator. In the ω ^-3 region, the phase noise at 3MHz away from the center frequency reaches -100.83dBc/Hz at a rate of 30dB/dec. Outside this frequency, the phase noise of the frequency synthesizer enters the ω ^-2 region and drops at a rate of 20dB/dec. At this time, the noise mainly comes from the thermal noise of the components of the internal voltage-controlled oscillator. Using extrapolation, it can be deduced that The phase noise at 25MHz away from the center frequency is about -119.25dBc/Hz, which can already meet the requirements of IEEE802.11b for the phase noise of the frequency synthesizer (the phase noise performance at 25MHz away from the center frequency should be better than -118.4dBc /Hz). When the offset frequency is within the loop bandwidth, the phase noise of the frequency synthesizer mainly comes from the reference frequency source and the internal voltage-controlled oscillator. At 30kHz from the center frequency, the phase noise reaches the maximum value, about -57dBc/Hz.

In addition to the noise of the reference frequency source and the internal voltage-controlled oscillator, which play a major role in and outside the loop bandwidth, the charge pump, the resistors R1 and R2 of the loop filter, and the digital circuit all play an important role in reducing the phase noise of the frequency synthesizer. Influence. In addition, the equipment used in the test will also introduce a lot of noise, all of which limit the phase noise performance of the frequency synthesizer.

When the digital circuit part of the frequency synthesizer of the present invention uses a 2.5V power supply and the analog part uses a 2.7V power supply, the total current consumed by the analog part of the frequency synthesizer is about 48mA. The current consumed by each module is: the internal voltage-controlled oscillator is about 3.2mA; the output buffer circuit of the two internal voltage-controlled oscillators is about 16mA; the interface circuit of the internal voltage-controlled oscillator and the dual-mode prescaler is about 10.5mA ; The dual-mode prescaler is about 15.7mA; the frequency and phase detector and the charge pump are about 2.5mA; the constant transconductance source is about 0.1mA.

It can be seen from the above test results that the integrated phase-locked loop frequency synthesizer proposed by the present invention can realize the function of frequency synthesis, and has high performance, and can be applied in the field of wireless communication.

Claims (3)

1, an integrated radio frequency phase-locked loop type frequency synthesizer, it is characterized in that, by adopting CMOS technology to be integrated on the digital unit part on a chip, analog unit part and the loop filter realized by off-chip components, wherein, The digital unit components include; R programmable counter, P programmable counter, S programmable counter, three-wire serial interface circuit, shift register and power consumption controller; the analog unit includes: frequency and phase detector, dual-mode pre- Frequency divider, voltage-controlled oscillator, charge pump and constant transconductance source; the connection relationship of each device of this frequency synthesizer is: the output end of said voltage-controlled oscillator is connected with the input end of dual-mode prescaler, the The output terminal of the dual-mode prescaler is connected with the input terminal of the programming P counter and the programmable S counter respectively, the output terminal of the S counter is connected with the input terminal of the dual-mode prescaler, and the output terminal of the P counter is respectively connected with the S counter The input terminal of the programmable R counter is connected to the input terminal of the frequency and phase detector, and the input of the programmable R counter receives the crystal oscillator signal input by the reference frequency source, and the output terminal of the programmable R counter is connected to the input terminal of the frequency and phase detector. The output end of the frequency and phase detector is connected to the input end of the charge pump, and the output end of the charge pump is connected to the input end of the voltage-controlled oscillator through a loop filter; the shift register is connected to the three-wire serial interface It is used to control the frequency division ratio of the three counters R, S and P and to control the working mode of the entire frequency synthesizer; the power management module provides enable signals for each sub-module, and the constant transconductance source provides each The analog unit part provides the bias, and finally the required signal is obtained from the output of the voltage controlled oscillator. 2. The integrated RF phase-locked loop frequency synthesizer as claimed in claim 1, further comprising a selection circuit of an off-chip voltage-controlled oscillator and internal/external voltage-controlled oscillator mode; the selection circuit consists of Transistors MS1-MS16, DC blocking capacitors CS3, CS4, resistors RS5, RS6 and inductor LS1 are composed; the connection relationship of each device is: the signal INT_VCO from the internal voltage-controlled oscillator is input to the gate of transistor MS1, and the source of MS1 is grounded , the drain is connected to the load resistor RS5 and one pole of the DC blocking capacitor CS3; the gate of the transistor MS5 is connected to the power consumption control signal EN1B, the source is connected to the power supply VDD, the drain is connected to the source of the transistor MS6, the gate of the transistor MS6 and The other end of capacitor CS3 is connected to the drain of transistor MS6, the drain of MS7, the gate of MS7, the gate of MS10, and one end of CS4; the source of MS7 is connected to the drain of MS8, and the gate of MS8 is connected to the power consumption control The gates of signals EN1 and MS9, the source of MS8 are grounded; the drain of MS9 is connected to the source of MS10, the source of MS9 is grounded, one end of the inductor LS1 on the drain of MS10 and the output to the dual-mode prescaler Interface Fdmp, the source of transistor MS13 is grounded, the drain is connected to its gate, the gate of MS11 is connected to the source of MS14, the drain of MS14 is connected to the gate of MS14, the gate of MS12 is connected to the drain of MS15, and the gate of MS15 is connected The gate is connected to the bias signal VP2, its source is connected to the drain of MS16, the gate of MS16 is connected to the control signal ENP, its source is connected to the power supply VDD, the drain of MS11 is connected to the external voltage-controlled oscillation signal EXT_VCO and the source of MS12, The source of MS11 is grounded, the drain of MS12 is connected to one end of RS6 and one end of CS4, and the other end of RS6 is connected to VDD. 3. The integrated radio frequency phase-locked loop frequency synthesizer as claimed in claim 1, wherein said dual-mode prescaler is controlled by a synchronous 4-frequency divider/5-frequency divider, an asynchronous counter and The logic circuit is composed; wherein, the voltage-controlled oscillating signal is respectively connected to the CLK input terminals of the two NOR triggers and the D flip-flop, and the Q+ output terminal of the D flip-flop is connected to the D1 input terminal of the first NOR trigger, Its Q- output terminal is connected to the D1 input terminal of the second NOR gate trigger; the D2 input terminal of the first NOR gate trigger is connected to the Q+ output terminal of the second NOR gate trigger, and its Q+ output terminal is connected to The D input terminal of the D flip-flop and the input terminal of the asynchronous counter, the D2 input terminal of the second NOR gate trigger is connected to the output of the control logic, and the output terminals Q- of the first and second NOR gate triggers are all suspended , the input of the control logic is provided by the asynchronous counter, and the asynchronous counter provides the frequency division signal at the same time.

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