CN1280891C - Non-volatile memory structure and method of manufacturing the same - Google Patents

Abstract

In the non-volatile memory of the present invention, the select gate is a self-aligned partition formed over the sidewall of the floating/control gate stack, the same mask (1710) can be used to perform the steps of removing the select gate layer from over the source line (144), etching the trench insulation layer in the source line region, doping the source line, etc., the memory can be formed in or over a separate substrate region, and the source line can be at least partially doped before etching the trench insulation layer, thereby isolating the substrate region from the underlying structure to avoid short circuits; such memories can be erased in blocks (sectors); or performing a chip erase operation to erase all the cells in parallel; the peripheral transistor gate and the select gate can be formed from the same layer, and the select gate wall has an extension for making a low resistance contact from the upper metal line; when the upper insulating layer is mechanically or chemically mechanically polished, the circuit elements above the semiconductor substrate can be protected by the adjacent dummy structures.

Description

Non-volatile memory structure and method of manufacturing the same

technical field

The invention relates to a semiconductor technology, in particular to a non-volatile memory structure and a manufacturing method thereof.

Background technique

In the past, when manufacturing non-volatile flash memory, a very typical process-local oxidation of Silicon (LOCOS) process was often used to isolate and arrange various components (such as bit lines) on the chip. However, the process of local silicon oxidation often produces a bird's beak-shaped oxide layer. We must reserve space for this protruding structure, but the size of this protruding structure accounts for a considerable proportion of the bit line pitch, making the device The distance between them cannot be further reduced, and the misalignment step becomes the main factor limiting the size of the component. In view of this, a so-called shallow trench isolation (shallow trench isolation, STI) technology was developed accordingly, which can effectively improve this situation in a self-aligned manner.

1 to 8 illustrate the fabrication method of a conventional non-volatile stacked gate flash memory described in US Patent No. 6,013,551 issued to J. Chen et al. on January 11, 2000. A silicon dioxide layer 108 (also called a tunnel oxide layer (tunnel oxide layer), which will be referred to as an oxide layer in the following description) is grown on the P-doped silicon substrate 150, and a doped Complex polysilicon layer 124, the polysilicon layer 124 will form the floating gate of the memory cell transistor.

Next, a mask 106 is formed on the surface of the structure, and the polysilicon layer 124, the oxide layer 108, and the substrate 150 are etched downward through the opening of the mask, so that a plurality of trenches 910 are formed in the substrate 150 (as shown in FIG. 2 ). .

As shown in FIG. 3, the dielectric material is filled into the trench 910 and covers the entire structure. The detailed steps are as follows: first grow the silicon dioxide layer 90 by thermal vaporization, and then use plasma enhanced chemical vapor deposition (plasma enhanced A silicon dioxide layer 94 is deposited by chemical vapor deposition (PECVD), and then a thicker silicon dioxide layer 96 is deposited by subatomspheric chemical vapor deposition (SACVD).

Next, a chemical mechanical polishing (CMP) step is performed on the structure, as shown in FIG. 4 , to expose the polysilicon layer 124 .

Regarding chemical mechanical polishing, we will give a little explanation here. Before the insulating layer is patterned or the next layer will be deposited, it is necessary to planarize the top surface of the insulating layer, because doing so relaxes the depth of focus requirements of the lithographic equipment used to pattern the insulating layer or the layer above, if the insulating layer With the top surface being flat, we can accept greater variability in the depth of focus, which is especially important for the fabrication of small-scale items with lithography equipment.

The chemical mechanical polishing method is widely used in the planarization process because the chemical mechanical polishing method is very fast and does not need to be performed at high temperature.

The insulating layer processed by chemical mechanical polishing usually stops at the harder layer below the insulating layer. For example, when processing the silicon dioxide layer by chemical mechanical polishing, an oxide layer can be deposited before the silicon dioxide layer. Silicon layer, as a stop layer, please refer to US Patent No. 5,909,628 "REDUCING NON-UNIFORMITY IN A REFILL LAYER THICKNESSFOR A SEMICONDUCTOR DEVICE" published on June 1, 1999.

Next, as shown in FIG. 5 , an ONO (silicon oxide, silicon nitride, silicon oxide) layer 98 is formed on the structure, and then a silicon layer 99 is deposited thereon, and then a tungsten silicide layer 100 is deposited.

Then form a mask (not shown), and pattern the above-mentioned layers 100, 99, 98, and 124 (as shown in Figure 6). At this time, the polysilicon layer 124 will become a floating gate, and the silicon layer 99 and silicide The tungsten layer 100 will be a control gate and a wordline respectively.

As shown in FIG. 8, a mask 101 is then formed on the structure, and part of the oxide layers 90, 94, and 96 (as shown in FIG. 7 ) are removed by etching using the mask 101. After etching, the mask 101 is retained for planting dopant to form the source line 103 .

Additional implantation steps are then performed to properly dope the source and drain regions.

Although the above method can reduce the size of the memory, it is still necessary to reduce the size of the memory with the evolution of the manufacturing process and the limitation of the line width.

Contents of the invention

The object of the present invention is to provide a method for manufacturing an integrated circuit including a non-volatile memory, which uses multiple self-alignment steps to form a polysilicon layer (floating gate, control gate, selection gate), and through the self-alignment of the three gates The alignment and mutual arrangement can further reduce the gate pitch of the bit line, and further reduce the size of the memory.

According to the above purpose, an embodiment of the present invention provides a method for manufacturing an integrated circuit including a non-volatile memory, and the method includes the following steps:

(a) forming a first insulating layer and a first layer on a first region of a semiconductor, wherein the integrated circuit includes a plurality of non-volatile memory cells, each of the memory cells includes a portion of the first layer The formed floating gate;

(b) forming a plurality of trenches in the semiconductor first region through openings of the first layer, and filling the trenches with an insulating material;

(C) forming a second layer over the semiconductor first region, wherein each of the cells includes a conductive gate formed partly of the second layer, the conductive gate and the floating gate of the cells isolated by a second insulating layer;

(d) patterning the second layer to form strips extending in a predetermined direction, each strip spanning a plurality of the grooves;

(e) removing a portion of the first layer on the semiconductor first region not covered by the second layer to form a plurality of first structures, each of the first structures comprising a layer formed by the second layer strips comprising a portion of the first layer below the strips, and each of the first structures has a first side wall;

(f) forming a third layer on the first layer and the second layer, and removing part of the third layer with a process including anisotropic etching, so that at least each of the first structures A partition is formed on part of the first side wall, wherein each partition is separated from the material of the first layer and the second layer in the corresponding first structure by an isolation material;

(g) forming a lithography mask pattern using lithography, the lithography mask pattern covering the partition wall on the first sidewall of the first structure;

(h) using the lithographic mask pattern as a mask to remove the partition not covered by the lithographic mask pattern, so that each of the cells includes a first side wall formed by the first structure The conductive gate formed by the partition on the

(i) Doping dopants in the semiconductor first region by using the lithography mask pattern as a mask.

Before forming the second layer, the first layer forms strips at an angle to the predetermined direction and the grooves pass through a row of non-volatile memory cells in the same direction as the strips.

The method of forming the first layer further includes:

lithographically patterning a lithographic mask pattern on the first layer to define the strips of the first layer; and

The grooves are defined by the lithographic mask pattern described above.

In the above method:

Each of the first structures includes a second sidewall;

The lithographic mask pattern process includes depositing and lithographically patterning a lithographic mask pattern to cover at least part of the partition on the first sidewall of the first structure and cover the adjacent first structure. A first semiconductor substrate and a region between the first sidewalls.

Each of the second semiconductor substrate regions extends between two adjacent first structures, and provides a joint portion of source/drain regions of all memory cells between two adjacent first structures, wherein the source/drain regions The drain regions are electrically connected to each other.

The above method further includes using the lithography mask pattern to completely or partially etch away the insulating material in the trench in the second semiconductor substrate region.

After completely or partially etching away the insulating material in the trench, it further includes removing the photolithography mask pattern, and doping dopants in the first and second semiconductor substrate regions.

The first layer includes a polysilicon layer, and the second layer includes a polysilicon layer and a metal silicide layer.

In the above method:

Before forming the second layer, the first layer has a plurality of rectangular openings, but the area where the source line will be formed is covered by the first layer;

The trench is formed by etching down the semiconductor first region from the rectangular opening; and

Step (e) includes removing the first layer from over the source line region.

The above method further includes the following steps to form the second metal oxide semiconductor transistor:

When forming the first insulating layer and the first layer on the first region of the semiconductor, the first insulating layer and the first layer are also formed on a second region of the semiconductor at the same time:

removing the first layer and the first insulating layer of the second region of the integrated circuit;

When step (c) is performed, a second insulating layer is also formed on the second region;

When step (c) is performed, a second layer is also formed on the second insulating layer in the second region to form a second metal-oxide-semiconductor transistor.

The thickness of the second insulating layer is different from that of the first insulating layer.

The above-mentioned method further comprises the following steps of the third metal-oxide-semiconductor transistor:

When forming the first insulating layer in the first region and the second region, the first insulating layer is also formed in the third region at the same time;

removing the first insulating layer from the second and third regions and forming a third insulating layer on the second and third regions before forming the first layer; and

When the first layer is removed from the second region, the first layer at the first and third regions is simultaneously patterned to provide conductive gates for the first and third MOS transistors.

After forming the second layer, the first insulating layer, the second insulating layer, and the third insulating layer have different thicknesses.

When forming the third insulating layer, the thickness of the first insulating layer located in the first region will increase.

The integrated circuit includes a non-volatile memory cell including (a) a conductive gate formed from part of the first layer and (b) a conductive gate formed from the second layer.

Before the step of forming the first insulating layer, it further includes:

forming a gate insulating layer on the semiconductor substrate, the memory cell will be formed in a region of the integrated circuit;

forming a conductive layer on the gate insulating layer to provide a floating gate for the memory cell; and

The conductor layer and the gate insulating layer are removed from the first and second regions.

The above method further includes forming an insulating layer above the conductive layer to isolate the conductive layer from the first layer.

The present invention also provides a method of manufacturing an integrated circuit including a non-volatile memory, the method comprising:

forming an insulating layer, wherein the integrated circuit includes a plurality of non-volatile memory cells, and the insulating layer (108) is used as a gate insulating layer of the non-volatile memory cells;

forming a first layer as a floating gate for the non-volatile memory cells;

forming an insulating layer on the floating gate on the first layer of the memory cells;

Remove the insulating layer on the floating gate, the first layer and the insulating layer in order from the high voltage area, high speed area, and I/O (output and output) area around the non-volatile memory cell of the integrated circuit, for At least one peripheral metal-oxide-semiconductor transistor is formed on each of the high-voltage area, the high-speed area, and the I/O (output-input) area;

forming a first gate insulating layer in the high-voltage area, high-speed area, and I/O area;

removing the first gate insulating layer from the high speed area, I/O area;

forming a second gate insulating layer in the high-speed area and the I/O area;

A second layer is formed on the upper insulating layer of the floating gate, the first gate insulating layer, and the second gate insulating layer, wherein the metal oxide semiconductor transistor located in the high voltage region has a part of the second layer forming a conductive gate;

removing the second layer and second gate insulating layer from the I/O region;

forming a third gate insulating layer in the I/O region; and

High temperature oxidation of the first layer and the second layer on the side wall of the memory cell;

forming a third layer on the memory cells and metal-oxide-semiconductor transistors in the high-voltage area and the high-speed area;

forming a lithography mask pattern on the I/O region to define a metal oxide semiconductor transistor;

Applying anisotropic etching to make the third layer form partition walls on the side walls of the memory cells, the metal oxide semiconductor transistors in the high voltage region and the metal oxide semiconductor transistors in the high speed region;

forming another lithography mask pattern to protect the partition walls on each side of the memory cells;

removing all of the unpatterned third layer for forming metal oxide semiconductor transistors on the I/O region;

Wherein the first gate insulating layer located in the high voltage region is thicker than the second gate insulating layer and also thicker than the third gate insulating layer, and the third gate insulating layer is thicker than the second gate insulating layer The insulation is thick.

The above method further includes forming a dummy structure around the I/O region, the dummy structure being the same as the metal oxide semiconductor transistor in the high speed region, and removing the dummy structure from the I/O region after the second layer step is formed. Before the steps of the second layer and the second gate insulating layer, a protective layer is formed on the metal oxide semiconductor transistors in the high voltage region, the high speed region and the memory cells to protect the metal oxide semiconductor transistors in the I/O region. the third floor.

Description of drawings

1 to 7 are process cross-sectional views of a conventional flash memory;

Fig. 8 is a top view of the memory of Fig. 1 to Fig. 7;

9A is a top view of an embodiment of a memory according to the present invention;

9B and FIG. 9C are cross-sectional views of the memory of FIG. 9A;

FIG. 10A is a circuit diagram of the memory of FIG. 9A;

Figure 10B is a top view of the memory of Figure 9A;

11 and FIG. 12A are process cross-sectional views of the memory of FIG. 9A;

Figure 12B is a top view of the structure of Figure 12A;

13 to 15 are process sectional views of the memory of FIG. 9A;

FIG. 16 is a perspective view of the memory of FIG. 9A during the manufacturing process;

17A to 22B are process cross-sectional views of the memory of FIG. 9A;

Fig. 22C is a top view of the structure of Fig. 22A and Fig. 22B;

23A to 24C are cross-sectional views of the memory embodiment of the present invention during the manufacturing process;

25 to 26C are cross-sectional views of memory embodiments of the present invention;

27 to 29 are top views of memory embodiments of the present invention;

30A and 30B are cross-sectional views of memory embodiments of the present invention;

Figure 30C shows a mask layout for a memory embodiment of the present invention;

31A to 33B are cross-sectional views of memory embodiments of the present invention;

Figure 34 is a top view of an embodiment of a memory of the present invention;

Figure 35 and Figure 36 are process sectional views of the memory of Figure 34;

Figure 37 and Figure 38 are top views of the memory in Figure 34 during the manufacturing process

39 to 41 are process sectional views of the memory of FIG. 34;

Fig. 42 is a top view of the memory embodiment of the present invention during the manufacturing process;

Figure 43 is a block diagram of a voltage generator used in a memory embodiment of the present invention;

44 to 61 are process cross-sectional views of the memory embodiment of the present invention.

98, 1010, 1810, 2901, 2903, 3003: insulating layer

98.1, 98.3, 1510, 1810, 2710, 4408, 4410: silicon dioxide layer

98.2, 720, 903, 1203, 2607: silicon nitride layer

103: Source line

108: Tunnel oxide layer (can be a silicon dioxide layer)

110: Semiconductor Structures

113: dielectric layer

120: memory cell

120S: select transistor

120F: floating gate transistor

124: Floating gate (formed of polysilicon, in order to match the illustration, sometimes it will be called polysilicon layer, or floating gate line)

128: Control gate (in order to cooperate with the illustration, it is sometimes called the control gate line)

128.1: Polycrystalline silicon layer

128.2: Tungsten silicide layer

128A: Section

130: bit line

133: Source/drain region

134, 312: bit line area

138: Bit line contact area

141: Virtual structure

144: Source line

144C, 29003C: contact opening

150: substrate area

520: word line (formed by polysilicon, in order to match the illustration, it will be called a polysilicon layer or a selection gate in some cases)

520E: Lateral Raised

710: A stack structure (or column structure) including floating gates and control gates

901: memory array

904, 1014, 1710, 2501, 2810, 4501, 4601, 4801: photoresist mask

905: Substrate

910: Isolation Trench

1103, 1105: N-area

1107, 2709: area

1603: Surrounding area

1810: Gate Oxide

2110, 2401: Implantation

2605: Conductive material

2701, 3010: Clearance

2703.1, 2703.2: memory array segment

2903: metal belt

3301: Silicide layer

4201: Voltage generator

4402, 4404, 4406, 4404D: active area

Detailed ways

The descriptions of the preferred embodiments are for purposes of illustration and not limitation, and the present invention is not limited to any particular dimensions, materials, process steps, dopants, doping concentrations, crystallographic positions, unless otherwise specified herein. orientation, layer thickness, layout, or other component characteristics.

9A is a top view of a flash memory array of self-aligned three-gate memory cells 120, FIG. 9B is a cross-sectional view cut along line 9B-9B of FIG. 9A, and FIG. 9C is a sectional view along line 9C-9C of FIG. 9A Cutaway, Figure 10A is a circuit diagram of the array, and Figure 10B is a top view illustrating other added features.

The bit lines (bit lines) 130 in the figure extend laterally. The bit lines 130 are formed by a conductive layer (such as aluminum or tungsten, not shown) above the memory cell 120. The bit lines 130 are connected to the memory cell 120. The bit line region 134 of the cell 120 contacts in the bit line contact region 138. The source lines 144 extend longitudinally between adjacent column structures 710. Each column structure 710 includes a longitudinal control gate line. (control gate Line) 128, as the control gate of each row of memory cells, the control gate line 128 in this embodiment is composed of a polysilicon layer 128.1 and a tungsten silicide layer 128.2, and the polysilicon floating gate 124 is located Below the control gate 128 , each floating gate is located in an adjacent isolation trench 910 , and the trench 910 is located between the bit lines 130 laterally.

Each column structure 710 is a self-aligned stack.

The word line 520 (such as a doped polysilicon layer) is perpendicular to the bit line 130 (or at a special angle). Each word line 520 can be used as a selection gate for a column of memory cells. Each word line 520 is a self-aligned partition formed on the sidewall of the corresponding stack structure 710, the word line 520 is separated from the adjacent control gate 128 and floating gate 124 by the silicon oxide partition 903 and the silicon dioxide layer 1510, and 903 and 1510 layers can be generated without mask only.

As shown in Figure 10A, the memory cells of each column have two cells 120 between two adjacent bit lines 130, wherein each memory column has a control gate line 128 and a word line 520, two Adjacent memory columns share a source line 144. In each memory cell 120, an NMOS selection transistor 120s and a floating gate transistor 120F are connected in series, and the gate of the selection transistor 120s is provided by a word line 520. , and the control gate of the floating gate transistor 120F is provided by the control gate line 128 .

We can erase each cell by Fowler-Nordheim electron tunneling from floating gate 124 through silicon dioxide layer 108 to source line 144 or substrate region 150 (region 150 includes the channel region of the memory cell), and Cells can be programmed by hot electron injection at the source terminal. The term "source terminal hot electron injection" assumes that the bit line region 134 of the cell is the "source". In another case, if this region is drain, the source line region 144 is the source, and the regions 134 and 144 can be referred to as source/drain regions, and we do not use specific terms to limit the present invention.

The memory is formed in and above the independent P-type region 150 of the silicon substrate 905 (as shown in FIG. 11 ). The silicon substrate 905 is formed of single crystal silicon or other semiconductor materials. In some embodiments, the substrate 905 The top surface has a crystal orientation of <100>, and the substrate is doped with boron at a concentration of 2E15 to 2E16 atoms/cm ³ .

The method for generating the region 150 is as follows: implant N-type dopants in the substrate 905 through the mask opening by ion implantation to form the N-region 1103, which can isolate the region 150 from the underlying structure. For example, the ratio of 1.5 The energy of MeV and the dosage of 1.0E13atom/cm ² implant phosphorus.

In a single ion implantation step or a series of ion implantation steps, an additional mask (not shown) is used to implant N-type dopants to form N-region 1105, which completely surrounds region 150 As a matter of fact, in some embodiments, this step can simultaneously create N-wells (not shown) in which peripheral PMOS transistors will be formed for peripheral circuits such as sense amplifiers, input/output drivers, Decoders, voltage generators, etc. It is known in CMOS technology to fabricate such N-wells.

When the memory is in operation, the voltage of the N-regions 1103 and 1105 is the same as or higher than the voltage of the substrate region 150. Table 1 below shows the reference voltage of the region 150, and the voltage of the region 1107 of the substrate 905 is the same as the voltage of the regions 1103 and 1105. Or lower, in some embodiments, regions 150, 1103, 1105 are connected together to form a short circuit, and region 1107 is additionally connected to ground.

The present invention does not specifically limit the isolation technology of the region 150, nor is it limited to a memory with an independent substrate region.

As shown in FIG. 12A, a silicon dioxide layer (or called a tunnel oxide layer, sometimes simply referred to as an oxide layer) 108 is formed by thermal oxidation on the top surface of the substrate region 150, and in some embodiments, it is about 800 ℃ dry oxidation method to grow a thick 9um oxide layer.

Next, a polycrystalline silicon layer 124 is formed on the top surface of the oxide layer 108. In some embodiments, a layer of polycrystalline silicon layer 124 with a thickness of 120 μm is deposited by low pressure chemical vapor deposition (LPCVD), Lightly doped (N-type) at the time of deposition or after, the above-mentioned polysilicon layer 124 will be used as a floating gate, or can be used as other circuit components of peripheral circuits, such components include interconnection lines, transistor gates, etc. poles, resistors, capacitor plates, etc.

Continue to deposit a silicon nitride layer 1203 on the top surface of the polycrystalline silicon layer 124. In some embodiments, a layer of nitride with a thickness of 120 nm is deposited by low pressure chemical vapor deposition. A silicon dioxide layer (not shown) is formed on the polysilicon layer 124 prior to the compound to reduce stress.

Then, a photoresist mask 904 is formed on the silicon nitride layer 1203 by lithography, and the silicon nitride layer 1203 and the polysilicon layer 124 are etched from the opening of the mask, thereby forming a memory array through the same direction as the bit line. In the top view of FIG. 12B, the "BL" axis points to the direction of the bit line, while the "WL" axis points to the direction of the word line. In some embodiments, the reactive ion etching The polysilicon layer 124 and the silicon nitride layer 1203 are etched by reactive ion etching process (RIE).

Even if the photoresist mask 904 is misaligned, it will not affect the cell geometry. Even if it needs to be adjusted, it only needs to be adjusted at the edge of the array and the peripheral area (the area where the peripheral circuits are located).

After etching the polycrystalline silicon layer 124, the oxide layer 108 and the substrate region 150 are etched from the opening of the photoresist mask 904 to form isolation trenches 910 (as shown in FIG. 13 ), isolation trenches for peripheral circuits (not shown) It is also formed in this step, and the etching method can choose reactive ion etching, and the groove depth is about 0.25nm.

The photoresist mask 904 is then removed.

As long as it is mentioned here that a two-layer or multi-layer structure is etched using a mask, unless it is specifically mentioned, it will only etch the uppermost layer using this mask. When the uppermost layer is etched away, remove the mask, and then use the remaining The lower uppermost layer is used as a mask, and the remaining layers are etched, or no mask is needed at all. For example, after etching the silicon nitride layer 1203, the first resist mask 904 is removed, and then the silicon nitride layer 1203 As a mask, etch the underlying polysilicon layer 124 , oxide layer 108 , and substrate 150 , and part of the silicon nitride layer 1203 may be etched at the same time, but not completely removed.

Fill trench 910 with trench insulating material to form an insulating layer 1010 and cover the wafer (as shown in FIG. 13 ). In some embodiments, insulating layer 1010 may be formed by the following methods: over the exposed surface of trench 910 A silicon monoxide layer with a thickness of 13.5um is formed by known rapid thermal oxidation (rapid termal oxide, RTO), and then high density plasma (high density plasma, HDP) chemical vapor deposition (chemical vapor deposition, CVD) to deposit a silicon dioxide layer with a thickness of 480nm.

Then use chemical mechanical polishing (CMP) and/or some comprehensive etching processes (blanketetch process) to etch and remove part of the insulating layer 1010 until the silicon nitride layer 1203 is exposed (as shown in FIG. 14 ), wherein the silicon nitride layer 1203 is used as an etch stop layer in this step. Then remove the silicon nitride layer 1203 (such as by wet etching), or etch the insulating layer 1010, which can use timed wet etching (timed wet etch), the final structure will be as shown in Figure 15, a flat or the sidewall of the polycrystalline silicon layer 124 can be exposed by etching the insulating layer 1010, which will improve the efficiency of the memory cell, which will be described later.

Next, an insulating layer 98 is formed (as shown in FIG. 9B and FIG. 9C ). In some embodiments, the insulating layer 98 is an oxide-nitride-oxide (ONO) structure, and its formation method is as follows: first, in The silicon dioxide layer 98.1 (as shown in FIG. 16 ) is formed on the polycrystalline silicon layer 124 by dry oxidation method at 800° C. or lower temperature. The reference thickness of the silicon dioxide layer 98.1 is 6 μm, and then the A silicon nitride layer 98.2 with a thickness of 4um is deposited by deposition method, and then a silicon oxide layer 98.3 is formed by heating at a temperature lower than 850° C. by wet oxidation method.

In FIG. 16, the silicon dioxide layer 98.3 is also used as the gate insulating layer of the peripheral transistor. Before forming the silicon dioxide layer 98.3, a photoresist mask (not shown) is formed on the memory array. The mask has no Cover the peripheral region 1603, etch away the layers 98.2, 98.1, 124, and 108 of the peripheral region 1603 to expose the substrate 905, then remove the mask, oxidize the wafer to generate a silicon dioxide layer 98.3, and the silicon dioxide layer 98.3 in the peripheral region 1603 The reference thickness of the silicon layer 98.3 is 24nm, while the silicon monoxide layer 98.3 above the silicon nitride layer 98.2 in the memory area is 1nm thick, and the silicon monoxide layer 98.3 above the silicon nitride layer 98.2 is relatively thin, this is because two The growth rate of silicon oxide on nitride is slower than that on silicon substrate 905 .

A polysilicon layer 128.1 is formed above the insulating layer 98. In some embodiments, a polysilicon layer 128.1 with a thickness of 80 um is deposited by a low-pressure chemical vapor deposition method, and is doped with N+ or P+ during or after deposition, and then A tungsten silicide layer 128.2 is deposited, with a reference thickness of 50nm. The tungsten silicide layer 128.2 can be formed by chemical vapor deposition, and then a silicon nitride layer 720 is deposited on the wafer. The nitride layer 720 can be formed by a low-pressure chemical vapor deposition method, with a thickness of about It is 160um.

In some embodiments, one of the polysilicon layer 128.1 and the tungsten silicide layer 128.2 can be omitted or replaced by other materials.

Next, a photoresist is formed on the surface of the silicon nitride layer 720, and the photoresist is patterned to form long strips, which are in the same direction as the word lines on the memory array. This photoresist mask 1014 will be used to form the stack structure 710. The resist mask 1014 can also pattern the peripheral transistor gates 128.1, 128.2, and the silicon nitride layer 720 of the peripheral region 1603. The misalignment of the photoresist mask 1014 will not change the geometric structure of the memory cell, only need to adjust The boundary and surrounding area of the memory array are sufficient.

Etch 720, 128 (namely 128.1 and 128.2), 98 layers to define the stacked structure 710, the available etching method is anisotropic reactive ion etching method, and then remove the first resist mask 1014, and then form on the peripheral area 1603 Another photoresist mask (not shown), using the silicon nitride layer 720 as a mask to etch the underlying polycrystalline silicon layer 124 and oxide layer 108, the photoresist will protect the silicon substrate 905 in the peripheral active area, and then peel off Photoresist, Figure 17A and Figure 17B show the sectional view of the generated memory array, its section is parallel to the bit line, these sections are taken along the arrows 17A and 17B in Figure 16 respectively, the section in Figure 17B is cut along the trench 910 Next, the section in FIG. 17A is cut along the position between adjacent grooves.

Similarly, the sections of Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 31A, Fig. 32A, and Fig. 33A are cut along the position between adjacent grooves, while Fig. 18B , FIG. 19B, FIG. 20B, FIG. 21B, FIG. 22B, FIG. 23B, FIG. 24B, FIG. 31B, FIG. 32B, and FIG. 33B are cut along the groove 910.

In some embodiments, the polysilicon layer 128.1 and the tungsten silicide layer 128.2 are not used to form the peripheral transistor gate, the peripheral transistor gate is formed by the polysilicon layer deposited later, and the word line is also formed by Formed by polycrystalline silicon layer. This embodiment omits the step of etching each layer of 98.2, 98.1, 124, 108 before forming the silicon dioxide layer 98.3, and the step of protecting the memory array with a mask during etching is also omitted, when forming the photoresist mask 1014 At the same time, there are layers 108, 124, 98, 128, and 720 above the peripheral active area, which are the layers covering the active area of the memory array, and these layers are etched in the peripheral area and the memory array area at the same time, so that the silicon dioxide is etched The photoresist mask 1014 does not need to be stripped after layer 98.3, and the mask used to protect the peripheral active area when etching the polysilicon layer 124 can be omitted.

Oxidize the structure (for example, perform rapid thermal oxidation in an oxygen atmosphere at 1080° C.), so that a silicon dioxide layer 1510 with a thickness of 5 μm will be formed on the exposed surface of the substrate region 150 (as shown in FIG. 18A and FIG. 18B ), this This step simultaneously oxidizes the exposed polysilicon layers 124 and 128.1, and the silicon monoxide layer 1510 on the polysilicon sidewalls has a horizontal thickness of 8nm.

A thin silicon nitride layer 903 with a thickness of 20 μm is deposited by low-pressure chemical vapor deposition (as shown in FIG. 19A and FIG. 19B ). No mask is required, and the above-mentioned silicon nitride layer 903 can be etched anisotropically to form a stacked structure. Partition walls are formed on the side walls of 710 .

This etching step also removes the exposed silicon dioxide layer 1510 and re-grows a silicon dioxide layer 1810 over the substrate region 150 by dry oxidation at temperatures below 800° C., which is designated 1810 in FIG. 19A The silicon dioxide layer will provide the gate insulating layer of the select transistor, and the reference thickness of the silicon dioxide layer 1810 is 5nm.

In some embodiments, the step of forming the silicon nitride layer 903 or the silicon dioxide layer 1510 may be omitted.

Next, a polycrystalline silicon layer 520 is formed (as shown in FIGS. 20A , 20B, 21A, and 21B). In some embodiments, a polycrystalline silicon layer 520 with a thickness of 300 μm is deposited by a low-pressure chemical vapor deposition method. Perform heavy doping (N+ or P+) at the time of deposition or after, and perform comprehensive anisotropic etching (such as reactive ion etching) on the above-mentioned polycrystalline silicon layer 520, so as to form partitions on the side walls of the stacked structure 710, We can control the width of the polysilicon partition formed by adjusting the vertical thickness of the silicon nitride layer 720 and the polysilicon layer 520 .

In some embodiments, there are polysilicon partitions 520 on the sidewalls at both ends of the stacked structure 710. In some embodiments, the source line 144 is so narrow that the polysilicon layer 520 fills up the stacked structure above the source line. 710 without forming a spacer on the sidewall of the stack near the end of the source line.

In addition to being used as a selection gate, the polysilicon layer 520 can also be used as circuit elements of other peripheral circuits such as interconnect lines and transistor gates. For this purpose, before etching the polysilicon layer 520, it can be The surrounding area forms the mask, while no such mask is required above the memory cell.

A photoresist mask 1710 (shown in FIGS. 21A and 21B ) is formed by lithography on part of the polysilicon layer 520. This part of the polysilicon layer 520 will form word lines, and the photoresist mask 1710 can also cover Part or all of the peripheral area forms strips in the word line direction, each strip overlaps with two adjacent stacked structures 710 between adjacent source lines 144, and covers the bit line area 134, while the source Line 144 is not covered by photoresist mask 1710 .

The longitudinal edge of the photoresist mask 1710 can be located at any position on the stack structure 710 , so as long as the mask alignment error is less than half of the width of the stack structure 710 , we are not so strict about the position. In some embodiments, the minimum feature size is 0.14 mm, the mask alignment tolerance is 0.07 mm, and the width of each stack 710 is 0.14 mm, ie twice the alignment tolerance.

The polysilicon layer 520 on the side of each stacked structure 710 close to the source line is etched (as shown in FIG. 22A and FIG. 22B ), and the polysilicon partition wall 520 on the side of each stacked structure 710 close to the bit line is retained.

After the polycrystalline silicon layer 520 is etched away, the photoresist mask 1710 is reserved for implanting N-type dopants (such as phosphorus) into the wafer, as indicated by the arrow 2110 in FIG. 22A , heavily doped (N+ ) source line 144, which is a "deep" implant that allows the source line to carry a high voltage for erasing and/or programming operating voltages. When the dopant diffuses to the side, the deep implant can Appropriate overlap is formed between the source line and the floating gate 124 .

In some embodiments, the dopant will not penetrate the insulating layer 1010, so this step will not dope the bottom of the trench 910 (as shown in Figure 22B), the source line doped in this step The region is marked as "144.0" in FIG. 22C. Regardless of whether the dopant will penetrate the insulating layer 1010, the insulating layer 1010 will prevent the dopant from approaching or reaching the N-region 1103 (as shown in FIG. 11 ), thus avoiding A high leakage current or a short circuit occurs between the source line 144 and the N-region 1103 . In some embodiments, after the process is finished (ie, after the heating step), the upper surface of the N-region 1103 is about 1 mm away from the upper surface of the substrate 905 in the region 150 , and the depth of the groove 910 is 0.25 mm.

After implantation, the photoresist mask 1710 is left, and the exposed insulating layer 1010 has been completely or partially removed from the trench 910 at the source line 144 (as shown in FIG. 23B ), the silicon nitride layer 903 and the oxide Layer 1510 will protect the sidewalls of layers 124 and 128 from being exposed, and the etching method may be anisotropic etching, such as reactive ion etching. In this step, the silicon dioxide layer 1810 on the top surface of the source line 144 is simultaneously etched away (as shown in FIG. 23A ).

Then remove the mask 1710, and perform a comprehensive N+ implantation 2401 to dope the bit line region 134 and the source line 144 (as shown in Figures 24A, 24B, 9B, and 9C), the stack structure 710 and complex The crystalline silicon layer 520 covers the substrate during implantation. In some embodiments, the implant procedure step includes implanting ions at a non-zero angle to the vertical axis (the axis perpendicular to the wafer) to dope the trench sidewalls, in some embodiments at an angle of 7 °, 8° or 30°, the dopant can be arsenic.

The implantation described above does not penetrate the insulating layer 1010 near the bitline region 134, so the bitline region does not form a short circuit.

Fabrication of the memory can then be accomplished using known techniques, such as depositing an insulating layer (not shown), forming contact openings 138 (as shown in FIG. 9A ), depositing and patterning conductive materials to form bit lines, and others. must part.

As previously described with respect to FIG. 15, after grinding the insulating layer 1010, it may be etched to expose the sidewalls of the polysilicon layer 124. FIG. The cross-sectional view of the memory array of the gate 128 , the control gate 128 includes a portion 128A close to the sidewall of the floating gate 124 , so that the capacitive coupling between the control gate 128 and the floating gate 124 can be improved. In some embodiments. The polycrystalline silicon layer 124 is 120nm thick and 140nm wide. If the upper surface of the polycrystalline silicon layer 124 is about 60um above the upper surface of the insulating layer 1010, then the coupling between the control gate 128 and the floating gate 124 can be greatly improved.

It should be particularly noted that in the present invention, the floating gate 124 in the direction of the bit line is self-aligned with the active area, the control gate 128 in the direction of the word line is self-aligned with the floating gate 124, and then the selection gate (word line) 520 is self-aligned. Align the control gate 128 . Its implementation method is to use the shallow trench isolation technology to define the active area with the floating gate 124 (or directly use the active area mask to define the floating gate 124 and the active area at the same time), so that the floating gate 124 is the self-aligned active area; then use The control gate 128 above the floating gate 124 defines the floating gate 124 (or defines the thick insulating layer above the control gate 128 to define the floating gate 124 and the control gate 128 at the same time), so that the control gate 128 and the floating gate 124 are self-aligned; Finally, the select gate 520 (partition wall) is formed, because the select gate 520 is formed along the thick insulating layer above the control gate 128 , that is, the select gate 520 in the word line direction is also self-aligned to the control gate 128 below the thick insulating layer.

Using multiple self-alignment steps can not only effectively reduce the size of the memory cell, but also ensure the conductivity of each cell, although the misalignment between the selection gate 520 and the control gate 128 will not change the conductivity of the memory cell , but because the channel length between the selection gate 520 and the floating gate 124 determines the conductivity of the memory cell, the misalignment between the selection gate 520 and the floating gate 124 will affect the conductivity of the memory cell, and the design will be changed accordingly For the electrical properties of the components, such deviations can be effectively improved by using the manufacturing process of the present invention.

In some embodiments, the gates of the peripheral transistors are formed from the polysilicon layer 520 instead of the 128 layer, as mentioned earlier in relation to FIG. Before 128, the memory array is masked, and the polysilicon layer 124 and the layers 98.2, 98.1, 108 are removed from the peripheral area 1603. In the embodiment in which the polysilicon layer 520 is used to form the peripheral transistor gate, the photoresist mask 1014 does not cover the peripheral region 1603, or at least does not cover the area where the peripheral transistor gate will be formed, so when When defining the stack structure 710, the layers 108, 124, 98, 128, 720 of the peripheral region or at least the peripheral transistor gate region are etched away, exposing the substrate 905 of the peripheral active region.

The wafer is then processed as described above (as shown in FIGS. 17A-19B ), and the silicon dioxide layer 1810 will form the gate insulating layer for the peripheral transistors.

The polysilicon layer 520 is deposited as described above, and the resulting structure is shown in FIG. Resistors, etc.) to form a photoresist mask 2501 above the peripheral area, and then anisotropically etch the polysilicon 520, and then remove the photoresist mask 2501, the cross-sectional view of the peripheral area after removing the photoresist mask 2501 is shown in As shown in Figure 26A, the cross-sectional view of the memory array is shown in Figure 20A and Figure 20B

In some embodiments, the resistance of the peripheral transistor gate can be reduced by the following steps. After depositing the polysilicon layer 520 (as shown in FIG. 25 ), a layer of tungsten silicide or other A low-resistance material layer (not shown), and then form a photoresist mask 2501 above the peripheral area, etch and remove the tungsten silicide or other material layers on the polycrystalline silicon layer 520 that are not covered by the photoresist mask 2501, and then perform the polycrystalline silicon layer 520. The silicon layer 520 is anisotropically etched to form spacers (as shown in FIGS. 20A and 20B ) and define peripheral transistor gates and other peripheral components, and then the photoresist mask 2501 is removed, such that tungsten silicide or other The conductive material 2605 will cover the polysilicon layer 520 in the peripheral area (as shown in FIG. 26B ). If the conductive material 2605 and the polysilicon layer are etched simultaneously, there may be some left on the polysilicon layer 520 of the memory array. Conductive material 2605.

The photoresist mask 1710 (shown in FIG. 11A ) protects the peripheral active area while removing the polysilicon layer 520 from the source line.

In some embodiments, before forming the photoresist mask 2501, a silicon nitride layer 2607 is deposited on the polysilicon layer 520 (as shown in FIG. 26C ). resistance of the crystal gate, the silicon nitride layer 2607 is deposited on the conductive material 2605, and then a photoresist mask 2501 is formed on the peripheral transistor gate as described above, and the silicon nitride layer in the uncovered area is etched, The wafer is processed according to the manner of FIG. 25 , FIG. 26A , and FIG. 26B . FIG. 26C is a cross-sectional view of an embodiment with conductive material 2605 in the peripheral region. The silicon nitride layer 720 and 2607 will act as an etch stop layer when the structure is chemically mechanically polished later, at the stage of FIG. 24A and FIG. After being covered with an insulating material (such as vapor deposited oxide (vapox), not shown), chemical mechanical polishing can planarize the wafer. In some embodiments, the insulating layer is used for wafer dicing or packaging. In some embodiments, the material of the insulating layer can be doped or undoped silicon dioxide layer, such as borophosphosilicate glass (BPSG), and other Material.

In some embodiments, some peripheral transistor gates or other elements are formed by layer 128, and other peripheral gates or elements are formed by polysilicon layer 520, which will be described later with reference to FIGS. 44 to 50 One such embodiment.

To reduce the resistance of the polysilicon layer (word line) 520, metal strips can be used. Each metal strip is located on a word line and contacts the word line at regular intervals (such as every 128 rows), because The word line 520 is a narrow partition, which has low resistance even if there is a small bump in contact with the metal strip, and the photoresist mask 2501 can be used to form this bump. FIG. 27 is a top view of this embodiment, showing that after forming partition walls by anisotropic etching of polysilicon layer 520, the memory array is truncated to have a gap 2701, and the gap 2701 is in the same direction as the bit line, so that the character will be formed. The space raised by the line, the gap 2701 can be used for the groove 910, the memory array section 2703.1 is located on one side of the gap (it seems to be located above the gap in Figure 27), and the memory array section 2703.2 is located below the gap, the character The line 520 and the stacked structure 710 span the sections 2703.1 and 2703.2 and the gap without interruption. The mask 2501 formed before etching to form the partition wall covers part of the polysilicon layer 520 in the gap 2701. FIG. 28 shows that the photoresist is removed A top view of the mask 2501 and the area of the gap 2701 after the photoresist mask 1710 is formed.

The number of gaps 2701 in a memory array can be selected arbitrarily. For example, there can be a gap every 128 rows (bit lines) in a memory array. Of course, a memory can also have any number of memory arrays.

In FIG. 27, the photoresist mask 2501 includes strips extending along the gap, and the photoresist mask 2501 is truncated in the region 2709 between adjacent wordlines 520, so that the polysilicon layer of the wordline gate can be etched. 520, so it can avoid forming a short circuit between adjacent word lines, the photoresist mask 2501 can be broken or continuously above the source line 144, and the photoresist mask above the source line does not need to be interrupted, which is difficult for etching The polysilicon layer 520 in the source line region is made using a photoresist mask 1710 (as shown in FIG. 28 ).

The photoresist mask 2501 may also cover peripheral transistor gates and other peripheral components, as described above with respect to FIG. 25 .

The photoresist mask 1710 (shown in FIG. 28 ) can have the same geometry as the photoresist mask described above in relation to FIGS. Polycrystalline silicon layer 520, deep implantation 2110 for source lines, insulating layer 1010 for etching trenches, FIG. 29 shows polycrystalline silicon layer 520 with etched source lines, each polycrystalline silicon (word line) 520 Within the gap 2701 there is a lateral protrusion 520E.

Then process the wafer with reference to the previous FIG. 22A to FIG. 26C. If the insulating layer 1010 is etched in the manner referring to FIG. The bottom and sidewalls of the trenches in the gaps in the array, so that the source line 144 passes through the gaps without interruption.

FIG. 30A shows a cross-sectional view inside a memory gap 2701 in a later-stage process. An insulating layer 2901 has been formed above the memory cell. Each metal strip 2903 is located above the corresponding word line 520 and passes through the insulating layer in the gate gap 2701. Opening 2903C of layer 2901 is in contact with word line 520 . In FIG. 30A, the upper surface of the polycrystalline silicon layer 520 is at the same level as the upper surface of the silicon nitride layer 720 above the control gate 128. This is because the polycrystalline silicon layer 520 has been processed by chemical mechanical polishing and touches the silicon nitride layer 720. Silicon layer stops. Specifically, the insulating layer 2901 is composed of multiple layers, some layers are deposited after the steps in FIG. 24A and FIG. 24B , and then undergo chemical mechanical polishing, and then other layers are formed to complete a complete insulating layer 2901 . In other embodiments, the polysilicon layer 520 overlaps with the silicon nitride layer.

In some embodiments, the isolation trench 910 does not use up the width of the entire gap 2701 (ie, the vertical dimension of FIG. 28 and FIG. 29 ), the composite layer isolation trench may be located in the gap, or there may be no gap in the gap. any grooves.

FIG. 30B and FIG. 30C are the memory section and mask layout diagrams of another embodiment, respectively. FIG. 30c shows photoresist masks 904, 1014, and 2501 (please also refer to FIG. 12A, FIG. 12B, FIG. 16, and FIG. 27). The element line contact 138 can be etched simultaneously with the contact opening 290C of the polysilicon layer 520 , or not at the same time. The contact opening 144C of the source line 144 can also be etched simultaneously with the bit line contact 138 or the polysilicon contact 2903C. In some embodiments, the contact openings 138, 2903C, 144C and the contact opening (not shown) of the control gate 128 are etched simultaneously using the same photoresist mask, and the silicon nitride layer 720 is etched downward from the mask opening. To expose the control gate, the contact opening 2903C of the polysilicon layer 520 is disconnected from the control gate 128 to prevent the word line 520 from forming a short circuit with the control gate 128 .

The contact opening 138 can be filled with an N+ doped polysilicon plug using known techniques. If the etching of the contact opening 138 affects the insulating layer 1010 in the trench 910 due to misalignment of the contact mask, the trench The removed insulating layer 1010 will be filled with N+ polysilicon when the plug is formed, and the polysilicon plug can prevent short circuit between the metal contact and the P-doped substrate region 150 .

In some embodiments, a short circuit will be formed between adjacent source lines 144. For example, four source lines may form a group, and each group of four source lines may be in contact with the metal strip 2903. To form a short circuit, the metal strip 2903 can contact the source line through the opening 144C in the gap 3010 between adjacent rows of the memory array, so that the short circuit of the source line can reduce the area that needs to connect the source line to a higher metal layer (not shown) , because only one contact opening (not shown) is needed for the four source lines to be in contact with the higher metal layer, the contact with the higher metal layer can also be used to reduce the resistance of the source line, the metal formed by the higher metal layer The strips can be formed above the source lines in spaced contact with metal strips 2903 that contact the source lines with openings 144C in gaps 3010 , and the memory array can have multiple gaps 3010 . For each set of four source lines, the accompanying eight control gate lines 128 can also be connected together to form a short circuit.

The control gate lines 128 defined by the photoresist mask 1014 are bent along the source line contact opening 144C. If adjacent control gate lines 128 are in close proximity in the bit line region 312 within the gap 3010, the polysilicon layer 520 It may be filled into the above-mentioned regions 312, causing word lines 520 to form troublesome short circuits in these regions. In order to avoid short circuits, the polysilicon layer 520 in the gap 3010 can be removed using a photoresist mask 1710 (FIG. 28). The word line partition wall 520 will be cut off in the gap 3010, but the individual part of the word lines between the gate gaps 3010 will be electrically connected with the metal strip 2903 (as shown in FIG. 30B ), and the metal strip 2903 is connected to the word line in the gap 2701. element line contact.

The sections of memory array sections 2703.1 and 2703.2 located between gate gaps 2701 and 3010 are similar to those shown in Figures 24A and 24B. Metal strips 2903 are in memory array sections 2703.1 and 2703.2, above word lines but not in contact with them.

In some embodiments, source line 144 is reduced in resistance by silicidation, for example, by depositing cobalt on the structure at the stage of FIG. 24A and FIG. 24B (ie, before or after doping bit line region 134). or other suitable metals, the wafer is heated so that the exposed silicon reacts with cobalt or other metals to form a conductive silicide, and then the unreacted cobalt or other metals are removed, and the silicide remains on the source lines 144 and Above the word line 520, the above-mentioned silicidation steps are the same as the silicidation process known in the art (ie salicide).

In some embodiments, the insulating layer 1810 may not be sufficient to prevent cobalt or other metals from forming a short circuit with the bit line region 134, therefore, the word line 520 may form a short circuit with the bit line region 134, we can use The following method avoids this situation: after the wafer is processed through the stages of Fig. 20A and Fig. 20B, just before depositing the photoresist mask 1710, an insulating layer 3003 (as shown in Fig. 31A and Fig. 31B) is deposited earlier, the insulating layer 3003 The material can be silicon dioxide. Then, in the above-mentioned method, the photoresist mask 1710 is sequentially formed, and then the insulating layer 3003 exposed outside the photoresist mask 1710 is removed, and then the wafer is processed through the steps in FIG. 21A to FIG. 23B , specifically Etching the polysilicon layer 520 and the doped source line 144 (ie implant 2110), and then removing the photoresist mask 1710, the resulting structure is shown in FIGS. 32A and 32B.

Then deposit a layer of metal (such as cobalt), heat the wafer so that the metal reacts with the silicon in the source line area, and remove the unreacted metal, and finally, a silicide layer 3301 is formed just above the source line (as shown in Figure 33A and Figure 33B).

In some cases, if the insulating layer 1010 in the trench 910 is not completely etched away (as shown in FIG. 23B ), the silicide 3301 in the trench 910 will be cut off.

Next, continue to etch the insulating layer 3003, perform implantation 2401 on the bit line region 134 and the source line (as shown in FIG. 24A and FIG. 24B ), or perform implantation through the insulating layer 3003. Can choose to keep in memory.

The source line silicidation technology can be applied together with the embodiment of FIG. 16 (that is, the peripheral transistor gate is formed by the control gate layer 128), and can also be used with the embodiments of FIG. 25, FIG. 26A, FIG. 26B, and FIG. 26C ( That is, the peripheral transistor gate is formed by the polysilicon layer 520), or is used together with the embodiment of FIG. 44 to FIG. 50 (the polysilicon layer 128 and 520 are used as the peripheral transistor gate) Application, which will be described later, the siliconization technology can also be combined with the bump 520E (as shown in FIGS. 27 to 30 ).

FIG. 34 illustrates another flash memory array according to the present invention. Each isolation trench 910 protrudes between adjacent source lines 144, but does not intersect with the source lines. We mark the boundaries of the isolation trenches as 910B.

The manufacturing process of the above-mentioned memory is as follows: doping the substrate 905 to form an isolation region 150 (as shown in FIG. 11 ), and then sequentially forming a tunnel oxide layer 108, a polysilicon layer 124, a silicon nitride layer 1203, and a photoresist mask 904 (as shown in FIG. 12A and FIG. 12B ), patterning the silicon nitride layer 1203 and the polycrystalline silicon layer 124, however, this step does not etch the substrate region 150, and the tunnel oxide layer 108 can decide whether to etch it. , and then remove the photoresist mask 904, and the obtained structure is as shown in FIG. 35 .

Next, deposit a silicon oxide layer 2710 with a thickness of 300 nm (as shown in FIG. 36 ), such as borophosphosilicate glass, by chemical vapor deposition, and then lithographically pattern a photoresist mask 2810 (as shown in FIG. 37 ). , making it a long strip in the direction of the word line, each strip is located in the area where the source line 144 will be formed, and the photoresist mask 2810 is related to other elements of the memory (such as the control gate 128) (as shown in Figure 38 ), this The step does not yet form the control gate 128 .

The oxide layers 2710 and 108 surrounded by the photoresist mask and the silicon nitride layer 1203 are removed by selective etching of the photoresist mask 2810 and the silicon nitride layer 1203, and then the photoresist mask 2810 is removed to form two The oxide layer 2710 and the silicon nitride layer 1203 are used as a mask to etch the substrate region 150 to form a rectangular trench 910; or when etching the substrate region 150, the photoresist mask 2810 can be left, and in this case there is no need to deposit two Oxide layer 2710. FIG. 39 shows a cross-section of an embodiment using the oxide layer 2710. The cross-section is taken along line 39-39 of FIG.

Then deposit an insulating layer 1010 (as shown in FIG. 13 ), and remove part of the insulating layer 1010 (as shown in FIG. 14 ) by chemical mechanical polishing, then remove the silicon nitride layer 1203, and selectively etch the insulating layer 1010 , making the upper surface a flat surface. 40B is a plan cross-sectional view of the resulting structure parallel to word lines and passing through trenches, and FIG. 40A is a plan cross-sectional view passing between adjacent trenches. Some insulating layers 1010 may cover the substrate region 150 of the source line 144 part. The source line does not cross the trench (some of the oxide layer 2710 can remain on the sidewalls of the polysilicon strip 124, and the oxide layer will then appear to be part of the insulating layer 1010).

In some embodiments, a portion of the insulating layer 1010 is etched away to expose the sidewalls of the polysilicon layer 124, thereby improving the capacitive coupling between the control gate 128 and the floating gate 124 (as shown in FIG. 24C ).

The rest of the process steps can be the same as the above-mentioned FIG. 16 to FIG. 33B , such as forming an insulating layer (the material can be an oxygen nitride oxide layer, ONO layer) 98, a control gate layer 128, a silicon nitride layer 720, a photoresist mask 1014, etc. step (ie, the peripheral transistor gate can be formed from layer 128 or word line layer 520).

Then silicon dioxide layer 1510 (as shown in FIG. 18A ), silicon nitride spacers 903 and silicon dioxide layer 1810 (as shown in FIG. 19A ) are formed.

Deposition is not isotropic etching polysilicon layer 520 (as shown in FIG. 20A ), and then forms a photoresist mask 1710 (as shown in FIG. 21A ), and etches the polysilicon layer 520 at the source line 144 (as shown in FIG. 22A As shown), the insulating layer 1010 at the source line 144 can be etched or not etched, and then the implantation 2110 is performed, because the source line does not intersect the trench 910, this implantation dopes the entire long source line , the resulting structure is the same as that shown in FIG. 22A, and FIG. 41 shows a cross section along the trench (ie, this cross section assumes that the insulating layer 1010 at the source line has been etched).

24A and 24B, remove the photoresist mask 1710, perform N-type implantation 2401 to dope the bit line region 134 and source line 144, and etch the source line before the step of implantation 2410 The insulating layer 1010 at , is either etched between the steps of implanting 2110 and 2410, or is performed after the step of implanting 2410, or is not etched.

In some embodiments, the raised portion 520E of FIGS. 27 to 30 is used as the word line 520; in some embodiments, as shown in FIGS. 24A, 31A to 33B, the source line 144 to reduce its resistance.

In FIG. 42, we have omitted the oxide layer 2710 and the photoresist mask 2810. The isolation trench 910 is defined by the photoresist mask 904 as shown in FIG. 12A, but since the trench 910 is rectangular (as shown in FIG. 37 ), so the silicon nitride layer 1203 and the polycrystalline silicon layer 124 have the same outline as the composite layer in FIG. 37, and the groove 910 has the same shape as the groove in FIG. 34 to FIG. For the insulating layer 1010 above the source line 144 (as shown in FIG. 15 ), the rest of the process steps are the same as those in FIGS. 37 to 41 . layer 124 and the oxide layer 108 , this step exposes the source line 144 .

In the embodiment of Fig. 9A to Fig. 43, it is to utilize source terminal thermal electron injection method to program (make become non-conductive) memory cell, please refer to "NonvolatileSemiconductor Memory Technology" No. 21 published by W.D.Brown et al. in 1998 On page 23, Table 1 below lists the memory reference voltages driven by an external power supply (VCC) of 1.8V. The slash is used to indicate the voltage of the selected/non-selected memory column or row. For example, in Table 1 " Row "stylized", column "Bitline Region 134", item "0V/V3" indicates that the selected bitline is 0V, and the unselected bitline is at voltage V3, we have not listed all non-selected voltages.

Memory cells can be erased from the floating gate 124 to the source line 144 (please refer to the "Erase Sector Via Source Line" row of Table 1) or to the substrate area 150 ("Erase Sector Via Substrate" ) Fowler-Nordheim tunneling, which is a better technology because it reduces the band-to-band current. In the flash memory array shown in FIG. 10B and FIG. 34 , only the entire sector (sector) can be erased, and individual cells cannot be erased. A sector refers to a row or a number of rows, and their corresponding source lines 144 pass through the circuit The connection forms a short circuit, and the corresponding control gate line 128 also forms a short circuit via the circuit connection.

Some embodiments provide the option of erasing multiple regions or the entire memory array in a single operation step, using Fowler-Nordheim electron tunneling from the floating gate 124 to the substrate region 150 to simultaneously erase all cells to be erased Yuan, this is the "wafer erase" in Table 1. The area 150 is forward biased relative to all control gates. The speed of array erasing using the wafer erasing method will be faster than the row-by-row erasing method. This is in the test Especially useful for storage.

Table 1 Stylized Erase the entire area via the source line Erase the entire area through the substrate wafer erase read Control gate 128 +10V/0V -10V -10V -10V 1.8V bit line area 134 0V/V3 ^** (VCC＝1.8V) V4 ^*** (VCC＝1.8V) float float 1.5 source line 144 6V 5V float float 0V select gate 520 VTN+ΔV ₁ ^* 0V 0V 0V VCC+ΔV ₂ ^* (VCC＝1.8V) Substrate area 150 0V 0V 6V 6V 0V

Note:

*In the embodiment, VTN=0.6V, ΔV ₁ =0.9V, ΔV ₂ =1.4V.

**V3 is a voltage greater than 0V ₁ .

***V4 voltage range 0<V4<VCC.

A memory can have multiple memory arrays, each memory array has its own bit line and word line, and different arrays can be placed in the same substrate area 150 or in different isolated substrate areas 150 of the same integrated circuit. The “wafer erase” operation can erase the memory cells on a certain substrate region 150 without erasing the memory cells on other substrate regions 150 .

The voltage generator and decoder block 4201 (shown in FIG. 43 ) generates necessary voltages in response to the power supply voltage VCC, address signal “ADDR”, and other command/control signals using known techniques.

Fig. 44 illustrates the thickness of the gate insulating layer of different metal oxide semi-transistors according to the memory embodiment of Fig. 9A to Fig. A thicker gate insulating layer is required, and at the same time, the tunnel oxide layer 108 must have sufficient thickness to store long data.

In the embodiment described immediately below, all gate insulating layers are silicon dioxide layers, but this is not necessarily the case. The thickness of the gate insulating layer is assumed to be VCC=1.8V, and the operating voltage is as shown in Table 1 above. column, these voltages are for illustration only and are not intended to limit the invention.

In FIG. 44, the tunnel oxide layer 108 is about 9um thick, and the select transistor gate oxide layer 1810 should be relatively thin (such as 5nm) to provide fast operation, but it must be thick enough to withstand the The voltage for the read operation is 3.2V (VCC+ΔV ₂ =3.2V in the example).

The peripheral region 1603 includes active regions 4402, 4404, 4406. The high voltage active region 4402 is for transistors exposed to voltages from 10V to -10V (see Table 1) and other high voltages, which may be voltage generators A portion of 4201 (shown in FIG. 43 ), over gate oxide 4408 in region 4402 is thicker, about 22 to 25 nm thick.

The high-speed active area 4404 is used for transistors exposed to voltages below VCC. These transistors may be address decoders, sense amplifiers, clock signal generators, voltage generators, address and data buffers, and others Part of the circuit, their gate oxide 4410 is quite thin, about 3.5nm thick.

The I/O active area 4406 is used for the transistor used as the interface of the cut-off chip circuit. The cut-off chip circuit may operate at a higher power supply voltage, such as 2.5V or 3.3V, so the I/O transistor must be thicker In FIG. 44, the I/O transistor gate oxide layer 1810 is the same layer as the select transistor gate oxide layer 1810, which is about 5um thick.

In FIG. 44, the transistor gates of regions 4402 and 4404 are formed by the control gate layer 128, and the I/O transistor gates of region 4406 and the selection gate 520 (that is, the word line) of the memory cell are formed by complex gates. The crystal silicon layer 520 is formed, as illustrated in Figure 26B and Figure 26C, there may be a metal layer and/or a silicon nitride layer on the selection gate 520, and the control gate 128 may be made of polysilicon polysiliconization metal or other conductive layers. form.

The above-mentioned process for forming the gate insulating layer is as follows: a tunnel oxide layer 108 with a thickness of 9 nm (as shown in FIG. On the crystalline silicon layer 124, isolation trenches 910 are formed, and the trenches 910 are filled with an insulating material 1010. Please refer to FIGS. 12A to 15, 37, 42 and related text descriptions.

A silicon dioxide layer 98.1 and a silicon nitride layer 98.2 (as shown in FIG. 16 ) are formed, and the reference thicknesses of these layers are 1 nm and 5 nm, respectively.

A photoresist mask 4501 is then deposited and lithographically patterned to cover the memory array (as shown in FIG. 45 ), and layers 98.2, 98.1, 124, and 108 of the peripheral region 1603 are etched to expose the substrate 905.

Next, the photoresist mask 4501 is removed, and the wafer is oxidized at a temperature of 850° C. or lower, so that a silicon dioxide layer 4408 with a thickness of 24 μm will be formed in the active regions 4402, 4404, and 4406 (as shown in FIG. 46 ), At the same time, a silicon dioxide layer 98.3 with a thickness of 1 nm to 1.5 nm is formed on the silicon nitride layer 98.2 in the active area 901 of the memory array.

A photoresist mask 4601 is then deposited and patterned such that it covers the entire memory array and the high voltage active region 4402. The active regions 4404 and 4406 are not covered so that the silicon dioxide layer 4408 of the active regions 4404 and 4406 is etched.

The photoresist mask 4601 is then removed. Generally speaking, the step after removing the photoresist is usually to clean the wafer. In this embodiment, the cleaning step will not damage the oxide layer 4408 in the region 4402 because the oxide Layer 4408 is thick, while thin oxide layer 4410 (as shown in FIG. 44 ) does not come into contact with the photoresist and therefore cannot be damaged by cleaning steps after removal of the photoresist.

Then the wafer is oxidized to form a silicon dioxide layer 4410 with a thickness of 3.5nm in the active regions 4404 and 4406 (as shown in Figure 47). Here, a dry oxidation method with a temperature lower than 850°C can be used. (ie, within region 4402) increased to about 25um in thickness.

Then deposit a control gate layer 128 and a silicon oxide layer 720 on the wafer to form a photoresist mask 1014, and use the photoresist mask 1014 to define the stack structure 710 and transistor gates located in the high voltage region 4402 and the high speed region 4404 , the photoresist mask 1014 does not cover the I/O active region 44406, and the photoresist mask 1014 is sequentially etched to expose the underlying silicon nitride layer 720, the control gate layer 128, and 98.3, 98.2, 98.1, 4408, 4410 each layer, wherein during the etching process, it stops as long as it touches the polysilicon layer 124 of the array active area 901 and the substrate 905 of the peripheral active area.

Then remove the photoresist mask 1014 to form another photoresist mask 4801 (as shown in FIG. 48 ) to cover all the peripheral regions 1603 (the photoresist mask 4801 may not be used in the area where the silicon nitride layer 720 is formed), and etch The polycrystalline silicon layer 124 and the silicon dioxide layer 108 not protected by the photoresist mask 4801 and the silicon nitride layer 720 on the wafer form a stacked structure 710, and then the photoresist mask 4801 is removed, and the resulting structure is as follows Figure 49.

Next, continue to form a silicon dioxide layer 1510 and a silicon nitride layer 903 (as shown in FIG. 19A and FIG. 19B ) to protect the sidewalls of the stack structure 710, and then oxidize the wafer in the exposed substrate area of the memory array active area 901 150 and the bare substrate 905 of the I/O active region 4406 to form a silicon dioxide layer 1810 with a thickness of 5um (as shown in FIG. Peripheral transistor gates (as shown in FIG. 25, FIG. 26A, FIG. 26B, and FIG. 26C).

As mentioned above, during chemical mechanical polishing, the silicon nitride layer 2607 above the polysilicon layer 520 in the active region 4406 (as shown in FIG. 26C ) will protect the polysilicon layer 520, In the case of layer 2607, the polysilicon layer 520 can also be protected in the manner shown in FIG. The steps are the same as in the high-speed region 4404 (FIG. 44), so that the silicon nitride layer 720 will be formed in the region 4404D, and the upper surface of the silicon nitride layer 720 is higher than the upper surface of the polysilicon layer 520 in the region 4406. Silicon nitride layer 720 in region 4404D does not allow removal of silicon dioxide over polycrystalline silicon layer 520 in region 4406 when silicon oxide (not shown) covers the crystal pattern and undergoes chemical mechanical polishing, thereby protecting the polycrystalline Silicon layer 520 .

In addition, the processing steps of the dummy area can also be the same as that of the high voltage area 4402, or different dummy areas can be used to surround each I/O transistor active area 4406, some of which use the area 4402, and some use the area 4404, or provide a single handling structure that encloses the component on either side. Some regions 4404D may not be dummy regions, that is, transistors may be formed in these regions. Region 4404D may be separated from region 4406 by isolation trench 910, or region 4404D may partially overlap the isolation trench, or lie entirely above the isolation trench.

Next, we will further explain the method of protecting circuit components with a dummy structure.

51 is a cross-sectional view of a semiconductor structure 110 , which includes a semiconductor substrate 905 , polysilicon layers 128 and 520 , a protective layer 720 (which can be made of silicon nitride), and a dielectric layer 113 . The circuit structure 121.1 includes a circuit element 128.1 formed by the polycrystalline silicon layer 128 and a circuit element 520.1 formed by the polycrystalline silicon layer 520. In one embodiment, the above-mentioned element 128.1 may be a capacitor plate or a gate of a thin film transistor , while element 520.1 can be a capacitive plate, source, drain and/or channel region of a transistor, both can be different devices, for example, element 128.1 can be a transistor gate, and element 520.1 can be a resistor Devices, capacitor plates, interconnects, etc.

Polycrystalline silicon layer 520 provides circuit element 520.2. In the embodiment of FIG. 51, element 520.2 is the gate of transistor 121.2. There is a gate insulating layer 1810 between the gate 520.2, and the present invention does not limit this type of transistor, and the element 520.2 can be a capacitor plate, a resistor, an interconnection wire or any other elements. Likewise, polycrystalline silicon layer 128 provides circuit element 128.3. In FIG. 4410 separates the gate 128.3 from the substrate 905.

Protective features 720.1 and 720.2 are formed by layer 720 to protect components 128.1, 520.1, 520.2 during chemical mechanical polishing of dielectric layer 113.

At least a part of the element 128 . 3 is not covered by the protective layer 720 .

Dummy structures 141 are formed close to the element 128.3 to protect the circuit element during chemical mechanical polishing of the dielectric layer 113. Each dummy structure includes a portion 520.3 formed by the polysilicon layer 520, which is formed by the protective layer 720. The feature element 720.3 is formed to cover the individual portion 520.3. The feature 520.3 does not serve as any circuit element and does not provide any electrical function. It can be connected to a fixed voltage or allowed to float.

The field isolation region 1010 is formed by shallow trench isolation technology, or can be formed by local oxidation of silicon (LOCOS) technology or other techniques; the dummy structure 141 is located above the field isolation region 1010, but this is not necessary .

Due to the influence of the non-flat profile of each element, the upper surface of the dielectric layer 113 is not flat. We perform chemical mechanical polishing on the dielectric layer 113 and stop when it touches the protective layer 720, so as to achieve the purpose of planarization. The structure is shown in Figure 52. The upper surface of the structure may be completely flat, or there may be some non-flat areas. One reason for the non-flatness is that each feature element 720.1, 720.2, 720.3 is not flat, and the elements 720.2 and 720.3 The upper surface of the upper surface of the element 720.1 is lower than the upper surface of the element 720.1, and the upper surface of the dielectric layer 113 above the element 128.3 will also be relatively lower, because there is no structure of the protective layer 720 below, another reason for poor flatness may be The density of components in some parts of the integrated circuit is low, please refer to US Patent No. 5,909,628 "REDUCING NON-UNIFORMITY IN A REFILL LAYER THICKNESS FOR ASEMICONDUCTOR DEVICE" issued on June 1, 1999. However, after chemical mechanical polishing, The upper surface of the structure 110 is already relatively flat and is substantially flat.

In some embodiments, the gap between the high point of the protective layer 720 and the low point of the dielectric layer 113 is less than 15nm. ), the degree of unevenness is also related to specific chemical mechanical polishing techniques (such as using slurry or low slurry fixed abrasive), and the present invention does not limit any specific chemical mechanical polishing process or degree of unevenness.

In some embodiments, not all of the protective layer 720 is affected by grinding, for example only the upper feature elements 720.1 are affected by grinding while the lower feature elements 720.2 are not.

The dummy structure 141 will protect the device 128.3 from being affected. In some embodiments, the distance between adjacent structures 141 on opposite sides of the device 128.3 is about 5 mm. The layer 720 is 160 nm thick silicon nitride, and the dummy feature device The upper surface of 720.3 is about 0.21 mm above element 128.3; in other embodiments, the distance between dummy structures 141 on opposite sides of element 128.3 exceeds 10 mm, and the maximum allowable distance depends on the material used, layer thickness, and quality of chemical mechanical polishing There are relationships.

Dummy structures may be provided on only one side of the structure 121.3.

If the dielectric layer 113 above the element 128.3 is not thick enough to provide the desired isolation, another insulating layer (not shown) can be deposited over the structure, this layer having a substantially flat upper surface. The surface, because the underlying dielectric layer 113 has a relatively flat structure after chemical mechanical polishing.

The gate insulating layer 1810 and the gate insulating layer 4410 are not necessarily formed of the same insulating layer, and different insulating layers can be used, especially when we want the gate insulating layers of transistors 121.2 and 121.3 to have different thicknesses.

A reference process is provided below: process the substrate 905 according to individual needs (such as forming complementary metal oxide semiconductor (CMOS) wells, but the present invention is not limited to complementary metal oxide semiconductor), and then form the insulating layer 4410 or 1810 and others Layers are deposited and patterned 128, 520, 720, and then the insulating layer 113 is deposited and processed by chemical mechanical polishing. Of course, other layers can be formed or doping steps can be performed at certain stages in the process.

The polysilicon layers 128 and 520 can be deposited by chemical vapor deposition, sputtering or other known or unknown techniques. Layers 720 and 520 can be patterned simultaneously using a single mask, or layer 1810 can be formed after layer 128 has been formed.

In FIG. 53, the dummy structure 141 uses a polysilicon layer 128. The integrated circuit of FIG. 53 includes a flash memory array 901, the silicon layer 124 is used as a floating gate of the memory cell, and the polysilicon layer 128 is used as a control gate, the polysilicon layer 520 serves as the select gate, and the insulating layer 108 (“tunnel oxide layer”) is formed of silicon dioxide with sufficient thickness to provide adequate data memory. In some embodiments, the oxide Layer 108 is 9 nm thick and select transistor gate oxide layer 1810 is 5 nm thick. The materials and thicknesses mentioned here are for illustrative purposes only and are not intended to limit the invention.

The bit line area 134 of the memory cell is connected to the upper bit line (not shown), and it extends to the direction of the bit line "BL", and the source line area 144 extends to the direction of the word line, and is connected to the bit line vertical.

The peripheral region 1603 includes active regions 4402, 4404, and 4406 (as shown in FIG. 53 ), in which transistors are formed. The high-voltage active region 4402 is used for transistors located in a high-voltage environment, and the transistors are used for erasing And program the memory cells of the array 901, the gate of the transistor in this area is formed by the polycrystalline silicon layer 128, and the gate insulating layer 4408 is a silicon dioxide layer with a thickness of about 20nm.

The high speed region 4404 includes transistors with a thinner gate oxide 4410 for low voltage operation. The oxide 4410 is 3.5nm thick. The gate of the transistor is formed by 128 layers.

The I/O active area 4406 is used for the transistor used as the interface of the cut-off chip circuit. The cut-off chip circuit can operate at a higher power supply voltage, so the transistor has a thicker gate oxide layer to withstand this voltage , the gate insulating layer is the same as the gate insulating layer 1810 of the selection transistor of the memory array 901 .

Reference numeral 133 indicates source and drain regions of transistors in regions 4402 , 4404 , 4406 , and field insulating layer 1010 is formed around transistors or other transistors in region 4406 .

The relevant manufacturing steps are briefly described as follows:

A tunnel oxide layer 108 with a thickness of 9nm is formed on the substrate 905 by thermal oxidation (FIG. 54), and then the polysilicon layer 124, the silicon dioxide layer 98.1, and the silicon nitride layer 98.2 are sequentially deposited, and then on the memory array 901 A photoresist mask 4501 is formed, and layers 98.2, 98.1, and 124 in regions 4402, 4404, and 4406 are etched to expose the substrate 905.

Before depositing the silicon dioxide layer 98 . 1 , the polysilicon layer 124 and the substrate 905 are patterned to form isolation trenches, and the trenches are filled with silicon dioxide 1010 .

After etching the oxide layer 108, remove the photoresist mask 4501, and heat the substrate 905 to form an oxide layer 4408 with a thickness of 19 nm (FIG. 55). At this time, a thin silicon dioxide layer 98.3 will be formed on the silicon nitride layer 98.2. .

The photoresist mask 4601 is formed by lithography in the memory array 901 and the high voltage area 4402, and the silicon dioxide layer 4408 on the substrate in the areas 4404 and 4406 is etched.

The photoresist mask 4601 is then removed, the wafer is oxidized, and a silicon dioxide layer 4410 with a thickness of 3.5 nm is formed over the substrate 905 in regions 4404 and 4406 (Fig. 56). 4408 has slightly increased thickness.

A polysilicon layer 128 and a silicon nitride layer 720 are then deposited on the wafer to form a photoresist mask 1014 to define (i) the floating and control gates of the memory array (ii) the transistor gates in regions 4402 and 4404 (iii) The dummy structure 141 in the area 4406, etch the layers 720, 128, 98.3, 98.2, 98.1, 4408, 4410 in the area not covered by the mask, and the etching will stop at the polycrystalline silicon layer in the memory array area 124 and the substrate 905 in other areas (FIG. 57).

The photoresist 1014 is then removed, and the polysilicon layer 128 and the silicon nitride layer 720 protect the thin gate oxide layer 4410 in the high speed region 4404 during the cleaning step.

Another photoresist mask 4801 is formed in the regions 4402, 4404, 4406, and the place where the silicon nitride layer 720 is present may not be used. crystalline silicon layer 1124 and silicon dioxide layer 108, and then remove the photoresist mask 4801 (FIG. 58).

Thin silicon dioxide layer 1510 is formed on the exposed sidewalls of layers 124 and 128 and the substrate 905 is oxidized (FIG. 59), and then a thin silicon nitride layer 903 that is not isotropically etched is deposited, so that the gate structure of the transistor can be formed. The silicon dioxide layer 1510 exposed by etching the silicon nitride layer 903 may be removed during etching.

A silicon dioxide layer 1810 with a thickness of 5 nm was grown by thermal oxidation over the exposed surface of the substrate 905 (FIG. 60).

Deposit a polysilicon layer 520 on the structure, then form a photoresist mask 2501 to define the transistor gate of the I/O region 4406, etch the polysilicon layer 520 anisotropically to form the transistor gate structure and dummy structures partition on the side wall.

The resist mask 2501 is removed, a photoresist layer 1710 is formed on the gate of the I/O transistor and the select gate of the memory array (FIG. 61), and the polysilicon layer 520 in the remaining area is etched.

Appropriate doping steps are performed at appropriate stages in the manufacturing process to form source and drain regions, bit line and source line regions and other doped regions of the transistor.

In some embodiments, the memory cells are multilevel cells (MLC), that is, each memory cell can store more than one bit of information, and each floating gate 124 can store three or more For charge levels corresponding to three or more different control gate 128 limiting voltages, please refer to US Patent 5,953,255 issued September 4, 1999 by Lee.

The present invention is not limited to the above-mentioned embodiments. The present invention is not limited to a specific erasing or programming mechanism (such as Fowler-Nordheim, or hot electron injection). The present invention covers non-flash electronic erasable and programmable only Read memory (electrically eraseable programmable read onlymemory, EEPROM) and other known or uninvented memory, the present invention is not limited to the above materials, for example, the material of control gate, selection gate and other conductive elements can be metal, metal silicide, Polycrystalline silicide metal and other conductive materials or composites, or can also contain conductors and conductor parts, such as partially doped polycrystalline silicon layers, silicon dioxide or silicon nitride can also be replaced by other insulating materials, P-type and N-type conduction methods are interchangeable, and the invention is not limited to any particular process steps or sequence of steps. For example, in some embodiments, thermal oxidation of silicon may be replaced by chemical vapor deposition or other technology to deposit a layer of silicon dioxide or other insulating material, in some embodiments, the deep implant 2110 can be performed after etching the insulating material 1010, the present invention is not limited to silicon integrated circuits, the scope of the claims defines other scopes consistent with the present invention Examples and variations.

Claims (19)

1. A method of manufacturing an integrated circuit comprising a non-volatile memory, characterized in that the method at least comprises: (a) forming a first insulating layer (108) and a first layer (124) on a first region of a semiconductor, wherein the integrated circuit includes a plurality of non-volatile memory cells, each of the memory cells includes a a floating gate formed by part of the first layer (124); (b) forming a plurality of trenches (910) in the semiconductor first region through openings of the first layer, and filling the trenches (910) with an insulating material (1010); (c) forming a second layer (128) over the semiconductor first region, wherein each of the cells includes a conductive gate formed from a portion of the second layer (128), the conductive gate and the The floating gate (124) of the cell is isolated by a second insulating layer (98); (d) patterning the second layer (128) to form strips extending in a predetermined direction, each strip spanning a plurality of the grooves (910); (e) removing the portion of the first layer (124) on the semiconductor first region not covered by the second layer (128) to form a plurality of first structures, each of the first structures comprising a a strip formed by the second layer and comprising a portion of the first layer below the strip, each of the first structures having a first side wall; (f) forming a third layer (520) on the first layer and the second layer, and removing part of the third layer (520) by a process including anisotropic etching, so that in each of the A partition (520) is formed on at least part of the first sidewall of some first structures, wherein each partition (520) is connected to the first layer (124) and the second layer (128) in the corresponding first structure ) is separated by an insulating material; (g) forming a lithography mask pattern (1710) using lithography, the lithography mask pattern covering the partition on the first sidewall of the first structure; (h) using the lithographic mask pattern (1710) as a mask to remove the partition wall (520) not covered by the lithographic mask pattern, so that each of the cells contains a structure composed of the first structure The conductive gate formed by the partition wall (520) on the first side wall; and (i) Doping dopants in the semiconductor first region by using the lithography mask pattern (1710) as a mask. 2. The method according to claim 1, characterized in that, before forming the second layer (128), the first layer (124) is formed into strips at an angle to the predetermined direction and the grooves are The same direction as the strip runs through a row of non-volatile memory cells. 3. The method of claim 2, wherein the method for forming the first layer (124) further comprises: lithographically patterning a lithographic mask pattern on the first layer to define the strips of the first layer; and The trenches are defined (910) using the lithography mask pattern. 4. The method of claim 1, wherein: Each of the first structures includes a second sidewall; The lithographic mask pattern process includes depositing and lithographically patterning a lithographic mask pattern to cover at least part of the partition on the first sidewall of the first structure and cover the adjacent first structure. A first semiconductor substrate and a region between the first sidewalls. 5. The method according to claim 4, wherein each of the second semiconductor substrate regions extends between two adjacent first structures and provides a bonding portion for all memory between two adjacent first structures Source/drain regions (1810) of cells, wherein the source/drain regions (1810) are electrically connected to each other. 6. The method of claim 4, further comprising using the lithographic mask pattern to completely or partially etch away the insulating material in the trench in the second semiconductor substrate region. 7. The method as claimed in claim 6, further comprising removing the lithography mask pattern after completely or partially etching and removing the insulating material in the trench, and forming the first and second semiconductor substrates dopant doped in the region. 8. The method of claim 1, wherein the first layer (124) comprises a polysilicon layer, and the second layer (128) comprises a polysilicon layer and a metal silicide layer. 9. The method of claim 1, wherein: Before forming the second layer, the first layer has a plurality of rectangular openings, but the area where the source line will be formed is covered by the first layer; The trench is formed by etching down the semiconductor first region from the rectangular opening; and Step (e) includes removing the first layer from over the source line region. 10. The method of claim 1, further comprising the following steps to form the second metal oxide semiconductor transistor: When forming the first insulating layer (108) and the first layer (124) on the first region of the semiconductor, the first insulating layer (108) and the first layer (124) are also simultaneously formed on a second region of the semiconductor; removing the first layer (124) and the first insulating layer (108) of a second region of the integrated circuit; Also forming a second insulating layer (98) on the second region while performing (c) step; When step (c) is performed, a second layer (128) is also formed on the second insulating layer (98) in the second region to form a second metal oxide semiconductor transistor. 11. The method according to claim 10, characterized in that the thickness of the second insulating layer (98) is different from that of the first insulating layer (108). 12. The method as claimed in claim 1, further comprising the step of: forming a third metal oxide semiconductor transistor: When forming the first insulating layer (108) in the first region and the second region, the first insulating layer (108) is also formed in the third region at the same time; removing the first insulating layer (108) from the second and third regions and forming a third insulating layer on the second and third regions prior to forming the first layer (124); and When removing the first layer (124) from the second region, simultaneously pattern the first layer (124) in the first and third regions to provide the first and third metal-oxide-semiconductor transistors conductive gate. 13. The method of claim 12, wherein after forming the second layer (128), the thicknesses of the first insulating layer, the second insulating layer, and the third insulating layer are all different. same. 14. The method of claim 12, wherein when forming the third insulating layer, the thickness of the first insulating layer located in the first region increases. 15. The method of claim 1, wherein the integrated circuit comprises a non-volatile memory cell comprising (a) a conductive gate formed from part of the first layer (124) and (b) A conductive gate formed from the second layer (128). 16. The method according to claim 15, further comprising: before the step of forming the first insulating layer (108): forming a gate insulating layer on the semiconductor substrate, the memory cell will be formed in a region of the integrated circuit; forming a conductive layer on the gate insulating layer to provide a floating gate for the memory cell; and The conductor layer and the gate insulating layer are removed from the first and second regions. 17. The method of claim 16, further comprising forming an insulating layer over the conductive layer to isolate the conductive layer from the first layer. 18. A method of fabricating an integrated circuit comprising a non-volatile memory, the method comprising: forming an insulating layer (108), wherein the integrated circuit includes a plurality of non-volatile memory cells, and the insulating layer (108) is used as a gate insulating layer of the non-volatile memory cells; forming a first layer (124) as a floating gate for the non-volatile memory cells; forming an insulating layer (98) on the floating gate on the first layer (124) of the memory cells; Remove the upper insulating layer (98), the first layer and the insulating layer (108) of the floating gate in sequence from the high-voltage area, high-speed area, and I/O area around the non-volatile memory cell of the integrated circuit, and use to form at least one peripheral metal-oxide-semiconductor transistor on each of the high-voltage area, the high-speed area, and the I/O area; forming a first gate insulating layer (4408) in the high-voltage area, high-speed area, and I/O area; removing the first gate insulating layer from the high speed region, I/O region (4408); forming a second gate insulating layer (4410) in the high-speed area and the I/O area; A second layer (128) is formed on the floating gate upper insulating layer (98), the first gate insulating layer (4408), and the second gate insulating layer (4410), wherein the the metal oxide semiconductor transistor has a conductive gate formed from part of the second layer; removing the second layer (128) and second gate insulating layer (4410) from the I/O region; forming a third gate insulating layer (1810) in the I/O region; and High temperature oxidation of the first layer and the second layer on the side wall of the memory cell; forming a third layer (520) on the memory cells and metal-oxide-semiconductor transistors in the high-voltage region and the high-speed region; forming a lithography mask pattern on the I/O region to define a metal oxide semiconductor transistor; performing anisotropic etching so that the third layer (520) forms partitions on the side walls of the memory cells, the metal oxide semiconductor transistors in the high voltage region and the metal oxide semiconductor transistors in the high speed region; forming another lithography mask pattern to protect the partition walls on each side of the memory cells; removing all of the unpatterned third layer for forming metal oxide semiconductor transistors on the I/O region; Wherein the first gate insulating layer located in the high voltage region is thicker than the second gate insulating layer and also thicker than the third gate insulating layer, and the third gate insulating layer (1810) is thicker than the first gate insulating layer The second gate insulating layer (4410) is thick. 19. The method according to claim 18, further comprising forming a dummy structure around the I/O area, the dummy structure is the same as the metal oxide semiconductor transistor in the high-speed area, and the second layer After the step is formed, before removing the second layer (128) and the second gate insulating layer (4410) from the I/O region, a protective layer (720) is formed on the metal oxide of the high voltage region and high speed region The top of the semi-transistor and these memory cells to protect the third layer of the I/O area metal oxide semi-transistor.

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