CN120011284B - A CAN communication driving circuit with adaptive input impedance - Google Patents

Abstract

The invention provides a CAN communication driving circuit with self-adaptive input impedance, which comprises an output voltage monitoring circuit, a CANH step-by-step opening control circuit, a CANL step-by-step opening control circuit, a CANH self-adaptive impedance matching driving circuit and a CANL self-adaptive impedance matching driving circuit, wherein the output voltage monitoring circuit is used for detecting the voltage of a CANH port and the voltage of the CANL port, comparing the detected voltage of the CANH port and the detected voltage of the CANL port with a reference value of CANH and a reference value of CANL respectively and outputting a first comparison result signal and a second comparison result signal, the CANH step-by-step opening control circuit outputs a switch control signal to control the step-by-step closing of switches in m parallel branches in the CANH self-adaptive impedance matching driving circuit according to the first comparison result signal, and the CANL step-by-step opening control circuit outputs a switch control signal to control the step-by-step closing of switches in n parallel branches in the CANL self-adaptive impedance matching driving circuit according to the second comparison result signal.

Description

CAN communication driving circuit with self-adaptive input impedance

Technical Field

The invention relates to the technical field of integrated circuits, in particular to a CAN communication driving circuit with self-adaptive input impedance.

Background

In industrial electronics and automotive electronics, CAN bus communications are generally classified into protocol control and CAN physical layers because of their high speed, strong anti-interference capability, and extremely wide application in bus interconnect communications. The protocol control is divided into a host and a Slave, in the automotive application, the host and the Slave are far away from each other, so that a special CAN physical layer chip is required to perform signal driving conversion at both the host end and the Slave end, as shown in figure 1, the host (Master) CAN transmit data to a transmission chip 1 (CAN PHY chip) through a local TX/RX interface, the transmission chip 1 chip CAN convert a single-ended signal into a common-mode interface signal and perform remote transmission through a CANH/CANL bus, and a transmission chip 2 (CAN PHY chip) at the Slave end receives the CANH/CANL signal, converts the signal into a local single-ended signal TX/RX and transmits the signal to a Slave module to complete data transmission.

In automotive electronics, the slave devices of two communication buses, namely CANH and CANL, are various, and the number of slaves in different applications is also different, when the number of nodes on the CAN bus is different, the equivalent impedance of the CAN bus also changes greatly, when the equivalent impedance changes, the driving voltage of the nodes on the CAN bus also changes when the nodes transmit high and low electric potentials, which may lead to that the driving output characteristics of the CAN bus interfaces of part of the nodes cannot meet the electromagnetic compatibility and signal integrity of the bus system, and cause communication abnormality, resulting in systematic risks.

In order to improve the withstand voltage of the CAN bus interface end, a CAN PHY chip usually adopts a driving mode of combining a high-voltage-resistant MOS tube and an anti-reflection diode at an output stage. In general, the output current of the CAN bus chip is defined as a dominant mode when the bus voltage difference generated on the external load Rload is high level voltage drop, the output current of the CAN bus chip is shut down, the bus voltage difference generated on the external load Rload is low level voltage drop, and the conventional CAN bus chip driving stage is shown in fig. 2, wherein IB is a driving output reference current source, in the dominant state, en_dom=1, the canl end is a mirror image of N2 and N1, I _CANL=I_dom =β×ib, β is a size ratio of N2 and N1, and the CANH end is a current of P2 mirror image P1, I _CANH=I_P2=β*I_P1=β*I_N3=β*IB=I_CANL. When the recessive state is in a dominant state, the currents of the high side CANH and the low side CANL are equal, the purpose of output driving matching is achieved, and the dominant differential voltage V _DOM=V_CANH-V_CANL=I_CANH*R_LOAD is achieved. In the recessive state, en_dom=0, N6 is turned on, pull down the gate terminal of N2 to GND, turn off N2I _dom =0, and at the same time, P3 is turned on, pull up the gate terminal of P2 to power VCC, P2 is turned off, I _dom =0, at which time recessive differential voltage V _REC =0.

However, the scheme has two defects in dealing with the abnormal protection of the car gauge CAN transceiver chip:

1. the switching speed of the dominant mode and the recessive mode is too high when the CAN bus is in communication, slope control is not performed, and larger noise interference CAN be generated when the CAN bus is in communication.

2. When the Rload changes due to different nodes on the CAN bus, the Rload may have a large difference, so that the consistency of V _DOM is poor, which may make it impossible for devices on the bus to correctly recognize the state of the CAN bus.

Therefore, the drive output circuit of the traditional CAN transceiver chip CAN not meet the requirements of a system in vehicle-mounted application on high signal integrity and low electromagnetic radiation interference of multiple nodes of the CAN transceiver chip.

Disclosure of Invention

The invention aims to provide a CAN communication driving circuit with self-adaptive input impedance, which CAN improve the impedance matching characteristic of a vehicle-mounted CAN bus chip in the communication output process, so that an interface of the CAN bus chip has better driving compatibility characteristic and signal integrity characteristic.

In order to achieve the above object, the present invention provides a CAN communication driving circuit with adaptive input impedance, comprising:

The device comprises an output voltage monitoring circuit, a CANH step-by-step starting control circuit, a CANL step-by-step starting control circuit, a CANH self-adaptive impedance matching driving circuit and a CANL self-adaptive impedance matching driving circuit;

The output voltage monitoring circuit is used for detecting the voltage of the CANH port and the voltage of the CANL port, comparing the detected voltage of the CANH port and the detected voltage of the CANL port with a reference value of CANH and a reference value of CANL respectively, and outputting a first comparison result signal and a second comparison result signal;

The CANH self-adaptive impedance matching driving circuit and the CANL self-adaptive impedance matching driving circuit comprise a plurality of parallel branches, and each branch comprises a switch and a resistor which are connected in series;

in dominant mode:

When the voltage of the CANL port does not reach the reference value, the CANL step-by-step starting control circuit receives the second comparison result signal;

The CANH step-by-step starting control circuit outputs a switch control signal SP <1:m > (m is an integer greater than 1) under the driving of a clock signal according to the first comparison result signal to control the switches in the m parallel branches in the CANH self-adaptive impedance matching driving circuit to be closed step by step, so that the resistors are connected in parallel step by step, and the voltage of a CANH port finally reaches a reference value;

and the CANL step-by-step opening control circuit outputs a switch control signal SN <1:n > (n is an integer greater than 1) under the driving of a clock signal according to the second comparison result signal to control the switches in the n parallel branches in the CANL self-adaptive impedance matching driving circuit to be closed step by step, so that the resistors are connected in parallel step by step, and the voltage of the CANL port finally reaches a reference value.

In an alternative scheme, the CANH step-by-step start control circuit includes:

Each CANH single-stage starting control circuit comprises a first trigger, a second inverter and a second AND gate;

the input end of the first trigger of the first CANH single-stage starting control circuit is used for inputting the first comparison result signal, and the input end of the first trigger of the following CANH single-stage starting control circuit is connected with the output end of the second AND gate of the previous CANH single-stage starting control circuit;

The output end of a first trigger of the CANH single-stage starting control circuit is connected with the input end of the second inverter, one input end of the second AND gate is connected with the input end of the first trigger, and the other input end of the second AND gate is connected with the output end of the second inverter;

One input end of the first AND gate is used for inputting the first comparison result signal, the other input end of the first AND gate is used for inputting a clock signal, and the output end of the first AND gate is connected with the clock signal input end of each first trigger.

In an alternative solution, the CANL step-by-step start control circuit includes:

The system comprises a third AND gate, n CANL single-stage starting control circuits, a first logic circuit, a second logic circuit and a third logic circuit, wherein the n CANL single-stage starting control circuits are cascaded, and each CANL single-stage starting control circuit comprises a second trigger and a fourth AND gate;

the input end of the second trigger of the first CANL single-stage starting control circuit is used for inputting the second comparison result signal, and the input end of the second trigger of the following single-stage starting control circuit is connected with the output end of the fourth AND gate of the previous CANL single-stage starting control circuit;

One input end of a fourth AND gate of the CANL single-stage start control circuit is connected with the input end of the second trigger, and the other input end of the fourth AND gate is connected with the output end of the second trigger, wherein the output end of each second trigger outputs the switch control signal SN <1:n >;

One input end of the third AND gate is used for inputting the second comparison result signal, the other input end of the third AND gate is used for inputting a clock signal, and the output end of the third AND gate is connected with the clock signal input end of each second trigger.

In an alternative scheme, the switches in the CANH adaptive impedance matching driving circuit are all MOS transistors, and the CANH adaptive impedance matching driving circuit further includes:

the first high-voltage MOS tube and the first inverter;

the first high-voltage MOS tube is connected between the CANH port and the m parallel branches, and the other ends of the m parallel branches are connected with a power supply;

The input end of the first inverter is used for inputting an enable signal EN-DOM, and the output end of the first inverter is connected with the grid electrode of the first high-voltage MOS tube;

The grid electrodes of the MOS transistors are respectively used for inputting the switch control signals SP <1:m >.

In an alternative solution, the switch in the CANL adaptive impedance matching driving circuit is a MOS transistor, and the CANL adaptive impedance matching driving circuit further includes:

The second high-voltage MOS tube is connected between the CANL port and the n parallel branches, and the other ends of the n parallel branches are connected to the ground;

the grid electrode of the second high-voltage MOS tube is used for inputting an enable signal EN-DOM;

the grid electrodes of the MOS transistors are respectively used for inputting the switch control signals SN <1:n >.

In an alternative scheme, the first high-voltage MOS tube is a high-voltage PMOS tube, and the MOS tube in the CANH self-adaptive impedance matching driving circuit is a PMOS tube;

The drain electrode of the high-voltage PMOS tube is connected with the anode of the first diode at the CANH end, the source electrode of the high-voltage PMOS tube is connected with the drain electrode of each PMOS tube in the m parallel branches, and the source electrode of each PMOS tube is connected with a resistor.

In the alternative scheme, the second high-voltage MOS tube is a high-voltage NMOS tube, and the MOS in the CANL self-adaptive impedance matching driving circuit is an NMOS tube;

the drain electrode of the high-voltage NMOS tube is connected with the cathode of the second diode at the CANL end, the source electrode of the high-voltage NMOS tube is connected with the drain electrode of each NMOS tube in the n parallel branches, and the source electrode of each NMOS tube is connected with a resistor.

In an alternative, the output voltage monitoring circuit includes:

The first voltage dividing resistor, the second voltage dividing resistor, the third voltage dividing resistor, the first reference current source, the second reference current source, the third diode, the fourth diode, the first comparator and the second comparator;

One end of the first voltage dividing resistor is connected with a power supply, the other end of the first voltage dividing resistor is connected with one end of the second voltage dividing resistor, the other end of the second voltage dividing resistor is connected with one end of the third voltage dividing resistor, and the other end of the third voltage dividing resistor is grounded;

One end of the first reference current source is connected with a power supply, the other end of the first reference current source is connected with the anode of the third diode, and the cathode of the third diode is connected between the first voltage dividing resistor and the second voltage dividing resistor;

The anode of the fourth diode is connected between the second voltage dividing resistor and the third voltage dividing resistor, the cathode of the fourth diode is connected with one end of the second reference current source, and the other end of the second reference current source is grounded;

The positive input end of the first comparator is connected to the joint of the first high-voltage MOS tube and the m parallel branches, the negative input end of the first comparator is connected to the anode of the third diode, and the output end of the first comparator outputs the first comparison result signal;

And the positive input end of the second comparator is connected to the joint of the second high-voltage MOS tube and the n parallel branches, the negative input end of the second comparator is connected to the cathode of the fourth diode, and the output end of the second comparator outputs the second comparison result signal.

The invention has the beneficial effects that:

1. by monitoring the voltage on the CAN bus, the voltages of CANH and CANL are adaptively adjusted to reach the reference value, and the voltage is not influenced by the number of output nodes and the load impedance on the bus.

2. The dominant mode and the recessive mode are switched by adopting a mode of step-by-step control of a multi-level switch, the starting slope of the switching-on/switching-off control is not influenced by parameters of an output-stage MOS tube (MOS tube P2/MOS tube N2 in fig. 2) V _TH,C_GS, and the switching-on/switching-off control is controlled by an internal accurate high-frequency clock, so that the electromagnetic compatibility of chips is better, and the consistency among chips is better.

Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.

Fig. 1 is a schematic diagram of CAN bus communication in automotive electronics applications in the prior art.

Fig. 2 is a circuit diagram of a dominant mode output driving stage of a CAN bus transceiver chip in the prior art.

Fig. 3 is a schematic diagram of a CAN communication driving circuit with adaptive input impedance according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of an output voltage monitor circuit and a CANH/CANL step-by-step on control circuit according to an embodiment of the invention.

Fig. 5 is a driving waveform diagram of a CAN communication driving circuit with adaptive input impedance according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Examples

Referring to fig. 3 to 5, the present embodiment provides a CAN communication driving circuit with adaptive input impedance, including:

The device comprises an output voltage monitoring circuit, a CANH step-by-step starting control circuit, a CANL step-by-step starting control circuit, a CANH self-adaptive impedance matching driving circuit and a CANL self-adaptive impedance matching driving circuit;

The output voltage monitoring circuit is used for detecting the voltage of the CANH port and the voltage of the CANL port, comparing the detected voltage of the CANH port and the detected voltage of the CANL port with a reference value of CANH and a reference value of CANL respectively, and outputting a first comparison result signal CANH_CMPOUT and a second comparison result signal CANL_CMPOUT;

The CANH self-adaptive impedance matching driving circuit and the CANL self-adaptive impedance matching driving circuit comprise a plurality of parallel branches, and each branch comprises a switch and a resistor which are connected in series;

in dominant mode:

When the voltage of the CANL port does not reach the reference value, the CANL step-by-step starting control circuit receives the second comparison result signal;

The CANH step-by-step starting control circuit outputs a switch control signal SP <1:m > (m is an integer greater than 1) under the driving of a clock signal according to the first comparison result signal to control the switches in the m parallel branches in the CANH self-adaptive impedance matching driving circuit to be closed step by step, so that resistors are connected in parallel step by step, the impedance matching effect is achieved, and the voltage of a CANH port finally reaches a reference value;

and the CANL step-by-step opening control circuit outputs a switch control signal SN <1:n > (n is an integer greater than 1) under the driving of a clock signal according to the second comparison result signal to control the switches in the n parallel branches in the CANL self-adaptive impedance matching driving circuit to be closed step by step, so that the resistors are connected in parallel step by step, the impedance matching effect is achieved, and the voltage of the CANL port finally reaches a reference value.

IN this embodiment, the CANH step-by-step start control circuit includes a first and gate NAND1 and m cascaded CANH single-stage start control circuits canh_ctr, each of the CANH single-stage start control circuits canh_ctr includes a first flip-flop DFF1, a second inverter INV2 and a second and gate NAND2, an input terminal of the first flip-flop DFF1 of the first CANH single-stage start control circuit canh_ctr is used for inputting the first comparison result signal, an input terminal of the first flip-flop DFF1 of the following CANH single-stage start control circuit canh_ctr is connected to an output terminal of the second and gate NAND2 of the preceding CANH single-stage start control circuit canh_ctr, an output terminal of the first flip-flop DFF1 of the second and gate NAND2 are connected to an input terminal of the second inverter INV2, an input terminal of the second and a reset signal for inputting the first and a reset signal for the first gate signal for the first and a reset signal for the second gate NAND 1.

IN this embodiment, the CANL step-by-step start control circuit includes a third and gate NAND3 and n CANL single-stage start control circuits canl_ctr IN cascade, each CANL single-stage start control circuit canl_ctr includes a second flip-flop DFF2 and a fourth and gate NAND4, an input terminal of the second flip-flop DFF2 of the CANL single-stage start control circuit canl_ctr is used for inputting the second comparison result signal, an input terminal of the second flip-flop DFF2 of the following CANL single-stage start control circuit canl_ctr is connected to an output terminal of the fourth and gate NAND4 of the previous CANL single-stage start control circuit canl_ctr, one input terminal of the fourth and gate NAND4 of the CANL single-stage start control circuit canl_ctr is connected to an input terminal of the second flip-flop DFF2, another input terminal of the fourth and gate NAND4 is connected to an output terminal of the second flip-flop DFF2, an input terminal of the second flip-flop DFF2 is used for outputting the second comparison result signal, and another input terminal of the second and gate NAND 2 is used for outputting another reset signal.

In the embodiment, the switches in the CANH adaptive impedance matching driving circuit are all MOS transistors, the CANH adaptive impedance matching driving circuit further comprises a first high-voltage MOS transistor and a first inverter INV1, the first high-voltage MOS transistor is connected between a CANH port and the m parallel branches, the other ends of the m parallel branches are connected with a power supply VCC, the input end of the first inverter INV1 is used for inputting an enable signal EN-DOM, the output end of the first inverter INV1 is connected with the grid electrode of the first high-voltage MOS transistor, and the grid electrodes of the MOS transistors are respectively used for inputting a switch control signal SP <1:m >.

In this embodiment, the first high-voltage MOS transistor is a high-voltage PMOS transistor HVMP, the MOS transistor in the CANH adaptive impedance matching driving circuit is a PMOS transistor, the drain electrode of the high-voltage PMOS transistor HVMP is connected to the anode of the first diode D1 at the CANH end, the source electrode of the high-voltage PMOS transistor HVMP is connected to the drain electrode of each PMOS transistor in the m parallel branches, and the source electrode of each PMOS transistor is connected to a resistor (as shown in fig. 3, the source electrode of the first PMOS transistor MP1 is connected to the first resistor R1, the source electrode of the second PMOS transistor MP2 is connected to the second resistor R2, and the source electrode of the tenth PMOS transistor MP10 is connected to the tenth resistor R10).

In this embodiment, the switch in the CANL adaptive impedance matching driving circuit is a MOS transistor, and the CANL adaptive impedance matching driving circuit further includes a second high-voltage MOS transistor, the second high-voltage MOS transistor is connected between a CANL port and the n parallel branches, the other ends of the n parallel branches are connected to ground, a gate of the second high-voltage MOS transistor is used for inputting an enable signal EN-DOM, and gates of the MOS transistors are respectively used for inputting the switch control signals SN <1:n >.

In this embodiment, the second high-voltage MOS transistor is a high-voltage NMOS transistor HVMN, the MOS in the CANL adaptive impedance matching driving circuit is an NMOS transistor, the drain electrode of the high-voltage NMOS transistor HVMN is connected to the cathode of the second diode D2 at the CANL end, the source electrode of the high-voltage NMOS transistor HVMN is connected to the drain electrode of each NMOS transistor in the n parallel branches, and the source electrode of each NMOS transistor is connected to a resistor.

In this embodiment, the output voltage monitoring circuit includes a first voltage dividing resistor RH, a second voltage dividing resistor RDM, a third voltage dividing resistor RL, a first reference current source IB1, a second reference current source IB2, a third diode D3, a fourth diode D4, a first comparator CMP1 and a second comparator CMP2; one end of the first voltage dividing resistor RH is connected with the power supply VCC, the other end of the first voltage dividing resistor RH is connected with one end of the second voltage dividing resistor RDM, the other end of the second voltage dividing resistor RDM is connected with one end of the third voltage dividing resistor RL, the other end of the third voltage dividing resistor RL is grounded, one end of the first reference current source IB1 is connected with the power supply VCC, the other end of the first reference current source IB1 is connected with an anode of the third diode D3, a cathode of the third diode D3 is connected between the first voltage dividing resistor RH and the second voltage dividing resistor RDM, an anode of the fourth diode D4 is connected between the second voltage dividing resistor RDM and the third voltage dividing resistor RL, a cathode of the fourth diode D4 is connected with one end of the second reference current source IB2, the other end of the second reference current source IB2 is grounded, a positive input end of the first comparator CMP1 is connected with the first high voltage MOS tube in parallel connection with the m (voltage is V65 here), a negative input end (input voltage is V _{CANH_REF}) is connected with the third diode D3 in parallel, a negative input end is connected with the second voltage (37 n is connected with the second voltage 37 n-phase comparator) of the second voltage is connected with the second input end of the second voltage 37 is connected with the second voltage 37 n-phase of the second MOS, and the output end outputs the second comparison result signal.

In this embodiment, taking a CANH adaptive impedance matching driving circuit as an example, it is assumed that m=10 (10 parallel branches, the number of m can be adjusted according to the application requirement, the principle is not changed due to different numbers of m and is within the protection range of the scheme), when the chip enters the dominant mode, the enable signal en_dom=1, the first high-voltage PMOS transistor HVMP is turned on, the driving current flows from the power supply VCC to the CANH port, when only SP <1> =0, SP <2:10> =1, the first PMOS transistor MP1 is turned on, the input equivalent impedance of CANH is R _CANH =r1, when SP <1:10> =0, the first PMOS transistor MP1 to the tenth PMOS transistor MP10 are all turned on, and the input equivalent impedance of CANH is R _CANH =r1// r2// r3///////////r9// r10. As is known from the above description, the input impedance of CANH is dynamically adjusted according to the voltage of the CANH port.

The principle of the CANL adaptive impedance matching driving circuit is as described above. Assuming that n=10 (10 parallel branches, the number of n can be adjusted according to the application requirement, the principle is not changed due to different numbers of n and is within the protection scope of the present embodiment), when the chip enters the dominant mode, the enable signal en_dom=1, the second high-voltage NMOS transistor HVMN is turned on, the driving current flows from the CANL port to the ground GND, when SN <1> =1, SN <2:10> =0, the first NMOS transistor MN1 is turned on, the input equivalent impedance of CANL is R _CANL =r1a, when SN <1:10> =1, the first NMOS transistor MN1 to the tenth NMOS transistor MN10 are all turned on, and the input equivalent impedance of CANL is R _CANL =r1a// r2a// r3a///i. Usually r1a=r2a=. RnA, as can be seen from the above description, the input impedance of CANL is dynamically adjusted according to the voltage of the CANL port.

The process of dynamic adjustment is described below in conjunction with the schematic implementation of the output voltage monitor circuit and the step-by-step on control circuit of fig. 4. The first voltage dividing resistor RH, the second voltage dividing resistor RDM, and the third voltage dividing resistor RL function to generate a dominant mode reference voltage V _{CANH_int} (typically 3.5V when vcc=5V) of CANH and a dominant mode reference voltage V _{CANL_int} (typically 1.5V when vcc=5V) of CANL by performing resistive voltage division on the power supply VCC. In consideration of voltage drops of signals on the anti-reflection diodes (the first diode D1 and the second diode D2), the third diode D3 and the fourth diode D4 are superimposed on the V _{CANH_int} and the V _{CANL_int}, and compared with V _{CANH_FB} (voltage at the connection of the first high-voltage MOS transistor and the CANH adaptive impedance matching driving circuit) and V _{CANL_FB} (voltage at the connection of the second high-voltage MOS transistor and the CANL adaptive impedance matching driving circuit), respectively, and the outputs of the CANH-side first comparator CMP1 and the CANL-side second comparator CMP2 are the first comparison signal canh_cmpout and the second comparison signal canl_cmpout, respectively. IN the CANH step-by-step start control circuit, the first flip-flop DFF1, the second inverter INV2, and the second and gate NAND2 form a single-stage start control circuit canh_ctr, the first comparison signal canh_cmpout is an input signal thereof, the signal clk_in1 after the canh_cmpout and the clock signal clk_in (e.g., 200 MHz) pass through the first and gate NAND1 is a clock input signal of canh_ctr, the enable signal en_dom is a reset control signal of the module, and SP <1:m > is an output of canh_ctr. Wherein SP <1> is connected with the grid electrode of the first PMOS tube MP1 of the driving circuit. similarly, a second flip-flop DFF2, The fourth and gate NAND4 constitutes a single-stage on control circuit canl_ctr, the second comparison signal canl_cmpout is an input signal thereof, the signal clk_in2 after passing through the third and gate NAND3 is a clock input signal of canl_ctr, the enable signal en_dom is a module reset control signal, SN <1:n > is an output of canl_ctr, and SN <1> is connected to the gate of the first NMOS transistor MN1 of the driving circuit. the number of m and n may be equal or different, and the number of stages of the step-wise on control circuit is identical to the number of switching stages in the driving circuit, as shown in fig. 4, 10 stages being exemplified here for convenience of explanation.

When the chip works IN the recessive mode, V _CANH=V_CANL =2.5v, en_dom=0, when the chip changes from the recessive mode to the dominant mode, en_dom=1, V _{CANH_FB}<V_{CANH_REF},CANH_CMPOUT=1, V_{CANL_FB}>V_{CANL_REF}, canl_cmpout=1, when the rising edge of the clock signal clk_in comes, SP <1> =0, SN <1> =1, so as to control the first PMOS transistor MP1 and the first NMOS transistor MN1 to be turned on, current flows from the CANH port to the CANL port, the CANH voltage gradually increases as the rising edge of the clk_in comes, the CANL voltage gradually decreases, when the CANH and CANL port voltages reach the reference value, V _{CANH_FB}>V_{CANH_REF},CANH_CMPOUT=0, V_{CANL_FB}<V_{CANL_REF}, canl_cmpout=0, and when the rising edge of the clock clk_in comes, the states of SP <1:m > and SN <1:n > do not change any more, and the driving circuit keeps the current output, so as to generate the driving voltage IN the dominant mode.

The CAN communication driving circuit with the self-adaptive input impedance has the characteristics of self-adaptive input impedance matching, high bus output voltage consistency and good electromagnetic compatibility, and the CAN bus transceiver chip output control circuit of the embodiment CAN be widely applied to vehicle-mounted communication chips.

According to the embodiment, through detecting the switching state of the dominant mode and the recessive mode, the CANH interface and the CANL interface are simultaneously subjected to voltage monitoring and step-by-step opening during CAN bus communication, so that the output differential pressure VDOM of the CAN bus in the dominant mode does not change along with the node number (slave) on the bus, and meanwhile, the step-by-step opening control circuit reduces electromagnetic interference and bus disturbance, so that the impedance matching characteristic and electromagnetic compatibility of the CAN bus are improved.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (8)

1. A CAN communication driver circuit with adaptive input impedance, comprising:

The device comprises an output voltage monitoring circuit, a CANH step-by-step starting control circuit, a CANL step-by-step starting control circuit, a CANH self-adaptive impedance matching driving circuit and a CANL self-adaptive impedance matching driving circuit;

The output voltage monitoring circuit is used for detecting the voltage of the CANH port and the voltage of the CANL port, comparing the detected voltage of the CANH port and the detected voltage of the CANL port with a reference value of CANH and a reference value of CANL respectively, and outputting a first comparison result signal and a second comparison result signal;

The CANH self-adaptive impedance matching driving circuit and the CANL self-adaptive impedance matching driving circuit comprise a plurality of parallel branches, and each branch comprises a switch and a resistor which are connected in series;

in dominant mode:

When the voltage of the CANL port does not reach the reference value, the CANL step-by-step starting control circuit receives the second comparison result signal;

The CANH step-by-step starting control circuit outputs a switch control signal SP <1:m > under the drive of a clock signal according to the first comparison result signal, and m is an integer greater than 1, so as to control the switches in m parallel branches in the CANH self-adaptive impedance matching driving circuit to be closed step by step, thereby connecting resistors in parallel step by step, and finally enabling the voltage of a CANH port to reach a reference value;

And the CANL step-by-step opening control circuit outputs a switch control signal SN <1:n > under the driving of a clock signal according to the second comparison result signal, wherein n is an integer greater than 1, so as to control the switches in n parallel branches in the CANL self-adaptive impedance matching driving circuit to be closed step by step, thereby connecting resistors in parallel step by step and enabling the voltage of a CANL port to finally reach a reference value.

2. The adaptive input impedance CAN communication driver circuit of claim 1 wherein the CANH step-wise turn-on control circuit comprises:

Each CANH single-stage starting control circuit comprises a first trigger, a second inverter and a second AND gate;

the input end of the first trigger of the first CANH single-stage starting control circuit is used for inputting the first comparison result signal, and the input end of the first trigger of the following CANH single-stage starting control circuit is connected with the output end of the second AND gate of the previous CANH single-stage starting control circuit;

The output end of a first trigger of the CANH single-stage starting control circuit is connected with the input end of the second inverter, one input end of the second AND gate is connected with the input end of the first trigger, and the other input end of the second AND gate is connected with the output end of the second inverter;

One input end of the first AND gate is used for inputting the first comparison result signal, the other input end of the first AND gate is used for inputting a clock signal, and the output end of the first AND gate is connected with the clock signal input end of each first trigger.

3. The adaptive input impedance CAN communication driver circuit of claim 1 wherein the CANL step-wise turn-on control circuit comprises:

The system comprises a third AND gate, n CANL single-stage starting control circuits, a first logic circuit, a second logic circuit and a third logic circuit, wherein the n CANL single-stage starting control circuits are cascaded, and each CANL single-stage starting control circuit comprises a second trigger and a fourth AND gate;

the input end of the second trigger of the first CANL single-stage starting control circuit is used for inputting the second comparison result signal, and the input end of the second trigger of the following single-stage starting control circuit is connected with the output end of the fourth AND gate of the previous CANL single-stage starting control circuit;

One input end of a fourth AND gate of the CANL single-stage start control circuit is connected with the input end of the second trigger, and the other input end of the fourth AND gate is connected with the output end of the second trigger, wherein the output end of each second trigger outputs the switch control signal SN <1:n >;

One input end of the third AND gate is used for inputting the second comparison result signal, the other input end of the third AND gate is used for inputting a clock signal, and the output end of the third AND gate is connected with the clock signal input end of each second trigger.

4. The CAN communication driver circuit of claim 1, wherein the switches in the CANH adaptive impedance matching driver circuit are all MOS transistors, the CANH adaptive impedance matching driver circuit further comprising:

the first high-voltage MOS tube and the first inverter;

the first high-voltage MOS tube is connected between the CANH port and the m parallel branches, and the other ends of the m parallel branches are connected with a power supply;

The input end of the first inverter is used for inputting an enable signal EN-DOM, and the output end of the first inverter is connected with the grid electrode of the first high-voltage MOS tube;

The grid electrodes of the MOS transistors are respectively used for inputting the switch control signals SP <1:m >.

5. The CAN communication driver circuit of claim 4, wherein the switch in the CANL adaptive impedance matching driver circuit is a MOS transistor, the CANL adaptive impedance matching driver circuit further comprising:

The second high-voltage MOS tube is connected between the CANL port and the n parallel branches, and the other ends of the n parallel branches are connected to the ground;

the grid electrode of the second high-voltage MOS tube is used for inputting an enable signal EN-DOM;

the grid electrodes of the MOS transistors are respectively used for inputting the switch control signals SN <1:n >.

6. The CAN communication driving circuit of the adaptive input impedance of claim 4, wherein the first high voltage MOS transistor is a high voltage PMOS transistor, and the MOS transistor in the CANH adaptive impedance matching driving circuit is a PMOS transistor;

The drain electrode of the high-voltage PMOS tube is connected with the anode of the first diode at the CANH end, the source electrode of the high-voltage PMOS tube is connected with the drain electrode of each PMOS tube in the m parallel branches, and the source electrode of each PMOS tube is connected with a resistor.

7. The CAN communication drive circuit of self-adaptive input impedance of claim 5, wherein the second high voltage MOS tube is a high voltage NMOS tube, and the MOS in the CANL self-adaptive impedance matching drive circuit is an NMOS tube;

the drain electrode of the high-voltage NMOS tube is connected with the cathode of the second diode at the CANL end, the source electrode of the high-voltage NMOS tube is connected with the drain electrode of each NMOS tube in the n parallel branches, and the source electrode of each NMOS tube is connected with a resistor.

8. The adaptive input impedance CAN communication driver circuit of claim 5 wherein the output voltage monitoring circuit comprises:

The first voltage dividing resistor, the second voltage dividing resistor, the third voltage dividing resistor, the first reference current source, the second reference current source, the third diode, the fourth diode, the first comparator and the second comparator;

One end of the first voltage dividing resistor is connected with a power supply, the other end of the first voltage dividing resistor is connected with one end of the second voltage dividing resistor, the other end of the second voltage dividing resistor is connected with one end of the third voltage dividing resistor, and the other end of the third voltage dividing resistor is grounded;

One end of the first reference current source is connected with a power supply, the other end of the first reference current source is connected with the anode of the third diode, and the cathode of the third diode is connected between the first voltage dividing resistor and the second voltage dividing resistor;

The anode of the fourth diode is connected between the second voltage dividing resistor and the third voltage dividing resistor, the cathode of the fourth diode is connected with one end of the second reference current source, and the other end of the second reference current source is grounded;

The positive input end of the first comparator is connected to the joint of the first high-voltage MOS tube and the m parallel branches, the negative input end of the first comparator is connected to the anode of the third diode, and the output end of the first comparator outputs the first comparison result signal;

And the positive input end of the second comparator is connected to the joint of the second high-voltage MOS tube and the n parallel branches, the negative input end of the second comparator is connected to the cathode of the fourth diode, and the output end of the second comparator outputs the second comparison result signal.