CN120034194B - A sampling and holding circuit and an electronic chip - Google Patents
A sampling and holding circuit and an electronic chipInfo
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- CN120034194B CN120034194B CN202510496130.7A CN202510496130A CN120034194B CN 120034194 B CN120034194 B CN 120034194B CN 202510496130 A CN202510496130 A CN 202510496130A CN 120034194 B CN120034194 B CN 120034194B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/04—Modifications for accelerating switching
- H03K17/042—Modifications for accelerating switching by feedback from the output circuit to the control circuit
- H03K17/04206—Modifications for accelerating switching by feedback from the output circuit to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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Abstract
The application provides a sample hold circuit and an electronic chip, and relates to the technical field of integrated circuits. The sampling hold circuit comprises a grid voltage bootstrapping main switch module, a grid voltage bootstrapping sub-switch module, a sampling switch tube, a signal tracking switch tube and a pull-up switch tube, wherein the grid voltage bootstrapping main switch module is respectively connected with the grid voltage bootstrapping sub-switch module, the signal tracking switch tube and the pull-up switch tube, the grid voltage bootstrapping main switch module is connected with a grid electrode of the sampling switch tube through a first node, a drain electrode of the pull-up switch tube is connected with a power supply, and the source electrode is connected with a grid electrode of the signal tracking switch tube and the grid voltage bootstrapping main switch module through a second node. The sample hold circuit and the electronic chip provided by the application have the advantages of higher conduction speed and better circuit linearity.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a sample-and-hold circuit and an electronic chip.
Background
The sample-and-hold circuit in the signal chain circuit is generally composed of a switched capacitor, wherein the sampling switch is mainly divided into a single MOS (Metal-Oxide-Semiconductor) switch, a CMOS (Complementary Metal Oxide Semiconductor, complementary Metal-Oxide-Semiconductor) switch and a gate voltage bootstrap switch. The conventional single MOS sampling switch introduces a large nonlinearity into the sampling system because its on-resistance changes with the change of the input signal. The CMOS switch compensates for a part of nonlinearity, but the linearity of a circuit with higher signal requirement is still insufficient, so that a grid voltage bootstrap switch is introduced into a sampling system with certain requirement on linearity to reduce the correlation between the on-resistance of the sampling switch and the sampled signal.
Due to the advent of cloud computing, optical computing, machine learning, and artificial intelligence, data center network demands have grown exponentially, and these emerging technologies place extremely high data throughput rate demands on data centers. To support these increasing bandwidth demands, the development of corresponding high-speed signal processing circuits is urgent, and many conventional circuit technologies or structures are difficult to directly apply to ultra-high-speed circuits, so that optimization improvements are required for the conventional circuits.
The linearity of the sampling switch can be well improved by the traditional grid voltage bootstrap switch, however, the speed of the grid voltage bootstrap switch is limited because the grid voltage bootstrap technology can introduce a feedback loop into the circuit. In addition, with the increase of the signal speed and the sampling speed, in the ultra-high speed signal acquisition system, the size of the sampling capacitor is limited by the speed and the power consumption, and in many applications, the sampling capacitor is only f F stages, so that the nonlinearity of the sampling switch introduced to the signal at f F stages of the sampling node becomes non-negligible. In the prior art, the grid voltage bootstrap switch circuit is connected with a plurality of switches on the sampling node, so that parasitic capacitance of the sampling node is more, the conduction speed of the grid voltage bootstrap switch is influenced, and the linearity of the grid voltage bootstrap switch is also influenced.
In summary, the gate voltage bootstrap switch circuit in the prior art has the problem that the conducting speed and the linearity cannot meet the requirements of the ultra-high-speed signal acquisition system.
Disclosure of Invention
The application aims to provide a sampling hold circuit and an electronic chip, which are used for solving the problem that the on-speed and the linearity of a grid voltage bootstrap switch circuit in the prior art cannot meet the requirements of an ultra-high-speed signal acquisition system.
In order to achieve the above object, the technical scheme adopted by the embodiment of the application is as follows:
In one aspect, an embodiment of the present application provides a sample-hold circuit, where the sample-hold circuit includes a gate voltage bootstrap main switch module, a gate voltage bootstrap sub switch module, a sampling switch tube, a signal tracking switch tube, and a pull-up switch tube, where the gate voltage bootstrap main switch module is connected to the gate voltage bootstrap sub switch module, the signal tracking switch tube, and the pull-up switch tube, the gate voltage bootstrap main switch module is connected to a gate of the sampling switch tube through a first node, a drain of the pull-up switch tube is connected to a power supply, and a source is connected to a gate of the signal tracking switch tube and the gate voltage bootstrap main switch module through a second node;
When the grid voltage bootstrapping main switch module is in a holding stage, a charging loop in the grid voltage bootstrapping sub-switch module is conducted, and bootstrapping capacitors in the grid voltage bootstrapping main switch module and the grid voltage bootstrapping sub-switch module are charged;
when the sampling phase is in, the pull-up switching tube is conducted, the sampling switching tube is driven to be conducted with the signal tracking switching tube, and then the bootstrap circuit inside the grid voltage bootstrap main switching module and the grid voltage bootstrap sub-switching module is conducted, and the grid potential of the sampling switching tube is booted to a set potential.
Optionally, the gate voltage bootstrap main switch module includes a first bootstrap capacitor, a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube and a pull-down component, one end of the first bootstrap capacitor is connected with a drain electrode of the first switch tube and a drain electrode of the signal tracking switch tube through a third node, a source electrode of the first switch tube is grounded, source electrodes of the signal tracking switch tube and the sampling switch tube are all used for receiving an input signal, the other end of the first bootstrap capacitor is respectively connected with a source electrode of the second switch tube and a source electrode of the third switch tube, a drain electrode of the second switch tube is connected to a power supply, a gate electrode of the third switch tube is connected to a gate electrode of the sampling switch tube and the gate voltage bootstrap sub-switch module, a source electrode of the fourth switch tube is connected to the power supply, a drain electrode of the fourth switch tube is connected to a gate electrode of the third switch tube, a source electrode of the fifth switch tube is connected to a third node, a drain electrode of the fifth switch tube is connected to a control node, a drain electrode of the second switch tube is connected to a control node, a pull-down component is connected to a control node, a signal is connected to a pull-down component is connected to the other end of the second switch tube, and the second switch tube is connected to the drain electrode of the second switch tube is connected to the control node,
When the first switch tube, the pull-down assembly, the second switch tube and the fourth switch tube are in a holding stage, the third switch tube and the fifth switch tube are turned off, and the first switch tube, the first bootstrap capacitor and the second switch tube form a charging loop;
when the sampling stage is in, the first switching tube, the pull-down assembly, the second switching tube and the fourth switching tube are turned off, and the third switching tube is turned on with the fifth switching tube.
Optionally, the second switching tube, the third switching tube and the fourth switching tube are P-type tubes, and the first switching tube and the fifth switching tube are N-type tubes.
Optionally, the pull-down assembly includes a sixth switching tube and a seventh switching tube, a source electrode of the sixth switching tube is connected to the second node, a drain electrode of the sixth switching tube is connected to the source electrode of the seventh switching tube, a gate electrode of the sixth switching tube is connected to a power supply, a drain electrode of the seventh switching tube is grounded, and a gate electrode of the seventh switching tube is used for receiving a second control signal;
When the sampling phase is in, the sixth switching tube is conducted, the seventh switching tube is turned off, and the potential of the second node is booted to a set potential.
Optionally, the gate voltage bootstrapping sub-switch module includes a second bootstrap capacitor, an eighth switch tube and a ninth switch tube, one end of the second bootstrap capacitor is connected to the third node, the other end of the second bootstrap capacitor is connected to the eighth switch tube and a source electrode of the ninth switch tube, a drain electrode of the eighth switch tube is connected to a power supply, a gate electrode of the eighth switch tube is connected to the second node, a drain electrode of the ninth switch tube is connected to the second node, and a gate electrode of the ninth switch tube is connected to a gate electrode of the third switch tube;
When the sampling phase is in, the eighth switching tube is turned off, and when the sampling phase is in, the ninth switching tube is turned on.
Optionally, the eighth switching tube and the ninth switching tube are P-type tubes.
Optionally, the gate voltage bootstrapping sub-switch module further includes a tenth switch tube, a drain electrode of the tenth switch tube is connected to the second node, a source electrode of the tenth switch tube is connected to the first node, a gate electrode of the tenth switch tube is connected to the power supply, and the tenth switch tube is in a conducting state in a holding stage and a sampling stage.
Optionally, the sample hold circuit further includes an eleventh switch tube, and a source-drain electrode of the eleventh switch tube is connected to a drain electrode of the sampling switch tube after being shorted.
Optionally, the bootstrap capacitor inside the gate voltage bootstrap main switch module and the bootstrap capacitor inside the gate voltage bootstrap sub-switch module have the same capacitance value.
On the other hand, the embodiment of the application also provides an electronic chip, which comprises the sample hold circuit.
Compared with the prior art, the application has the following beneficial effects:
The application provides a sampling hold circuit and an electronic chip, wherein the sampling hold circuit comprises a grid voltage bootstrapping main switch module, a grid voltage bootstrapping sub-switch module, a sampling switch tube, a signal tracking switch tube and a pull-up switch tube, the grid voltage bootstrapping main switch module is respectively connected with the grid voltage bootstrapping sub-switch module, the signal tracking switch tube and the pull-up switch tube, the grid voltage bootstrapping main switch module is connected with a grid electrode of the sampling switch tube through a first node, a drain electrode of the pull-up switch tube is connected with a power supply, a source electrode is connected with the grid electrode of the signal tracking switch tube and the grid voltage bootstrapping main switch module through a second node, a charging loop inside the grid voltage bootstrapping main switch module and the grid voltage bootstrapping sub-switch module is conducted, and bootstrap capacitors inside the grid voltage bootstrapping sub-switch module are charged, the sampling switch tube, the signal tracking switch tube and the pull-up switch tube are all turned off, when the sampling stage is in, the pull-up switch tube is conducted, the sampling switch tube is driven to be conducted with the signal tracking switch tube, and then the grid voltage bootstrapping main switch module and the grid voltage bootstrapping sub-switch module is conducted to the bootstrap potential of the sampling loop.
On one hand, the sampling hold circuit provided by the application is additionally provided with the grid voltage bootstrapping sub-switch module, so that more switch tubes are connected with the second node, and fewer switch tubes are connected on the first node, namely, fewer parasitic capacitances are connected on the first node, thereby improving the bootstrap potential establishment speed of the sampling switch tubes and improving the linearity of the sampling hold circuit. On the other hand, because the pull-up switching tube is additionally arranged in the sampling and holding circuit, and in the sampling stage, the conduction of the pull-up switching tube can directly drive the sampling switching tube to be conducted with the signal tracking switching tube, so that the bootstrap potential can be built after the pilot conduction of the sampling switching tube, and the conduction speed of the sampling switching tube can be faster. Meanwhile, the signal tracking switching tube is not required to be conducted after the bootstrap potential is established, so that the conduction speed of the signal tracking switching tube is improved.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic circuit diagram of an ideal gate voltage bootstrapped switch circuit.
Fig. 2 is a circuit schematic diagram of a gate voltage bootstrapped switch circuit actually used in the prior art.
Fig. 3 is a schematic circuit diagram of a sample-and-hold circuit according to an embodiment of the present application.
In the figure:
110-grid voltage bootstrap sub-switch module, ms-sampling switch tube, mg-signal tracking switch tube, mx-pull-up switch tube, C1-first bootstrap capacitor, C2-second bootstrap capacitor, Q1-first switch tube, Q2-second switch tube, Q3-third switch tube, Q4-fourth switch tube, Q5-fifth switch tube, Q6-sixth switch tube, Q7-seventh switch tube, Q8-eighth switch tube, Q9-ninth switch tube, Q10-tenth switch tube, Q11-eleventh switch tube, VG-first node, VP-second node and VS-third node.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
As described in the background art, the sample-hold circuit in the prior art is generally implemented by using a gate voltage bootstrap switch circuit, and an ideal gate voltage bootstrap switch circuit is shown in fig. 1, and the circuit mainly includes a sampling switch tube Ms, a bootstrap capacitor Cb, a sampling capacitor Cs, and switch tubes M1-M5, where the sampling capacitor Cs is used for storing a sampling signal.
The grid voltage bootstrapping switch circuit comprises two stages in operation, namely a holding stage and a sampling stage.
When in the hold phase, the switching tubes M3, M4 are turned off, the switching tubes M1, M2 and M5 are turned on, the power supply charges the bootstrap capacitor Cb, and the voltage rises to VDD with the charge stored in the bootstrap capacitor Cb having a size of vdd×c1 (C1 is the capacitance of the bootstrap capacitor Cb). It can be understood that the voltage of the bootstrap capacitor Cb increases to VDD in this stage, which means that the voltage difference between the upper plate and the lower plate of the bootstrap capacitor Cb is VDD, that is, the potential of the upper plate is VDD, and the potential of the lower plate is ground (0V). And the switching transistor M5 is turned on to set the gate potential of the sampling switching transistor Ms to the ground potential. At this time, the sampling switch Ms is turned off, and the output Vo keeps the sampled voltage unchanged.
When in the sampling stage, the switching tubes M1, M2 and M5 are turned off, the switching tubes M3 and M4 are turned on, and the input signal VIN is conducted to the lower electrode plate of the bootstrap capacitor Cb, and at this time, the voltage difference between the upper electrode plate and the lower electrode plate of the bootstrap capacitor Cb is kept unchanged due to conservation of charge. Since the potential of the bottom plate of the bootstrap capacitor Cb becomes VIN at this time, the potential of the top plate of the bootstrap capacitor Cb is bootstrapped to vdd+vin. The switch tube M3 is turned on to transfer the potential to the gate of the sampling switch tube Ms, and the source potential of the sampling switch tube Ms is VIN, so that the gate-source voltage V GS of the sampling switch tube Ms is V G-VS = (vdd+vin) -vin=vdd, that is, the gate-source voltage of the sampling switch tube Ms is constant to VDD. Therefore, the on-resistance of the sampling switch is not changed along with the change of an input signal, and the sampling linearity of the sampling system is improved.
Fig. 2 shows a gate voltage bootstrapped switch circuit actually used in the prior art based on fig. 1. In the figure, CLKH and CLKS are a pair of opposite control signals, and switching tubes M2, M5, M6 are P-type switching tubes, and the other switching tubes are N-type switching tubes, and in combination with the working principle of fig. 1, the working principle of the circuit in fig. 2 is as follows:
When in the hold phase, CLKH is a high level signal and CLKS is a low level signal, and at this time, the switching transistors M2, M3, and M8 are turned on. The switching tube M7 is a protection tube and is in a constantly conductive state, and at this time, since the switching tube M8 is conductive, the VG node is pulled down to the ground, and thus the switching tubes M9, M4 and Ms connected to the VG node are all turned off, and M6 is turned on. And since the switching tube M2 is turned on, the switching tube M5 is turned off. Therefore, in the whole circuit, the bootstrap capacitor Cb is charged through a loop of VDD, the switching tube M6, the bootstrap capacitor Cb, the switching tube M3 and ground.
When in the sampling stage, CLKH is a low level signal, CLKS is a high level signal, at this time, the switching tube M1 is turned on, the switching tubes M2, M3 and M8 are turned off, and since the switching tube M1 is turned on, the gate-source voltage of the switching tube M5 is actually the opposite value of the voltage of the bootstrap capacitor Cb, that is, -VDD, at this time, the switching tube M5 is turned on, the potential of the VG node is gradually pulled up to VDD, the switching tube M6 is turned off, the switching tubes M4 and M5 are gradually turned on, and the input signal VIN is conducted to the lower plate of the bootstrap capacitor Cb, so that the gate-source voltage of the sampling switching tube Ms is constant to VDD.
In practical applications, it is found that although the gate voltage bootstrap switch circuit shown in fig. 2 can well improve the linearity of the sampling switch, the gate voltage bootstrap switch circuit introduces a feedback loop (i.e. a loop that needs to turn on the switch tube M5 to raise the voltage of the VG node), so that the speed of the gate voltage bootstrap switch is limited. In addition, as the signal speed and the sampling speed are increased, in ultra-high speed signal acquisition systems, the size of the sampling capacitor is limited by speed and power consumption, and in many applications, the sampling capacitor is only f F stages. The nonlinear parasitic capacitance of the sampling switch at f F stages of the sampling node therefore becomes non-negligible for the signal introduced nonlinearity.
In addition, before the switch tube Ms of the traditional gate voltage bootstrapping switch is turned on, parasitic capacitance of the M4 and the Ms grid needs to be charged, so that the M4 is turned on first, after an input signal is transmitted to the Cb lower polar plate, the grid potential of the Ms can change along with the change of the input voltage, so that the turn-on time of the grid source voltage of the Ms is too long, the higher frequency sampling of the switch is limited, meanwhile, the larger the parasitic capacitance of the M4, M6, M9 and the Ms grid is, the slower the voltage rising speed of the VG node is, and the lower the grid source voltage of the Ms bootstrapping is due to the capacitance division.
In view of the above, the present application provides a gate voltage bootstrap switch circuit, which achieves the effect of improving the conduction speed and linearity of the sample hold circuit by setting the gate voltage bootstrap sub-switch module and the pull-up switch tube.
The sample-and-hold circuit provided in the application is exemplified below:
As an alternative implementation manner, referring to fig. 3, the sample-and-hold circuit includes a gate voltage bootstrap main switch module (not shown), a gate voltage bootstrap sub-switch module 110, a sampling switch tube Ms, a signal tracking switch tube Mg and a pull-up switch tube Mx, wherein the gate voltage bootstrap main switch module is respectively connected with the gate voltage bootstrap sub-switch module 110, the signal tracking switch tube Mg and the pull-up switch tube Mx, the gate voltage bootstrap main switch module is connected with a gate of the sampling switch tube Ms through a first node VG, a drain of the pull-up switch tube Mx is connected with a power supply, a source is connected with a gate of the signal tracking switch tube Mg through a second node VP, and the gate voltage bootstrap main switch module, when in a hold phase, a charging circuit inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module 110 is conducted, and a capacitor inside the gate voltage bootstrap main switch module and the gate voltage bootstrap sub-switch module 110 is charged, and the sampling switch tube Mg and the pull-up switch tube Mx are both turned off, when in the sample phase, the pull-up switch tube x is conducted, and the signal bootstrap switch tube Ms is driven to the gate voltage bootstrap main switch module and the voltage bootstrap switch module is conducted to the sample voltage bootstrap main switch module 110.
On the one hand, since the sampling hold circuit provided by the application is additionally provided with the grid voltage bootstrapping sub-switch module 110, more switch tubes are connected with the second node VP, and fewer switch tubes are connected on the first node VG, namely, fewer parasitic capacitances are connected on the first node VG, so that the bootstrap potential establishment speed of the sampling switch tube Ms is improved, and the linearity of the sampling hold circuit is also improved. On the other hand, because the pull-up switch tube Mx is additionally arranged in the sample hold circuit, and in the sampling stage, the pull-up switch tube Mx can be conducted to directly drive the sample switch tube Ms to be conducted with the signal tracking switch tube Mg, so that the bootstrap potential can be built after the sample switch tube is conducted, and the conduction speed of the sample switch tube Ms can be faster. Meanwhile, the signal tracking switch tube Mg is not required to be conducted after the bootstrap potential is established, so that the conduction speed of the signal tracking switch tube Mg is improved.
As an alternative implementation manner, the gate voltage bootstrap main switch module comprises a first bootstrap capacitor C1, a first switch tube Q1, a second switch tube Q2, a third switch tube Q3, a fourth switch tube Q4, a fifth switch tube Q5 and a pull-down component, one end of the first bootstrap capacitor C1 is connected with the drain electrode of the first switch tube Q1 and the drain electrode of a signal tracking switch tube Mg through a third node VS, the source electrode of the first switch tube Q1 is grounded, the source electrode of the signal tracking switch tube Mg and the source electrode of a sampling switch tube Ms are all used for receiving input signals, the other end of the first bootstrap capacitor C1 is connected with the source electrode of the second switch tube Q2 and the source electrode of the third switch tube Q3 respectively, the drain electrode of the second switch tube Q2 is connected to a power supply, the gate electrode of the third switch tube Q3 is connected to a second node VP, the drain electrode of the third switch tube Ms is connected to the gate electrode of the sampling switch tube Ms and the gate voltage bootstrap sub-switch module 110, the source electrode of the fourth switch tube Q4 is connected to the power supply, the drain electrode of the fourth switch tube Q4 is connected to the third switch tube Q3, the drain electrode of the fourth switch tube Q3 is connected to the fourth switch tube Q5, the fourth switch tube Q5 is connected to the other end of the fourth switch tube Q5, the signal is connected to the fourth switch tube Q5, and the fourth switch tube Q is connected to the control node is connected to the fourth control node, and the fourth switch tube Q is connected to the fourth opposite to the fourth switch Q; when in the holding stage, the first switching tube Q1, the pull-down component, the second switching tube Q2 and the fourth switching tube Q4 are conducted, the third switching tube Q3 and the fifth switching tube Q5 are disconnected, the first switching tube Q1, the first bootstrap capacitor C1 and the second switching tube Q2 form a charging loop, when in the sampling stage, the first switching tube Q1, the pull-down assembly, the second switching tube Q2 and the fourth switching tube Q4 are turned off, and the third switching tube Q3 and the fifth switching tube Q5 are turned on.
The second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 are P-type tubes, and the first switching tube Q1 and the fifth switching tube Q5 are N-type tubes.
The pull-down assembly comprises a sixth switching tube Q6 and a seventh switching tube Q7, wherein a source electrode of the sixth switching tube Q6 is connected to the second node VP, a drain electrode of the sixth switching tube Q6 is connected with a source electrode of the seventh switching tube Q7, a grid electrode of the sixth switching tube Q6 is connected to a power supply, a drain electrode of the seventh switching tube Q7 is grounded, a grid electrode of the seventh switching tube Q7 is used for receiving a second control signal, when the pull-down assembly is in a holding stage, the sixth switching tube Q6 and the seventh switching tube Q7 are both conducted and pull the second node VP to the ground after being conducted, when the pull-down assembly is in a sampling stage, the sixth switching tube Q6 is conducted, and the seventh switching tube Q7 is turned off.
As can be appreciated, in the sample-hold circuit provided by the present application, since only the gate of the sampling switch tube Ms is connected to the first node VG, compared with the existing topology, the parasitic capacitance of the first node VG is greatly reduced. According to the capacitance charging formula t=rc, T represents charging time, R represents equivalent resistance, C represents equivalent capacitance, and when the equivalent capacitance of the first node VG decreases, the time for charging the capacitance is shortened in the bootstrap process, so that the charging speed of the first bootstrap capacitor C1 to the first node VG is increased and the voltage drop caused by capacitive voltage division is reduced.
In addition, because the pull-up switching tube Mx provided by the application can directly act on the first node VG, the pull-up switching tube Mx directly pulls up the voltage of the first node VG to the power supply VDD after being conducted in the sampling stage, so that the sampling switching tube Ms is conducted in advance, and then the bootstrap process is established, thereby improving the initial stage establishment speed of the gate voltage of the sampling switching tube Ms. That is, the sampling switch tube Ms is turned on first, the signal starts to be established first, then the first node VG node enters the bootstrap state to ensure the linearity of signal establishment, and the turn-on speed of the sampling hold circuit is improved as a whole.
In addition, since the gate of the second switching tube Q2 is directly connected to the second node VP, the second switching tube Q2 does not need to wait for the establishment of the first node VG to turn off again, which increases the speed of the first node VG tracking the input signal, and then ensures that the gate voltage bootstrapping sub-switch module 110 has no risk of backflow through the bootstrap voltage of the gate voltage bootstrapping sub-switch module 110.
As an implementation manner, the gate voltage bootstrapping sub-switch module 110 includes a second bootstrap capacitor C2, an eighth switch tube Q8 and a ninth switch tube Q9, one end of the second bootstrap capacitor C2 is connected to the third node VS, the other end is connected to the eighth switch tube Q8 and the source of the ninth switch tube Q9, the drain of the eighth switch tube Q8 is connected to the power supply, the gate of the eighth switch tube Q8 is connected to the second node VP, the drain of the ninth switch tube Q9 is connected to the second node VP, the gate of the ninth switch tube Q9 is connected to the gate of the third switch tube Q3, the eighth switch tube Q8 is turned on when in the holding phase, the ninth switch tube Q9 is turned off, and the eighth switch tube Q8 is turned on when in the sampling phase. The eighth switching tube Q8 and the ninth switching tube Q9 are P-type tubes. In the present application, the capacitance of the first bootstrap capacitor C1 is the same as that of the second bootstrap capacitor C2.
The gate voltage bootstrapping sub-switch module 110 further includes a tenth switch tube Q10, a drain electrode of the tenth switch tube Q10 is connected to the second node VP, a source electrode of the tenth switch tube Q10 is connected to the first node VG, a gate electrode of the tenth switch tube Q10 is connected to the power source, and the tenth switch tube Q10 is in a conducting state in both the holding phase and the sampling phase.
By setting the gate voltage bootstrapping sub-switch module 110, the second node VP can be introduced, so that more switch tubes can be connected to the second node VP, the number of switch tubes connected to the first node VG is reduced, and the gate voltage bootstrapping speed of the first node VG is further improved.
Meanwhile, in the bootstrap process, the potential of the second node VP is also bootstrapped to vdd+vin, and the gate of the signal tracking switch tube Mg is connected to the second node VP, so that the signal tracking switch tube Mg does not need to wait for the second node VP to be turned on after the voltage is established, but is directly turned on after the pull-up switch tube Mx is turned on, thereby improving the speed of the gate voltage tracking input signal of the sampling switch tube Ms, and then the potential of the second node VP is bootstrapped to vdd+vin in the second bootstrap capacitor C2, and guaranteeing the linearity of the signal tracking switch tube Mg.
In addition, after the second node VP is bootstrapped to vdd+vin, since the gates of the second switching tube Q2 and the eighth switching tube Q8 are connected to the second node VP, it is ensured that the second switching tube Q2 and the eighth switching tube Q8 are not turned on even after the second node VP is bootstrapped, and the risk of backflow from the sources of the second switching tube Q2 and the eighth switching tube Q8 to the power supply is avoided.
In addition, in order to further improve the linearity of the sampling switch tube Ms, the sample hold circuit provided by the application further includes an eleventh switch tube Q11, where the source and drain of the eleventh switch tube Q11 are connected to the drain of the sampling switch tube Ms after being shorted. By providing the eleventh switching transistor Q11, a parasitic capacitance opposite to the change of the sampling switching transistor Ms can be introduced at the signal sampling node, thereby realizing compensation of the nonlinear parasitic capacitance of the sampling switching transistor Ms.
The working principle of the circuit provided by the application is specifically described below in combination with the circuit:
When in the hold phase, the first control signal CLKS is low and the second control signal CLKH is high. At this time, the first switching tube Q1, the fourth switching tube Q4, and the seventh switching tube Q7 are turned on, the fifth switching tube Q5, and the pull-up switching tube Mx are turned off, and the sixth switching tube Q6 is used as a protection tube and is always in a turned-on state, so that after the seventh switching tube Q7 is turned on, the voltage of the second node VP is directly pulled down to the ground. The tenth switching tube Q10 is used as a protection tube, and is always turned on, and then after the voltage of the second node VP is pulled down to the ground, the second switching tube Q2 and the eighth switching tube Q8 are turned on, and the sampling switching tube Ms and the signal tracking switching tube Mg are turned off. Meanwhile, after the fourth switching tube Q4 is turned on, the gates of the third switching tube Q3 and the ninth switching tube Q9 are pulled up to the power supply VDD, and the third switching tube Q3 and the ninth switching tube Q9 are turned off. It can be seen that in this stage, the first bootstrap capacitor C1 is charged through the second switching tube Q2, the first bootstrap capacitor C1, and the charging loop of the first switching tube Q1, and the second bootstrap capacitor C2 is charged through the eighth switching tube Q8, the second bootstrap capacitor C2, and the charging loop of the first switching tube Q1.
When the sampling stage is in, the first control signal CLKS is at a high level, the second control signal CLKH is at a low level, and at this time, the first switching tube Q1, the fourth switching tube Q4, the seventh switching tube Q7 are turned off, and the fifth switching tube Q5, the pull-up switching tube Mx are turned on. It should be noted that, in this stage, the second node VP is actually included in the second node VP voltage establishment stage and the bootstrap stage, and the pull-up transistor Mx is turned on, so that the second node VP is directly pulled up to VDD, and the establishment process is faster because there is no feedback loop. When the second node VP is pulled up to VDD, the sampling switch Ms and the signal tracking switch Mg are turned on, and the second switch Q2 and the eighth switch Q8 are turned off. Because the process has higher establishing speed, the sampling switch tube Ms in the circuit can work at a higher speed, and the sampling frequency of the sampling switch tube Ms is greatly improved. After the sampling switch tube Ms is conducted with the signal tracking switch tube Mg, a bootstrapping stage is entered. In the prior art, the signal tracking switch tube Mg needs to be turned on after the voltage of the first node VG is established, but in the present application, the signal tracking switch tube Mg is turned on in the two-node voltage establishment stage, so that the establishment speed of the bootstrap stage is improved.
In the bootstrap phase process, under the action of the conduction of the fifth switching tube Q5, the third switching tube Q3 and the ninth switching tube Q9 are conducted, so that the first bootstrap capacitor C1 bootstraps the voltage of the first node VG to vdd+vin, and the second bootstrap capacitor C2 bootstraps the voltage of the second node VP to vdd+vin, thereby ensuring the linearity of the sampling switching tube Ms and the signal tracking switching tube Mg.
Therefore, the novel topological structure is adopted in the sample hold circuit. On the premise of not introducing larger device expenditure, the parasitic capacitance of the first node VG is greatly reduced, the voltage establishment speed of the first node VG is greatly accelerated, the turn-on speed of the signal tracking switch tube Mg and the turn-off speeds of the second switch tube Q2 and the eighth switch tube Q8 are accelerated, the speed of the gate voltage tracking input signal of the sampling switch tube Ms is improved, and the preliminary rising speed of the voltage establishment of the first node VG is accelerated through the pull-up switch tube Mx. The on-off speed of the sampling switch tube Ms is greatly improved. The non-linear capacitance parasitic to the sampling switch tube Ms is compensated for by introducing an eleventh switch tube Q11 opposite to the parasitic capacitance change.
Based on the implementation manner, the embodiment of the application also provides an electronic chip, which comprises the sample hold circuit.
In summary, the application provides a sample hold circuit and an electronic chip, the sample hold circuit comprises a grid voltage bootstrapping main switch module, a grid voltage bootstrapping sub-switch module, a sampling switch tube, a signal tracking switch tube and a pull-up switch tube, wherein the grid voltage bootstrapping main switch module is respectively connected with the grid voltage bootstrapping sub-switch module, the signal tracking switch tube and the pull-up switch tube, the grid voltage bootstrapping main switch module is connected with a grid electrode of the sampling switch tube through a first node, a drain electrode of the pull-up switch tube is connected with a power supply, a source electrode is connected with a grid electrode of the signal tracking switch tube and the grid voltage bootstrapping main switch module through a second node, a charging loop inside the grid voltage bootstrapping main switch module and the grid voltage bootstrapping sub-switch module is conducted, and a bootstrap capacitor inside the grid voltage bootstrapping sub-switch module is charged for the grid voltage bootstrapping main switch module and the grid voltage bootstrapping sub-switch module, the sampling switch tube, the signal tracking switch tube and the pull-up switch tube are all turned off, when the sample stage is in the sampling stage, the pull-up switch tube is conducted, the sampling switch tube and the signal tracking switch tube is driven to be conducted, and then the grid voltage bootstrapping main switch module and the bootstrap switch module is conducted to the potential of the sampling loop.
On one hand, the sampling hold circuit provided by the application is additionally provided with the grid voltage bootstrapping sub-switch module, so that more switches are connected with the second node, and fewer switch tubes are connected on the first node, namely, fewer parasitic capacitances are connected on the first node, thereby improving the bootstrap potential establishment speed of the sampling switch tubes and improving the linearity of the sampling hold circuit. On the other hand, because the pull-up switching tube is additionally arranged in the sampling and holding circuit, and in the sampling stage, the conduction of the pull-up switching tube can directly drive the sampling switching tube to be conducted with the signal tracking switching tube, so that the bootstrap potential can be built after the pilot conduction of the sampling switching tube, and the conduction speed of the sampling switching tube can be faster. Meanwhile, the signal tracking switching tube is not required to be conducted after the bootstrap potential is established, so that the conduction speed of the signal tracking switching tube is improved.
The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101986570A (en) * | 2010-11-02 | 2011-03-16 | 西安电子科技大学 | Analog-to-digital converter (ADC) and sample-and-hold circuit thereof |
| CN112953503A (en) * | 2021-02-01 | 2021-06-11 | 电子科技大学 | High-linearity grid voltage bootstrap switch circuit |
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| JP4043409B2 (en) * | 2003-06-17 | 2008-02-06 | 三菱電機株式会社 | Level conversion circuit |
| US10897263B1 (en) * | 2020-05-14 | 2021-01-19 | Telefonaktiebolaget Lm Ericsson (Publ) | Multiple paths bootstrap configuration for sample and hold circuit |
| CN115987267A (en) * | 2023-02-15 | 2023-04-18 | 江苏科技大学 | A High Linearity Sampling Switch Circuit |
| CN117240275A (en) * | 2023-09-15 | 2023-12-15 | 西安电子科技大学重庆集成电路创新研究院 | Grid voltage bootstrap switch using nonlinear capacitance compensation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101986570A (en) * | 2010-11-02 | 2011-03-16 | 西安电子科技大学 | Analog-to-digital converter (ADC) and sample-and-hold circuit thereof |
| CN112953503A (en) * | 2021-02-01 | 2021-06-11 | 电子科技大学 | High-linearity grid voltage bootstrap switch circuit |
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