CN120035224A

CN120035224A - Semiconductor structure and method for forming the same

Info

Publication number: CN120035224A
Application number: CN202311524611.1A
Authority: CN
Inventors: 余栋林
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2023-11-15
Filing date: 2023-11-15
Publication date: 2025-05-23

Abstract

The structure comprises a substrate, a grid structure, a source region and a drain region, wherein the substrate comprises an insulating layer and a substrate layer arranged on the insulating layer, the substrate layer comprises an active region, the grid structure is arranged on part of the active region and comprises a plurality of main grids arranged on a first region and a first auxiliary grid arranged on a second region, the plurality of main grids are connected with the first auxiliary grid, the plurality of main grids are parallel to a first direction and are distributed along a second direction, the first auxiliary grids are parallel to the second direction, the first direction and the second direction are mutually perpendicular, the source region and the drain region are respectively arranged in the first region on two sides of each main grid, each drain region is arranged between adjacent source regions, the source region and the drain region are of a first conductivity type, the first body region and the main grid are respectively arranged on two sides of the first auxiliary grid, the first body region is of a second conductivity type, the first conductivity type and the second conductivity type are different, and the robustness of the ESD structure is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.

Background

The electrostatic discharge (Electrostatic Discharge, abbreviated ESD) effect is one of the most likely factors to cause chip damage during chip fabrication and use. GGNMOS (gate grounded NMOS) devices, which are widely used as ESD protection devices due to their high robustness, low leakage current, etc., are mainly applied to bulk silicon (bulk silicon) platforms.

With the development of a silicon-on-insulator (silicon on insulator, abbreviated as SOI) process, the development and application of GGNMOS based on SOI processes are still to be further expanded. Currently, the GGNMOS based on SOI platform is mainly concentrated on low-voltage devices, and the disadvantages of low unit area robustness, high leakage and the like limit the application range of the GGNMOS, and meanwhile, the cost of the GGNMOS device is increased.

Therefore, the existing GGNMOS device based on SOI platform needs to be further improved.

Disclosure of Invention

The invention provides a semiconductor structure and a forming method thereof, which are used for improving the performance of an electrostatic discharge protection structure.

In order to solve the technical problems, the technical scheme of the invention provides a semiconductor structure, which comprises a substrate, a grid structure, a first auxiliary grid structure and a second auxiliary grid structure, wherein the substrate comprises an insulating layer and a substrate layer positioned on the insulating layer, the substrate layer comprises an active region, the active region comprises a first region and a second region which are arranged along a first direction, the first region and the second region are adjacent, the grid structure positioned on part of the active region comprises a plurality of main grids positioned on the first region and a first auxiliary grid positioned on the second region, the plurality of main grids are connected with the first auxiliary grid, the plurality of main grids are parallel to the first direction and are arranged along the second direction, the first auxiliary grids are parallel to the second direction, the first direction and the second direction are perpendicular to each other, the source region and the drain region which are respectively positioned in the first region and the second region are positioned between the adjacent source regions, the source region and the drain region are respectively positioned in the first region and the second region are not in the first body region and the second body region are respectively positioned in the first body region and the second body region are respectively in the first body region and the second body region are in the first body region and the second body region are respectively in the first body region.

Optionally, the semiconductor device further comprises a conductive structure located on the substrate, wherein the conductive structure comprises a first conductive layer and a second conductive layer which are electrically isolated from each other, the first conductive layer is used for electrically connecting the source regions, the first body regions and the gate structure, and the second conductive layer is electrically connected with the drain regions.

The semiconductor device comprises a substrate, a plurality of main grid electrodes, a blocking layer, a first conductive layer, a second conductive layer, a contact layer, a first conductive layer and a second conductive layer, wherein the blocking layer is arranged on the substrate and covers the surfaces of the plurality of main grid electrodes, the blocking layer also extends to part of the surfaces of the source region, part of the surfaces of the drain region and part of the surfaces of the first auxiliary grid electrodes, which are adjacent to the plurality of main grid electrodes, the contact layer is arranged on the surfaces of the source region, the drain region and the first body region, which are exposed by the blocking layer, the first conductive layer is electrically connected with the plurality of source regions, the first body region and the grid electrode structure through the contact layer, and the second conductive layer is electrically connected with the plurality of drain regions through the contact layer.

Optionally, the conductive structure further comprises a first conductive plug structure and a second conductive plug structure, wherein the first conductive plug structure comprises a plurality of first sub plugs for electrically connecting the first conductive layer with each source region, a plurality of second sub plugs for electrically connecting the first conductive layer with the first body region and a plurality of third sub plugs for electrically connecting the first conductive layer with the gate structure, the second conductive plug structure comprises a plurality of fourth sub plugs for electrically connecting the second conductive layer with each drain region, the plurality of first sub plugs are located on the surface of the contact layer on the source region and are arranged along the first direction, the plurality of second sub plugs are located on the surface of the contact layer on the first body region and are arranged along the second direction, the plurality of third sub plugs are located on the surface of the first auxiliary gate and are arranged along the second direction, and the plurality of fourth sub plugs are located on the surface of the contact layer on the drain region and are arranged along the first direction.

Optionally, the distance between the first sub-plug and the contact layer on the source region is a first size ranging from 0.1 micron to 1 micron, the contact layer on the source region is a second size ranging from less than or equal to 2 microns in the second direction, the contact layer on the drain region is a third size ranging from 0.2 micron to 4 microns in the second direction, the distance between the contact layer on the drain region and the fourth sub-plug is a fourth size ranging from 0.1 micron to 1 micron, each of the main gates is a fifth size ranging from 0.1 micron to 1 micron in the second direction, each of the main gates on the first region is a sixth size ranging from 5 microns to 40 microns in the first direction, the first auxiliary gate is a seventh size ranging from 0.2 micron to 4 microns, the distance between the contact layer on the drain region and the fourth sub-plug is a fourth size ranging from 0.1 micron to 1 micron, each of the main gates is a fifth size ranging from 0.1 micron to 1 micron in the second direction, each of the main gates on the first region is a sixth size ranging from 5 microns to 40 microns in the first direction, the first auxiliary gate is a seventh size ranging from 0.2 microns to 2 microns in the seventh size ranging from the eighth size to 2 microns.

Optionally, the active region further comprises a third region adjacent to the first region, the third region and the second region are respectively located at two sides of the first region, the grid structure further comprises second auxiliary grids located on the third region, the plurality of main grids are connected with the second auxiliary grids, the second auxiliary grids are parallel to the second direction, the structure further comprises a second body region located in the third region, the second body region and the main grids are respectively located at two sides of the second auxiliary grids, the second body region is of a second conductive type, and the first conductive layer is further electrically connected with the second body region.

The semiconductor device comprises a first region, a second region, a source region, a drain region, a first body region, a second region, a well region, a insulating layer, a drain region, a first body region, a second body region, a source region, a drain region and a bottom of the first body region, wherein the well region is positioned in the first region and the second region, the bottom of the well region is in contact with the insulating layer, the source region, the drain region and the first body region are positioned in the well region, and the bottoms of the source region, the drain region and the first body region are in contact with the insulating layer.

Optionally, the substrate layer further comprises an isolation structure surrounding the active region, the plurality of main gates further extend to part of the isolation structure, and the first auxiliary gates further extend to part of the isolation structure.

Optionally, the material of the insulating layer comprises silicon oxide and the material of the substrate layer comprises a combination of one or more of silicon, silicon germanium and germanium.

Correspondingly, the technical scheme of the invention also provides a method for forming the semiconductor structure, which comprises the steps of providing a substrate, wherein the substrate comprises an insulating layer and a substrate layer positioned on the insulating layer, the substrate layer comprises an active region, the active region comprises a first region and a second region which are arranged along a first direction, the first region and the second region are adjacent, a grid structure is formed on part of the active region, the grid structure comprises a plurality of main grids positioned on the first region and a first auxiliary grid positioned on the second region, the plurality of main grids are connected with the first auxiliary grid, the plurality of main grids are parallel to the first direction and are arranged along the second direction, the first auxiliary grids are parallel to the second direction, the first direction and the second direction are perpendicular to each other, a source region and a drain region are respectively formed in the first region at two sides of each main grid, each drain region is positioned between the adjacent source regions, the source region and the drain region is provided with a first auxiliary grid which is positioned on the first main grid which is positioned on the first region, the plurality of main grids are connected with the first auxiliary grid which is parallel to the first direction, the plurality of main grids which is parallel to the second direction, the first main grid is provided with the first direction which is provided with the first body and the second body which is provided with the first body.

Optionally, after forming the source region, the drain region and the first body region, forming a conductive structure on the substrate, wherein the conductive structure comprises a first conductive layer and a second conductive layer which are electrically isolated from each other, the first conductive layer electrically connects a plurality of source regions, the first body region and the gate structure, and the second conductive layer is electrically connected with the plurality of drain regions.

Optionally, before the conductive structure is formed, a blocking layer is formed on the substrate and covers the surfaces of the plurality of main gates, the blocking layer also extends to the surfaces of the source regions and the drain regions adjacent to the plurality of main gates and the surfaces of the first auxiliary gates, contact layers are formed on the surfaces of the source regions, the drain regions and the first body regions exposed by the blocking layer, the first conductive layer is electrically connected with the plurality of source regions, the first body regions and the gate structure through the contact layers, and the second conductive layer is electrically connected with the plurality of drain regions through the contact layers.

Optionally, the forming process of the contact layer includes a metal silicide treatment process.

Optionally, the active region further comprises a third region adjacent to the first region, the third region and the second region are respectively located at two sides of the first region, the grid structure further comprises second auxiliary grids located on the third region, the plurality of main grids are connected with the second auxiliary grids, the second auxiliary grids are parallel to the second direction, a second body region is formed in the third region, the second body region and the main grids are respectively located at two sides of the second auxiliary grids, the second body region is of a second conductive type, and the first conductive layer is further electrically connected with the second body region.

Optionally, before the gate structure is formed, a well region is formed in the first region and the second region, the bottom of the well region is in contact with the insulating layer, the source region, the drain region and the first body region are all located in the well region, and the bottoms of the source region, the drain region and the first body region are all in contact with the insulating layer.

Optionally, the well region forming process comprises a first ion implantation process, wherein the process parameters of the first ion implantation process comprise that implanted ions comprise N-type or P-type conductive ions, the implantation energy ranges from 10KeV to 100KeV, and the implantation dosage ranges from 1E12atom/cm ² to 1E13atom/cm ².

Optionally, the substrate layer further comprises an isolation region surrounding the active region, and before the well region is formed, the substrate layer further comprises etching the isolation region, forming a groove in the substrate, wherein the groove exposes the insulating layer, and forming an isolation structure in the groove.

Optionally, the forming method of the groove further comprises the step of continuing to etch the insulating layer at the bottom of the groove after the insulating layer is exposed, wherein the groove has a first depth in the insulating layer and a second depth in the substrate layer, and the ratio of the first depth to the second depth ranges from 5% to 30%.

Optionally, the forming process of the source region and the drain region comprises a second ion implantation process, wherein the process parameters of the second ion implantation process comprise that doped ions comprise N-type or P-type conductive ions, the implantation energy ranges from 5KeV to 100KeV, and the implantation dosage ranges from 1E15atom/cm ² to 9E15atom/cm ².

Optionally, the first body region forming process comprises a third ion implantation process, wherein the process parameters of the third ion implantation process comprise that doped ions comprise N-type or P-type conductive ions, the implantation energy ranges from 5KeV to 100KeV, and the implantation dosage ranges from 1E15atom/cm ² to 9E15atom/cm ².

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

In the semiconductor structure provided by the technical scheme of the invention, the grid structure positioned on part of the active area comprises a plurality of main grids positioned on the first area and a first auxiliary grid positioned on the second area, the plurality of main grids are connected with the first auxiliary grid, the source area and the drain area which are respectively positioned in the first area at two sides of each main grid are respectively positioned in the first area and the first integral area which are positioned in the second area, the first integral area and the main grid are respectively positioned at two sides of the first auxiliary grid, the plurality of source areas, the first integral area and the grid structure are electrically connected to serve as cathode ends, the plurality of drain areas are electrically connected to serve as anode ends, and can play a positive ESD protection role, the first integral area is grounded, and when the ESD structure is started, the accumulated charges in the body can be timely discharged, the adverse effect of a floating body effect is weakened, so that the starting voltage of the ESD structure is favorably improved, the electric leakage of a device is reduced, the static power consumption is improved, the thermal effect is improved, the performance of the ESD structure is improved, and the signal is further stressed to the second integral area due to the fact that the first integral area has the positive ESD protection effect and the second integral area has the advantages of being in the two-way when the ESD structure is started.

Further, the device performance can be accurately adjusted by adjusting one or more parameters of the first dimension to the ninth dimension to meet different requirements.

Further, the gate structure further comprises a second auxiliary gate located on the third region, the plurality of main gates are connected with the second auxiliary gate, a second body region is formed in the third region, and the second body region is grounded to further overcome the influence of the floating body effect and increase the robustness of the ESD structure.

In the method for forming the semiconductor structure, a grid structure is formed on a part of the active region, the grid structure comprises a plurality of main grids located on the first region and a first auxiliary grid located on the second region, the plurality of main grids are connected with the first auxiliary grid, a source region and a drain region are respectively formed in the first region on two sides of each main grid, a first integral region is formed in the second region, the first integral region and the main grids are respectively located on two sides of the first auxiliary grid, the plurality of source regions, the first integral region and the grid structure are electrically connected to serve as cathode terminals, the plurality of drain regions are electrically connected to serve as anode terminals, a positive ESD protection effect can be achieved, the first integral region is grounded, charges accumulated in a body can be discharged in time when the ESD structure is started, adverse effects of floating body effects are weakened, accordingly, electric leakage of devices is reduced, static power consumption is improved, thermal performance is improved, and the first integral region and the second integral region has the advantages of being connected to the drain region in a two-way mode due to the fact that the first integral region has the signal leakage effect and the second integral region has the fact that the first integral region has the positive ESD protection effect and the second integral region has the positive ESD protection effect.

Further, the gate structure further comprises a second auxiliary gate electrode located on the third region, the plurality of main gate electrodes are connected with the second auxiliary gate electrode, a second body region is arranged in the third region, the second body region is grounded and used for further overcoming the influence of floating body effect and increasing the robustness of the ESD structure, and besides a parasitic diode structure between the first body region and the drain region, the parasitic diode structure is also arranged between the second body region and the drain region, so that the device has better negative protection characteristics.

Drawings

FIGS. 1 and 2 are schematic diagrams of an ESD protection structure;

Fig. 3 to 17 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present invention;

fig. 18 to 32 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to another embodiment of the present invention.

Detailed Description

Note that "surface", "upper", as used herein, describes a relative positional relationship in space, and is not limited to whether or not it is in direct contact.

As described in the background, the performance of the conventional esd protection structure needs to be improved. The analysis will now be described in connection with an existing electrostatic discharge protection structure.

Fig. 1 and 2 are schematic structural diagrams of an esd protection structure.

Referring to fig. 1 and 2, fig. 1 is a schematic top view structure, fig. 2 is a schematic cross-sectional structure along the direction CC1 in fig. 1, the esd protection structure includes a substrate, the substrate includes an oxide layer 100, an active region (not shown) located on the oxide layer 100, and an isolation structure layer 102, the isolation structure layer 102 is further located between adjacent active regions, a P-type well region 101 is located in the active region, the bottom of the well region 101 contacts the oxide layer 100, a gate 103 located on the substrate, an N-type source region 104 and a drain region 105 located in the well region 101 at two sides of the gate 103, respectively, the bottoms of the source region 104 and the drain region 105 are all in contact with the oxide layer 100, the source region 104 and the gate 103 are electrically connected with each other, and are led out as a cathode terminal (cathode), and the led out of the drain region 105 is referred to as an anode terminal (anode).

The GGNMOS structure is used in an SOI-based process, where the source region 103 and the gate 102 are grounded, and the drain region 104 is electrically connected to the input/output terminal of the protected circuit, so as to play a role in electrostatic discharge protection of the integrated circuit.

However, in the GGNMOS structure based on the SOI process, since there is no body (body) contact, the body current cannot be drawn out by forming a p+ doped region in the well region 101. Thus, there will be a floating body effect (Floating body effect). As shown at the dotted line in fig. 2, when the anode terminal (drain terminal) has a positive signal to be temporarily supplied, a certain amount of positive charge is accumulated in the channel due to the hot carrier effect, so that the body potential is raised. When the body potential rises to about 0.7V, parasitic PN junctions of the body end and the source end are opened, so that a channel parasitic BJT is further opened, and finally the GGNMOS is opened too early, and as a result, the GGNMOS opening voltage (trigger voltage) is too low, and the GGNMOS working window is reduced. In addition, due to the existence of the floating body effect, the GGNMOS electric leakage is higher, and the static power consumption is increased.

In order to solve the problems, in the semiconductor structure and the forming method thereof provided by the invention, the gate structure positioned on a part of the active region comprises a plurality of main gates positioned on the first region and a first auxiliary gate positioned on the second region, the plurality of main gates are connected with the first auxiliary gate, the source region and the drain region respectively positioned in the first region at two sides of each main gate are connected, the first body region and the main gate are respectively positioned at two sides of the first auxiliary gate, the plurality of source regions, the first body region and the gate structure are electrically connected to serve as cathode terminals, the plurality of drain regions are electrically connected to serve as anode terminals, a positive ESD protection effect can be achieved, the first body region is grounded, charges accumulated in a body can be timely discharged when the ESD structure is started, adverse effects of a floating body effect are weakened, accordingly starting voltage of the ESD structure is improved, electric leakage of a device is reduced, the static state energy is improved, the signal leakage performance is improved, and the first body region and the second body region has the characteristics of being temporarily connected to the drain region when the ESD structure is in a two-way signal is started due to the fact that the first body region and the second body region has the ESD structure has the positive-side effect.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 3 to 17 are schematic structural views illustrating steps in a method for forming a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 3 and 4, fig. 3 is a schematic top view structure, fig. 4 is a schematic cross-sectional structure along the MM1 direction in fig. 3, and a substrate is provided, wherein the substrate includes an insulating layer 200 and a substrate layer 201 disposed on the insulating layer 200, the substrate layer 201 includes an active region, the active region includes a first region I and a second region II arranged along a first direction X, and the first region I and the second region II are adjacent.

And forming a gate structure on part of the active region.

In this embodiment, before forming the gate structure, a well region 202 is further formed in the first region I and the second region II, and the bottom of the well region 202 is in contact with the insulating layer 200.

In this embodiment, the well region 202 is formed by a first ion implantation process.

The technological parameters of the first ion implantation process comprise that the implanted ions comprise N-type or P-type conductive ions, the implantation energy ranges from 10KeV to 100KeV, and the implantation dosage ranges from 1E12atom/cm ² to 1E13atom/cm ². In this embodiment, the implanted ions are P-type conductive ions.

In this embodiment, the well region 202 is formed by forming a first mask layer (not shown) on a portion of the substrate, where the first mask layer exposes the active region, and implanting first doped ions into the substrate with the first mask layer as a mask.

In this embodiment, the substrate layer 201 further includes an isolation region (not shown) surrounding the active region, and before forming the well region 202, etching the isolation region to form a recess (not shown) in the substrate, where the recess exposes the insulating layer 200, and forming an isolation structure 203 in the recess.

In the process of forming the grooves, over etching can be selected to a certain extent to ensure isolation between different devices and avoid latch-up. Specifically, the method for forming the groove further comprises the step of continuing to etch the insulating layer 200 at the bottom of the groove after the insulating layer 200 is exposed, wherein the groove has a first depth in the insulating layer 200 and a second depth in the substrate layer 201, and the ratio of the first depth to the second depth ranges from 5% to 30%. The ratio of the first depth to the second depth is used herein to measure the degree of over-etching. In this embodiment, the ratio of the first depth to the second depth is 20%.

In this embodiment, during the formation of the well region 202, the first mask layer also exposes a portion of the isolation structure 203 (see the area indicated by the dashed line a in fig. 3) adjacent to the active region, so as to avoid problems such as alignment accuracy of the ion implantation position, and so on, so as to improve the process window.

In this embodiment, the material of the insulating layer 200 includes silicon oxide.

The material of the substrate layer 201 includes a combination of one or more of silicon, silicon germanium, and germanium. In this embodiment, the material of the substrate layer 201 includes silicon.

Referring to fig. 5 to 7, fig. 5 is a schematic top view structure, fig. 6 is a schematic cross-sectional structure along the MM1 direction in fig. 5, fig. 7 is a schematic cross-sectional structure along the NN1 direction in fig. 5, a gate structure is formed on a portion of the active region, the gate structure includes a plurality of main gates 204 located on the first region I and a plurality of first auxiliary gates 205 located on the second region II, the plurality of main gates 204 are connected with the first auxiliary gates 205, the plurality of main gates 204 are parallel to the first direction X and are arranged along the second direction Y, the first auxiliary gates 205 are parallel to the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

In this embodiment, the plurality of main gates 204 further extend onto a portion of the isolation structure 203, and the first auxiliary gate 205 further extends onto a portion of the isolation structure 203. The main gates 204 and the first auxiliary gates 205 on the active region are effective devices, and the purpose of forming the main gates 204 and the first auxiliary gates 205 on the isolation structures 203 is to improve a process window, for example, to avoid poor dimensional control caused by alignment accuracy in the etching process.

It should be noted that the number of the plurality of main gates 204 may be 1 or more, and specifically, the number may be adjusted according to actual needs.

Referring to fig. 8 to 10, fig. 8 is a schematic top view, fig. 9 is a schematic cross-sectional view along the MM1 direction in fig. 8, fig. 10 is a schematic cross-sectional view along the NN1 direction in fig. 8, a source region 206 and a drain region 207 are respectively formed in the first region I at two sides of each main gate 204, each drain region 207 is located between adjacent source regions 206, the source regions 206 and the drain regions 207 have a first conductivity type, a first body region 208 is formed in the second region II, the first body region 208 and the main gate 204 are respectively located at two sides of the first auxiliary gate 205, and the first body region 208 has a second conductivity type, wherein the first conductivity type is different from the second conductivity type.

In this embodiment, the source region 206, the drain region 207, and the first body region 208 are all located within the well region 202.

In this embodiment, bottoms of the source region 206, the drain region 207, and the first body region 208 are all in contact with the insulating layer 200.

In this embodiment, the forming process of the source region 206 and the drain region 207 includes a second ion implantation process.

The process parameters of the second ion implantation process comprise that the doped ions comprise N-type or P-type conductive ions, the implantation energy ranges from 5KeV to 100KeV, and the implantation dosage ranges from 1E15atom/cm ² to 9E15atom/cm ². In this embodiment, the doped ions in the source region 206 and the drain region 207 are N-type conductive ions.

The source region 206 and the drain region 207 are formed by forming a second mask layer (not shown) on a portion of the substrate, the second mask layer exposing the first region I, and implanting second doping ions into the first region I using the second mask layer as a mask.

In this embodiment, the second mask layer also exposes a portion of the isolation structure 203 and a portion of the first auxiliary gate 205 (as a region indicated by a dashed line B in fig. 8) adjacent to the first region I, so as to improve a process window.

In this embodiment, the forming process of the first body region 208 includes a third ion implantation process.

The process parameters of the third ion implantation process comprise that the doped ions comprise N-type or P-type conductive ions, the implantation energy ranges from 5KeV to 100KeV, and the implantation dosage ranges from 1E15atom/cm ² to 9E15atom/cm ². In this embodiment, the doped ions in the first body region 208 are P-type conductive ions.

The method for forming the first body region 208 includes forming a third mask layer (not shown) on a portion of the substrate, where the third mask layer covers the first region and exposes the second region II on one side of the first auxiliary gate 205, and implanting second doping ions into the second region II by using the second mask layer as a mask.

In this embodiment, the third mask layer also exposes a portion of the isolation structure 203 (a region shown by a dashed line C in fig. 8) adjacent to the first auxiliary gate 205 and the second region II, so as to improve a process window and avoid an abnormal occurrence of implanting doped ions in the first body 208 into the source region 206 and the drain region 207.

In this embodiment, the source region 206 and the drain region 207 are formed first, and then the first body region 208 is formed. However, the order of the formation process of the source region 206 (the drain region 207) and the formation process of the first body region 208 may not be limited.

In this embodiment, after the source region 206, the drain region 207 and the first body region 208 are formed, a conductive structure is further formed on the substrate, where the conductive structure includes a first conductive layer and a second conductive layer that are electrically isolated from each other, the first conductive layer electrically connects a plurality of the source regions 206, the first body region 208 and the gate structure, and the second conductive layer is electrically connected with the plurality of drain regions 207. Specifically, before forming the conductive structure, please refer to fig. 11 to 13.

Referring to fig. 11 to 13, fig. 11 is a schematic top view, fig. 12 is a schematic cross-sectional view along the MM1 direction in fig. 11 (the barrier layer is omitted), fig. 13 is a schematic cross-sectional view along the NN1 direction in fig. 11 (the barrier layer is omitted), a barrier layer 209 is formed on the substrate, the barrier layer 209 covers the surfaces of the plurality of main gates 204, and a contact layer 210 is formed on the surfaces of the source region 206, the drain region 207, and the first body region 208 exposed by the barrier layer 209.

In this embodiment, the forming process of the contact layer 210 includes a metal silicide treatment process. The contact layer 210 is used to reduce contact resistance, and the material of the contact layer 210 includes a metal silicide material.

The blocking layer 209 is used to avoid forming metal silicide on the surfaces of the plurality of main gates 204.

In this embodiment, the blocking layer 209 further extends to a portion of the surface of the source region 206 and a portion of the surface of the drain region 207, which are adjacent to the plurality of main gates 204, and a portion of the surface of the first auxiliary gate 205, where a size range of the blocking layer 209 on the first auxiliary gate 205 is greater than or equal to 0.03 micrometers and less than or equal to a width of the first auxiliary gate 205. The width refers to a dimension along the first subsidiary gate 205 in the first direction X.

In this embodiment, the blocking layer 209 is in a shape of a "back" letter. In another embodiment, the barrier layer may be of the "II" type, i.e. parallel to the first direction and arranged along the second direction.

Specifically, in the second direction Y, the first auxiliary gate 205 includes a plurality of extraction regions (not shown) and a plurality of body regions (not shown), each of the extraction regions is adjacent to the source region 206, each of the body regions is located between two adjacent extraction regions, each of the body regions further includes an adjacent region (not shown) adjacent to the drain region 207, and the barrier layer 209 covers a surface of the adjacent region and extends to a portion of a surface of the drain region 207 and a portion of a surface of the source region 206 adjacent to the first auxiliary gate 205, and exposes each of the extraction regions. The extraction region is used for defining the position of a subsequent third sub-plug, and the first conductive layer is electrically connected with the grid structure through the third sub-plug.

More specifically, the contact layer 210 is further located on a surface of each of the lead-out regions, so as to reduce a contact resistance between the third sub-plug and the gate structure.

Referring to fig. 14 to 17, fig. 14 is a schematic top view structure, fig. 15 is a schematic top view structure with a conductive structure added thereto according to fig. 14, fig. 16 is a schematic cross-sectional structure along the MM1 direction in fig. 15, fig. 17 is a schematic cross-sectional structure along the NN1 direction in fig. 15, a conductive structure is formed on the substrate, the conductive structure includes a first conductive layer 211 and a second conductive layer 212 that are electrically isolated from each other, the first conductive layer 211 electrically connects a plurality of source regions 206, the first body regions 208 and the gate structure, and the second conductive layer 212 is electrically connected with the plurality of drain regions 207.

In this case, the source regions 206, the first body regions 208 and the gate structure are electrically connected as cathode terminals (cathode), the drain regions 207 are electrically connected as anode terminals (anode), so that a positive ESD protection effect can be achieved, the first body regions 208 are grounded, charges accumulated in the body can be timely discharged when the ESD structure is turned on, adverse effects of floating body effects are reduced, thus facilitating improvement of the turn-on voltage of the ESD structure, reducing device leakage, reducing static power consumption, improving discharge capacity, improving performances such as thermal effects, and in addition, parasitic diode structures exist between the first body regions 208 and the drain regions 207 due to the existence of the first auxiliary gate 205, and the structure can be temporarily turned on when a negative signal comes at the drain regions 207 due to the fact that the first body regions 208 are grounded, so that a discharge ESD current effect can be achieved, and thus the structure has bidirectional ESD protection characteristics.

Next, description will be made with TLP (transmission line pulse ) test data, including:

The ESD performance of the above structure under positive signal was tested by comparing the conventional ESD structures shown in fig. 1 and 2, the leakage of the above structure was reduced by about 4 orders of magnitude, vt1 (on voltage) was increased by more than 1V, it2 (second breakdown current) per unit area was increased by about 50%, and the performance of the device was significantly improved.

The structure was tested for ESD performance under negative signals with It2 (second breakdown current) per unit area reaching 1.9mA/um.

In summary, the above structure has excellent reverse performance while improving forward protection characteristics.

Here, for convenience of explanation, fig. 16 and 17 do not show the conductive structure, but only show the electrical connection relationship.

Specifically, the first conductive layer 211 is electrically connected to the source regions 206, the first body regions 208 and the gate structure through the contact layer 210, and the second conductive layer 212 is electrically connected to the drain regions 207 through the contact layer 210.

In this embodiment, the conductive structure further includes a first conductive plug structure including a plurality of first sub-plugs 213 electrically connecting the first conductive layer 211 with each of the source regions 206, a plurality of second sub-plugs 214 electrically connecting the first conductive layer 211 with the first body regions 208, and a third sub-plug 215 electrically connecting the first conductive layer 211 with the gate structure, and a second conductive plug structure including a plurality of fourth sub-plugs 216 electrically connecting the second conductive layer 212 with each of the drain regions 207.

Specifically, the first sub-plugs 213 are located on the surface of the contact layer 210 on the source region 206 and are arranged along the first direction X, the second sub-plugs 214 are located on the surface of the contact layer 210 on the first body region 208 and are arranged along the second direction Y, the third sub-plugs 215 are located on the surface of the first auxiliary gate 205 and are arranged along the second direction Y, and the fourth sub-plugs 216 are located on the surface of the contact layer 210 on the drain region 207 and are arranged along the first direction X.

In this embodiment, before forming the conductive structure, an interlayer dielectric layer (not shown) is further formed on the substrate, and the conductive structure is located in the interlayer dielectric layer.

The forming method of the conductive structure comprises a large Ma Geshi process (Damascene) or a double large Ma Geshi process (Dual Damascene). In this embodiment, the method for forming the conductive structures includes a process Ma Geshi, i.e., the first conductive plug structure and the second conductive plug structure are formed first, and then the first conductive layer 211 and the second conductive layer 212 are formed. In another embodiment, the conductive structure may also be formed using a double-sided Ma Geshi process.

In this embodiment, by adjusting each dimension parameter of the device, the performance of the device may be accurately adjusted, and specific dimension parameter settings are described below.

With continued reference to fig. 14, the method includes a first dimension W1 of the first sub-plug 213 from the contact layer 210 on the source region 206, the first dimension W1 ranging from 0.1 to 1 micron, the contact layer 210 on the source region 206 having a second dimension W2 in the second direction Y in a range of less than or equal to 2 microns, the contact layer 210 on the drain region 207 having a third dimension W3 in the second direction Y in a range of 0.2 to 4 microns, the contact layer 210 on the drain region 207 having a fourth dimension W4 in a range of 0.1 to 1 micron, each of the main gates 204 having a fifth dimension W5 in the second direction Y in a range of 0.1 to 1 micron, the contact layer 210 on the drain region 207 having a seventh dimension W3 in a range of 0.2 to 4 microns, the first sub-plug 205 having a range of 0.7 to 7 microns, and the fifth dimension W5 in a range of 8 to 1 micron, the first sub-plug 205 having a range of 0.7 microns to 7 microns, and the eighth dimension W2 in a range of the second dimension W2 to 7 microns, and the contact layer 210 having a range of the eighth dimension W2 to 7 microns in the second direction W2 in a range of 0.7 microns to 7 microns.

The device performance can be accurately adjusted by adjusting one or more parameters from the first dimension W1 to the ninth dimension W9 to meet different requirements, which specifically includes:

For the forward characteristics of the device, it2 can be increased by increasing one or more of W1, W3 and W4, vt1 and Vt2 can be increased by increasing W2, leakage can be reduced by increasing W5, vt2 can be increased by increasing W6, and It2 per unit area can be reduced.

The reverse characteristic of the device is that the increase of W7 is beneficial to the improvement of Vt2, and the increase of W8 is beneficial to the improvement of It2.

Correspondingly, the embodiment of the invention further provides a semiconductor structure formed by adopting the method, and referring to fig. 8 to fig. 17, the semiconductor structure comprises a substrate, wherein the substrate comprises an insulating layer 200 and a substrate layer 201 positioned on the insulating layer 200, the substrate layer 201 comprises an active region, the active region comprises a first region I and a second region II which are arranged along a first direction X, the first region I and the second region II are adjacent, a gate structure positioned on part of the active region comprises a plurality of main gates 204 positioned on the first region I and a plurality of first auxiliary gates 205 positioned on the second region II, the plurality of main gates 204 are connected with the first auxiliary gates 205, the plurality of main gates 204 are parallel to the first direction X and are arranged along a second direction Y, the first auxiliary gates 205 are parallel to the second direction Y, the first direction X and the second direction Y are perpendicular to each other, the gate structure comprises a plurality of main gates 204 positioned on part of the first region I and a plurality of auxiliary gates 204 positioned on the second region II, the first region 206 and the second region 208 are positioned on the first region 207 and the second region 206 and the second region 208 are respectively positioned on the first region and the second region 206 is not in the first region and the second region 207 are respectively formed on the same body.

Here, the source regions 206, the first body regions 208 and the gate structure are electrically connected as cathode terminals (cathode), the drain regions 207 are electrically connected as anode terminals (anode), so that a positive ESD protection effect can be achieved, the first body regions 208 are grounded, charges accumulated in the body can be timely discharged when the ESD structure is turned on, adverse effects of floating body effects are weakened, accordingly, the turn-on voltage of the ESD structure is improved, device leakage is reduced, static power consumption is reduced, discharge capacity is improved, performances such as thermal effects are improved, robustness of the ESD structure is improved, and in addition, due to the existence of the first auxiliary gate 205, a parasitic diode structure exists between the first body regions 208 and the drain regions 207, and due to the fact that the first body regions 208 are grounded, the structure can be temporarily turned on when negative signals are generated at the drain regions 207, and further, the effect of discharging ESD current is achieved, and therefore the dual-direction ESD protection characteristic is achieved.

In this embodiment, the semiconductor structure further includes a conductive structure on the substrate, where the conductive structure includes a first conductive layer 211 and a second conductive layer 212 that are electrically isolated from each other, the first conductive layer 211 electrically connects the source regions 206, the first body regions 208, and the gate structure, and the second conductive layer 212 electrically connects the drain regions 207.

In this embodiment, the semiconductor structure further includes a blocking layer 209 on the substrate, where the blocking layer 209 covers the surfaces of the plurality of main gates 204, the blocking layer further extends to a portion of the surfaces of the source regions 206 and the drain regions 207, and a portion of the surfaces of the first auxiliary gates 205 adjacent to the plurality of main gates 204, a contact layer 210 on the surfaces of the source regions 206, the drain regions 207, and the first body regions 208 exposed by the blocking layer 209, the first conductive layer 211 is electrically connected to the plurality of source regions 206, the first body regions 208, and the gate structure through the contact layer 210, and the second conductive layer 212 is electrically connected to the plurality of drain regions 207 through the contact layer 210.

In this embodiment, the blocking layer 209 is in a shape of a "back" letter. In another embodiment, the barrier layer is of the "II" type, i.e. parallel to the first direction and arranged along the second direction.

Specifically, in the second direction Y, the first auxiliary gate 205 includes a plurality of extraction regions (not shown) and a plurality of body regions (not shown), each of the extraction regions is adjacent to the source region 206, each of the body regions is located between two adjacent extraction regions, each of the body regions further includes an adjacent region (not shown) adjacent to the drain region 207, and the barrier layer 209 covers a surface of the adjacent region and extends to a portion of a surface of the drain region 207 and a portion of a surface of the source region 206 adjacent to the first auxiliary gate 205, and exposes each of the extraction regions. The extraction region is used for defining the position of a third sub-plug, and the first conductive layer is electrically connected with the grid structure through the third sub-plug. More specifically, the contact layer 210 is further located on a surface of each of the lead-out regions, so as to reduce a contact resistance between the third sub-plug and the gate structure.

In this embodiment, the conductive structure further includes a first conductive plug structure including a plurality of first sub-plugs 213 electrically connecting the first conductive layer 211 with each of the source regions 206, a plurality of second conductive plugs 214 electrically connecting the first conductive layer 211 with the first body regions 208, and a third sub-plug 215 electrically connecting the first conductive layer 211 with the gate structure, and a second conductive plug structure including a plurality of fourth sub-plugs 216 electrically connecting the second conductive layer 212 with each of the drain regions 207.

In this embodiment, the distance between the first sub-plug 213 and the contact layer 210 on the source region 206 is a first size ranging from 0.1 to 1 micron, the contact layer 210 on the source region 206 has a second size ranging from 0.1 to 1 micron in the second direction Y, the second size ranging from less than or equal to 2 microns, the contact layer 210 on the drain region 207 has a third size ranging from 0.2 to 4 microns in the second direction, the distance between the contact layer 210 on the drain region 207 and the fourth sub-plug 216 is a fourth size ranging from 0.1 to 1 micron, the main gate 204 has a fifth size ranging from 0.1 to 1 micron in the second direction Y, the main gate 204 on the first region I has a sixth size ranging from 5 to 40 microns in the first direction X, the auxiliary gate 205 has a seventh size ranging from 0.205 to 1 micron in the second direction Y, the fifth size ranging from 0.205 to 2 microns in the seventh direction X, the contact layer 216 has a seventh size ranging from 0.205 to 1 micron in the eighth direction X, and the fifth size ranging from 0.205 to 2 microns in the eighth direction Y. The device performance can be precisely adjusted by adjusting one or more parameters of the first dimension W1 to the ninth dimension W9 so as to meet different requirements.

In this embodiment, the conductive structure further includes a well region 202 located in the first region I and the second region II, and the bottom of the well region 202 is in contact with the insulating layer 200.

In this embodiment, the substrate layer 201 further includes an isolation structure 203 surrounding the active region.

In this embodiment, the plurality of main gates 204 further extend onto a portion of the isolation structure 203, and the first auxiliary gate 205 further extends onto a portion of the isolation structure 203.

In the above embodiment, the first subsidiary gate and the first body region are added at one end of the main gate, the first body region being used to overcome the influence of the floating body effect, however, especially when the length of the main gate (refer to the sixth dimension W6 in fig. 15) is large (e.g., greater than 20 μm), the other end far from the first subsidiary gate may still be influenced by the floating body effect. For this reason, in this embodiment, a second auxiliary gate and a second body region are also added at the other end of the main gate, and the second body region is grounded to further overcome the influence of the floating body effect, so as to increase the robustness of the ESD structure.

Referring to fig. 18 and 19, fig. 18 is a schematic top view structure, fig. 19 is a schematic cross-sectional structure along the direction EE1 in fig. 18, and a substrate is provided, wherein the substrate includes an insulating layer 300 and a substrate layer 301 disposed on the insulating layer 300, and the substrate layer 301 includes an active region, and the active region includes a first region i and a second region ii arranged along a first direction X, and the first region i and the second region ii are adjacent.

In this embodiment, the active region further includes a third region iii adjacent to the first region i, and the third region iii and the second region ii are located on two sides of the first region i, respectively.

And forming a gate structure on part of the active region.

In this embodiment, before forming the gate structure, a well region 302 is further formed in the first region i, the second region ii, and the third region iii, and the bottom of the well region 302 is in contact with the insulating layer 300.

In this embodiment, the substrate layer 301 further includes an isolation region (not shown) surrounding the active region, and before forming the well region 302, etching the isolation region, forming a recess (not shown) in the substrate, the recess exposing the insulating layer 300, and forming an isolation structure 303 in the recess.

Referring to fig. 20 to 22, fig. 20 is a schematic top view structure, fig. 21 is a schematic cross-sectional structure along the direction EE1 in fig. 20, fig. 22 is a schematic cross-sectional structure along the direction FF1 in fig. 20, a gate structure is formed on a portion of the active region, the gate structure includes a plurality of main gates 304 located on the first region i and a plurality of first auxiliary gates 305 located on the second region ii, the plurality of main gates 304 are connected with the first auxiliary gates 305, the plurality of main gates 304 are parallel to the first direction X and are arranged along the second direction Y, the first auxiliary gates 305 are parallel to the second direction Y, and the first direction X and the second direction Y are perpendicular to each other.

In this embodiment, the gate structure further includes a second auxiliary gate 306 located on the third region iii, and the plurality of main gates 304 are connected to the second auxiliary gate 306, and the second auxiliary gate 306 is parallel to the second direction Y.

In this embodiment, the plurality of main gates 304 further extend onto a portion of the isolation structure 303, the first auxiliary gate 305 further extends onto a portion of the isolation structure 303, and the second auxiliary gate 306 further extends onto a portion of the isolation structure 303.

Referring to fig. 23 to 25, fig. 23 is a schematic top view, fig. 24 is a schematic cross-sectional view along the EE1 direction in fig. 23, fig. 25 is a schematic cross-sectional view along the FF1 direction in fig. 24, a source region 307 and a drain region 308 are respectively formed in the first region i on both sides of each main gate 304, each drain region 308 is located between adjacent source regions 307, the source regions 307 and the drain regions 308 have a first conductivity type, a first body region 309 is formed in the second region ii, the first body region 309 and the main gate 304 are respectively located on both sides of the first auxiliary gate 305, and the first body region 309 has a second conductivity type, the first conductivity type being different from the second conductivity type.

In this embodiment, a second body region 310 is also formed in the third region iii, the second body region 310 and the main gate 304 are located on two sides of the second auxiliary gate 306, respectively, and the second body region 310 has the second conductivity type.

In this embodiment, the source region 307, the drain region 308, the first body region 309, and the second body region 310 are all located within the well region 202.

In this embodiment, bottoms of the source region 307, the drain region 308, the first body region 309, and the second body region 310 are in contact with the insulating layer 200.

In this embodiment, after the source region 307, the drain region 308, the first body region 309 and the second body region 310 are formed, a conductive structure is further formed on the substrate, where the conductive structure includes a first conductive layer and a second conductive layer that are electrically isolated from each other, the first conductive layer electrically connects a plurality of the source regions 307, the first body region 309, the second body region 310 and the gate structure, and the second conductive layer is electrically connected with the plurality of drain regions 308. Specifically, before forming the conductive structure, please refer to fig. 26 to 28.

Referring to fig. 26 to 28, fig. 11 is a schematic top view, fig. 12 is a schematic cross-sectional view along the MM1 direction in fig. 11 (the barrier layer is omitted), fig. 13 is a schematic cross-sectional view along the NN1 direction in fig. 11 (the barrier layer is omitted), a barrier layer 311 is formed on the substrate, the barrier layer 311 covers the surfaces of the plurality of main gates 304, and a contact layer 312 is formed on the surfaces of the source region 307, the drain region 308 and the first body region 309 exposed by the barrier layer 311.

In this embodiment, the blocking layer 311 further extends to a portion of the surface of the source region 307, a portion of the surface of the drain region 308, a portion of the surface of the first auxiliary gate 305, and a portion of the surface of the second auxiliary gate 306 adjacent to the plurality of main gates 304.

Specifically, in the second direction Y, the first auxiliary gate 305 includes a plurality of first lead-out regions (not shown) and a plurality of first body regions (not shown), each of the first lead-out regions is adjacent to the source region 307, each of the first body regions is located between adjacent first lead-out regions, each of the first body regions further includes a first contact region (not shown) adjacent to the drain region 308, the barrier layer 311 covers a surface of the first contact region and extends to a portion of a surface of the drain region 308 and a portion of a surface of the source region 307 adjacent to the first auxiliary gate 305 and exposes each of the first lead-out regions, in the second direction Y, the second auxiliary gate 306 includes a plurality of second lead-out regions (not shown) and a plurality of second body regions (not shown) adjacent to the source region 307, each of the second lead-out regions is located between adjacent second body regions, each of the barrier layer 311 further covers a surface of the second contact region 308 adjacent to the second contact region 308, and extends to a portion of the second contact region 306. The first extraction region is used for defining the position of a subsequent third sub-plug, the second extraction region is used for defining the position of a subsequent fifth sub-plug, and the first conductive layer is electrically connected with the gate structure through the third sub-plug and the fifth sub-plug.

More specifically, the contact layer 312 is further located on the surfaces of each of the first lead-out regions and each of the second lead-out regions, for reducing contact resistance between the third sub-plug and the gate structure, and between the fifth sub-plug and the gate structure.

Referring to fig. 29 to 32, fig. 29 is a schematic top view structure, fig. 30 is a schematic top view structure with a conductive structure added to fig. 29, fig. 31 is a schematic cross-sectional structure along the EE1 direction in fig. 30, fig. 32 is a schematic cross-sectional structure along the FF1 direction in fig. 30, a conductive structure is formed on the substrate, the conductive structure includes a first conductive layer 313 and a second conductive layer 314 electrically isolated from each other, the first conductive layer 313 electrically connects a plurality of source regions 307, the first body regions 309 and the gate structure, and the second conductive layer 314 electrically connects a plurality of drain regions 308.

In this embodiment, the first conductive layer 313 is also electrically connected to the second body region 310.

In the above structure, when the structure is used as a forward ESD, the first conductive layer 313 serves as a cathode terminal (cathode) lead, and the second conductive layer 314 serves as an anode terminal (anode) lead. In contrast to the previous embodiment, a second auxiliary gate 306 and a second body region 310 are added at the other end of the main gate 304, and the second body region 310 is grounded to further overcome the influence of the floating body effect, so as to increase the robustness of the ESD structure. Specifically, in the TLP test, it2 of the unit area of the structure of this embodiment is improved by about 5 times, and the performance of the device is significantly improved, compared to the structure of the previous embodiment.

In addition, in addition to the parasitic diode structure between the first body region 309 and the drain region 308, there is also a parasitic diode structure between the second body region 310 and the drain region 308, resulting in a device having better negative-going protection characteristics.

Here, for convenience of explanation, fig. 31 and 32 do not show the conductive structure, but only show the electrical connection relationship.

Specifically, the first conductive layer 313 is electrically connected to the source regions 307, the first body regions 309, the gate structures, and the second body regions 310 through the contact layer 312, and the second conductive layer 314 is electrically connected to the drain regions 308 through the contact layer 312.

In this embodiment, the conductive structure further includes a first conductive plug structure including a plurality of first sub-plugs 315 electrically connecting the first conductive layer 313 to each of the source regions 307, a plurality of second sub-plugs 316 electrically connecting the first conductive layer 313 to the first body regions 309, a third sub-plug 317 electrically connecting the first conductive layer 313 to the first auxiliary gate 305, a fifth sub-plug 318 electrically connecting the first conductive layer 313 to the second auxiliary gate 306, and a sixth sub-plug 319 electrically connecting the first conductive layer 313 to the second body regions 310, and a second conductive plug structure including a plurality of fourth sub-plugs 320 electrically connecting the second conductive layer 314 to each of the drain regions 308.

Specifically, the first sub-plugs 315 are located on the surface of the contact layer 312 on the source region 307 and are arranged along the first direction X, the second sub-plugs 316 are located on the surface of the contact layer 312 on the first body region 309 and are arranged along the second direction Y, the third sub-plugs 317 are located on the surface of the first auxiliary gate 305 (as shown in fig. 23) and are arranged along the second direction Y, the fourth sub-plugs 320 are located on the surface of the contact layer 312 on the drain region 308 and are arranged along the first direction X, the fifth sub-plugs 318 are located on the surface of the second auxiliary gate 306 (as shown in fig. 23) and are arranged along the second direction Y, and the sixth sub-plugs 319 are located on the surface of the contact layer 312 on the second body region 310 and are arranged along the second direction Y.

In this embodiment, by adjusting each dimension parameter of the device, the performance of the device can be accurately adjusted, and reference is made to the previous embodiment for specific dimension parameter setting, which is not described herein.

Accordingly, another embodiment of the present invention further provides a semiconductor structure formed by the above method, and please continue to refer to fig. 29 to 32.

The main difference between this embodiment and the previous embodiment is that, based on the previous embodiment, the semiconductor structure of this embodiment further includes:

The active region further includes a third region iii adjacent to the first region i, the third region iii and the second region ii being located on both sides of the first region i, respectively, the gate structure further includes a second auxiliary gate 306 located on the third region iii, the plurality of main gates 304 are connected to the second auxiliary gate 306, the second auxiliary gate 306 is parallel to the second direction Y, a second body region 310 located in the third region iii, the second body region 310 and the main gate 304 are located on both sides of the second auxiliary gate 306, respectively, the second body region 310 has a second conductivity type, and the first conductive layer 313 is further electrically connected to the second body region 310.

The other parts of the structure in this embodiment refer to the previous embodiment, and are not described herein.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A semiconductor structure, comprising:

A substrate, the substrate comprising an insulating layer and a substrate layer located on the insulating layer, the substrate layer comprising an active region, the active region comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent;

a gate structure located on part of the active area, the gate structure comprising a plurality of main gates located on the first area and a first auxiliary gate located on the second area, the plurality of main gates being connected to the first auxiliary gate, the plurality of main gates being parallel to the first direction and arranged along a second direction, the first auxiliary gate being parallel to the second direction, and the first direction and the second direction being perpendicular to each other;

A source region and a drain region in the first region respectively located on both sides of each main gate, each drain region is located between adjacent source regions, and the source region and the drain region have a first conductivity type;

A first body region is located in the second region, the first body region and the main gate are respectively located on both sides of the first auxiliary gate, the first body region has a second conductivity type, and the first conductivity type is different from the second conductivity type.

2. The semiconductor structure as described in claim 1 is characterized in that it also includes: a conductive structure located on the substrate, the conductive structure includes a first conductive layer and a second conductive layer electrically isolated from each other, the first conductive layer electrically connects the plurality of source regions, the first body region and the gate structure, and the second conductive layer is electrically connected to the plurality of drain regions.

3. The semiconductor structure as described in claim 2 is characterized in that it also includes: a blocking layer located on the substrate, the blocking layer covering the surfaces of the several main gates; the blocking layer also extends to the surface of the portion of the source region and the surface of the portion of the drain region adjacent to the several main gates, and the surface of the portion of the first auxiliary gate; a contact layer located on the surface of the source region, the drain region, and the first body region exposed by the blocking layer; the first conductive layer is electrically connected to the several source regions, the first body region and the gate structure through the contact layer; the second conductive layer is electrically connected to the several drain regions through the contact layer.

4. The semiconductor structure as described in claim 3 is characterized in that the conductive structure further includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure includes a plurality of first sub-plugs electrically connecting the first conductive layer to each of the source regions, a plurality of second sub-plugs electrically connecting the first conductive layer to the first body region and a third sub-plug electrically connecting the first conductive layer to the gate structure, and the second conductive plug structure includes a plurality of fourth sub-plugs electrically connecting the second conductive layer to each of the drain regions; the plurality of first sub-plugs are located on the surface of the contact layer on the source region and are arranged along the first direction; the plurality of second sub-plugs are located on the surface of the contact layer on the first body region and are arranged along the second direction; the plurality of third sub-plugs are located on the surface of the first auxiliary gate and are arranged along the second direction; the plurality of fourth sub-plugs are located on the surface of the contact layer on the drain region and are arranged along the first direction.

5. The semiconductor structure according to claim 4, characterized in that the distance between the first sub-plug and the contact layer on the source region is a first size, and the first size ranges from 0.1 microns to 1 micron; the contact layer on the source region has a second size in the second direction, and the second size ranges from less than or equal to 2 microns; the contact layer on the drain region has a third size in the second direction, and the third size ranges from 0.2 microns to 4 microns; the distance between the contact layer on the drain region and the fourth sub-plug is a fourth size, and the fourth size ranges from 0.1 microns to 1 micron; each of the The main gate has a fifth dimension in the second direction, and the fifth dimension ranges from 0.1 micron to 1 micron; each of the main gates located on the first region has a sixth dimension in the first direction, and the sixth dimension ranges from 5 microns to 40 microns; the first auxiliary gate has a seventh dimension in the first direction, and the seventh dimension ranges from 0.2 microns to 2 microns; the distance between the second sub-plug and the first auxiliary gate is an eighth dimension, and the eighth dimension ranges from 0.1 micron to 1 micron; the contact layer on the drain region has a ninth dimension from the first auxiliary gate, and the ninth dimension ranges from less than or equal to 2 microns.

6. The semiconductor structure as described in claim 2 is characterized in that the active area also includes a third area adjacent to the first area, and the third area and the second area are respectively located on both sides of the first area; the gate structure also includes a second auxiliary gate located on the third area, the plurality of main gates are connected to the second auxiliary gates, and the second auxiliary gates are parallel to the second direction; the structure also includes: a second body region located in the third area, the second body region and the main gate are respectively located on both sides of the second auxiliary gate, and the second body region has a second conductivity type; the first conductive layer is also electrically connected to the second body region.

7. The semiconductor structure as described in claim 1 is characterized in that it also includes: a well region located in the first region and the second region; the bottom of the well region is in contact with the insulating layer; the source region, the drain region and the first body region are all located in the well region; the bottom of the source region, the drain region and the first body region are all in contact with the insulating layer.

8. The semiconductor structure as described in claim 1 is characterized in that the substrate layer also includes an isolation structure surrounding the active area; the plurality of main gates also extend to a portion of the isolation structure; and the first auxiliary gate also extends to a portion of the isolation structure.

9. The semiconductor structure according to claim 1, wherein the material of the insulating layer comprises silicon oxide; and the material of the substrate layer comprises a combination of one or more of silicon, silicon germanium and germanium.

10. A method for forming a semiconductor structure, comprising:

Providing a substrate, the substrate comprising an insulating layer and a substrate layer located on the insulating layer, the substrate layer comprising an active region, the active region comprising a first region and a second region arranged along a first direction, the first region and the second region being adjacent to each other;

forming a gate structure on part of the active area, the gate structure comprising a plurality of main gates located on the first area and a first auxiliary gate located on the second area, the plurality of main gates being connected to the first auxiliary gate, the plurality of main gates being parallel to the first direction and arranged along a second direction, the first auxiliary gate being parallel to the second direction, and the first direction and the second direction being perpendicular to each other;

Forming a source region and a drain region in the first region on both sides of each main gate respectively, each drain region is located between adjacent source regions, and the source region and the drain region have a first conductivity type;

A first body region is formed in the second region. The first body region and the main gate are respectively located on both sides of the first auxiliary gate. The first body region has a second conductivity type, which is different from the second conductivity type.

11. The method for forming a semiconductor structure as described in claim 10 is characterized in that after forming the source region, the drain region and the first body region, it also includes: forming a conductive structure on the substrate, the conductive structure includes a first conductive layer and a second conductive layer electrically isolated from each other, the first conductive layer electrically connects some of the source regions, the first body region and the gate structure, and the second conductive layer is electrically connected to the some drain regions.

12. The method for forming a semiconductor structure as described in claim 11 is characterized in that, before forming the conductive structure, it also includes: forming a blocking layer on the substrate, the blocking layer covering the surfaces of the several main gates; the blocking layer also extends to the surface of the portion of the source region and the surface of the portion of the drain region adjacent to the several main gates, and the surface of the portion of the first auxiliary gate; forming a contact layer on the surface of the source region, the drain region and the first body region exposed by the blocking layer; the first conductive layer is electrically connected to the several source regions, the first body region and the gate structure through the contact layer; and the second conductive layer is electrically connected to the several drain regions through the contact layer.

13 . The method for forming a semiconductor structure according to claim 12 , wherein the process for forming the contact layer comprises a metal silicide treatment process.

14. The method for forming a semiconductor structure as described in claim 12 is characterized in that the conductive structure further includes a first conductive plug structure and a second conductive plug structure, the first conductive plug structure includes a plurality of first sub-plugs electrically connecting the first conductive layer to each of the source regions, a plurality of second sub-plugs electrically connecting the first conductive layer to the first body region, and a third sub-plug electrically connecting the first conductive layer to the gate structure, and the second conductive plug structure includes a plurality of fourth sub-plugs electrically connecting the second conductive layer to each of the drain regions; the plurality of first sub-plugs are located on the surface of the contact layer on the source region and are arranged along the first direction; the plurality of second sub-plugs are located on the surface of the contact layer on the first body region and are arranged along the second direction; the plurality of third sub-plugs are located on the surface of the first auxiliary gate and are arranged along the second direction; the plurality of fourth sub-plugs are located on the surface of the contact layer on the drain region and are arranged along the first direction.

15. The method for forming a semiconductor structure as described in claim 11 is characterized in that the active area also includes a third area adjacent to the first area, and the third area and the second area are respectively located on both sides of the first area; the gate structure also includes a second auxiliary gate located on the third area, the plurality of main gates are connected to the second auxiliary gates, and the second auxiliary gates are parallel to the second direction; the method also includes: forming a second body region in the third area, the second body region and the main gate are respectively located on both sides of the second auxiliary gate, and the second body region has a second conductivity type; the first conductive layer is also electrically connected to the second body region.

16. The method for forming a semiconductor structure as described in claim 10 is characterized in that, before forming the gate structure, it also includes: forming a well region in the first region and the second region; the bottom of the well region is in contact with the insulating layer; the source region, the drain region and the first body region are all located in the well region; the bottom of the source region, the drain region and the first body region are all in contact with the insulating layer.

17. The method for forming a semiconductor structure according to claim 16, characterized in that the process for forming the well region comprises a first ion implantation process; process parameters of the first ion implantation process comprise: implanted ions comprise N-type or P-type conductive ions, an implantation energy ranges from 10 KeV to 100 KeV, and an implantation dose ranges from 1E12 atom/ ^cm2 to 1E13 atom/ ^cm2 .

18. The method for forming a semiconductor structure as described in claim 16 is characterized in that the substrate layer also includes an isolation region surrounding the active region; before forming the well region, it also includes: etching the isolation region to form a groove in the substrate, the groove exposing the insulating layer; and forming an isolation structure in the groove.

19. The method for forming a semiconductor structure as described in claim 18 is characterized in that the method for forming the groove further includes: after exposing the insulating layer, continuing to etch the insulating layer at the bottom of the groove; the groove has a first depth in the insulating layer, and the groove has a second depth in the substrate layer, and the ratio of the first depth to the second depth ranges from 5% to 30%.

20. The method for forming a semiconductor structure according to claim 10, characterized in that the process for forming the source region and the drain region comprises a second ion implantation process; process parameters of the second ion implantation process comprise: doping ions comprise N-type or P-type conductive ions, an implantation energy range is 5KeV to 100KeV, and an implantation dose range is 1E15atom/ ^cm2 to 9E15atom/ ^cm2 .

21. The method for forming a semiconductor structure according to claim 10, characterized in that the process for forming the first body region comprises a third ion implantation process; process parameters of the third ion implantation process comprise: doping ions comprise N-type or P-type conductive ions, an implantation energy range is 5KeV to 100KeV, and an implantation dose range is 1E15atom/ ^cm2 to 9E15atom/ ^cm2 .