CN120045140B - Multi-port synchronous FIFO data reading method, device, system, equipment and medium - Google Patents

Abstract

The application provides a multi-port synchronous FIFO data reading method, a device, a system, equipment and a medium, wherein the method comprises the steps of acquiring a reading enabling signal corresponding to each reading port and the current state information of the FIFO when a plurality of reading ports trigger corresponding data reading requests in parallel; the method comprises the steps of enabling a read enabling signal to indicate whether a read operation is carried out on a read port or not, determining a target address for each read port according to the read enabling signal and current state information of the FIFO, enabling the target address to represent identification of a data read address, selecting target data from a register file or write port data through a multiplexer according to the target address, enabling the write port data to refer to data which are currently written into the FIFO, inputting the target data into a register through an input port to carry out beat operation, and carrying out the read operation through a data read interface corresponding to the FIFO. The scheme avoids the problem of large MUX delay caused by the increase of the FIFO depth in the traditional design, and improves the overall running speed and performance of the system.

Description

Multi-port synchronous FIFO data reading method, device, system, equipment and medium

Technical Field

The present application relates to the field of processor technology, and in particular to a multi-port synchronous FIFO data reading method, apparatus, system, device and medium.

Background Art

In modern digital system design, multi-port synchronous First-In First-Out (FIFO) memory, a first-in, first-out queue storage structure with multiple read and write ports, where all read and write operations are synchronized based on a single global clock signal, has been widely used in various data processing and transmission scenarios, such as high-speed data acquisition systems, network communication equipment, and multimedia signal processing platforms. In these applications, multi-port synchronous FIFOs can buffer and coordinate data between different clock domains, ensuring efficient and stable data flow across multiple modules.

Currently, related technologies use a classic multi-port synchronous FIFO circuit structure. In this design, each output port selects data from the register stack during a read operation through a large multiplexer (MUX) tied to the FIFO depth. As the demand for FIFO depth increases, the number of MUX input ports increases, and the internal combinational logic becomes more complex, resulting in a longer delay (Delay1), which reduces the speed and performance of the entire system.

Summary of the Invention

Embodiments of the present application provide a multi-port synchronous FIFO data reading method, apparatus, system, device, and medium.

A first aspect of an embodiment of the present application provides a multi-port synchronous FIFO data reading method, the method comprising:

When multiple read ports trigger corresponding data read requests in parallel, obtain a read enable signal corresponding to each read port and current status information of the FIFO; the read enable signal is used to indicate whether the read port performs a read operation;

For each of the read ports, a target address is determined according to the read enable signal and the current state information of the FIFO; the target address is used to represent an identifier of a data read address;

According to the target address, target data is selected from the register file or the write port data through a multiplexer; the write port data refers to the data currently being written into the FIFO;

The target data is input into the register through the input port to perform a beat operation and a read operation is performed through the data read interface corresponding to the FIFO.

A second aspect of an embodiment of the present application provides a multi-port synchronous FIFO data reading device, comprising:

An acquisition module, configured to acquire a read enable signal corresponding to each read port and current status information of the FIFO when corresponding data read requests are triggered in parallel by multiple read ports; the read enable signal is used to indicate whether the read port performs a read operation;

a determination module, configured to determine, for each of the read ports, a target address according to the read enable signal and the current state information of the FIFO; the target address being used to identify a data read address;

A selection module is used to select target data from a register file or write port data through a multiplexer according to the target address; the write port data refers to data currently being written into the FIFO;

The reading module is used to perform a beat operation on the target data through a register and perform a read operation through the multi-port synchronous FIFO data reading interface.

According to a third aspect of an embodiment of the present application, a multi-port synchronous FIFO data reading system is provided, comprising: a register file, a plurality of multiplexers, a plurality of registers, a plurality of read pointers, a plurality of read ports, and a data reading interface, wherein each of the multiplexers establishes a communication connection with a corresponding register, and the data reading interface establishes a communication connection with each of the registers and each of the read pointers, respectively;

Each of the read pointers is used to: when multiple read ports trigger corresponding data read requests in parallel, obtain the read enable signal corresponding to the read port and the current status information of the FIFO and send them to the corresponding multiplexer; the read enable signal is used to indicate whether the read port performs a read operation;

Each of the multiplexers is configured to: for each of the read ports, determine a target address based on the read enable signal and the current state information of the FIFO; select target data from a register file or write port data based on the target address; the target address is used to identify a data read address; the write port data refers to data currently being written into the FIFO;

Each of the registers is used to: perform a beat operation on the target data and transmit the target data to the data reading interface;

The data reading interface is used to perform a read operation on the target data.

According to a fourth aspect of the embodiments of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

According to a fifth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above methods are implemented.

In an embodiment of the present application, a multi-port synchronous FIFO data reading method, apparatus, system, equipment and medium are provided, the method comprising: when a plurality of read ports trigger corresponding data read requests in parallel, obtaining a read enable signal corresponding to each read port and the current status information of the FIFO, and for each read port, determining a target address according to the read enable signal and the current status information of the FIFO, and selecting a target from a register stack or write port data through a multiplexer according to the target address, inputting the target data into a register through an input port to perform a beat operation, and performing a read operation through a data read interface corresponding to the FIFO. The technical solution in the present application can determine the target address in advance according to the obtained read enable signal and the current status information of the FIFO when a plurality of read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or the write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck in the downstream long combinational logic, and further improving the overall operating speed and performance of the system.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

FIG1 is a schematic diagram of an existing FIFO structure provided by an embodiment of the present application;

FIG2 is a schematic diagram of a structure of a delay generated by reading data through different reading ports according to an embodiment of the present application;

FIG3 is a schematic diagram of the structure of a computer device provided in one embodiment of the present application;

FIG4 is a flow chart of a multi-port synchronous FIFO data reading method provided by one embodiment of the present application;

FIG5 is a flow chart of a method for generating a corresponding target address according to a read enable signal according to another embodiment of the present application;

FIG6 is a schematic structural diagram of a multi-port synchronous FIFO data reading device provided by one embodiment of the present application;

FIG7 is a schematic structural diagram of a multi-port synchronous FIFO data reading system provided by an embodiment of the present application.

DETAILED DESCRIPTION

In the process of implementing the present application, the inventors discovered that the traditional multi-port synchronous FIFO circuit structure has an output data timing delay problem, which leads to a decrease in the operating speed and performance of the entire system.

In order to make the technical solutions and advantages of the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, and are not an exhaustive list of all the embodiments. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other unless they conflict.

As mentioned in the background, the multi-port synchronous FIFO structure features synchronous read and write, multiple read and write ports, read and write control logic, full/empty state detection, address mapping, and data consistency. Synchronous read and write means that all read and write operations are performed in the same clock domain, which means the read and write clock frequencies are the same, thus avoiding synchronization issues that may arise in cross-clock domain designs. Multiple read and write ports refer to the design containing multiple independent read and write interfaces, allowing multiple data sources to write data to or read data from the FIFO simultaneously, improving data throughput and the system's parallel processing capabilities. The read and write control logic includes the management and update logic of the read and write pointers, as well as the generation of read and write enable signals. Because it is a synchronous FIFO, the generation of these control signals must take into account clock domain synchronization issues to ensure that read and write operations within a given clock cycle are mutually exclusive and prevent data contention. Full/empty state detection refers to determining the FIFO status by comparing the read and write pointers, including full, empty, and half-full states. These status signals are the result of combinational logic and are promptly fed back to the read and write controller to prevent overflow or underflow. Address mapping refers to the use of complex address mapping algorithms for multiple read/write ports to ensure that each read/write port can correctly access the corresponding storage location in the FIFO. Data consistency refers to the requirement that data in a multi-port synchronous FIFO must always be in first-in, first-out order, regardless of which port the data is written or read from. In practical applications, multi-port synchronous FIFOs are commonly used in high-performance data exchange, multi-processor communication, pipeline design, and high-speed data acquisition. They can efficiently distribute, collect, and temporarily store data, effectively solving the data synchronization and caching requirements of parallel processing.

Please refer to Figure 1, which shows a schematic diagram of a classic multi-port synchronous FIFO structure. It includes several key components and interface signals, including a register file, a multiplexer (MUX), a write pointer, a read pointer, flag logic, a data write interface, and a data read interface. The register file is used to store data and is the main storage component of the FIFO. The flag logic generates FIFO status signals, including full and empty signals. These signals are fed back to the write and read interfaces to control read and write operations. Both the write and read paths have multiplexers. The write path multiplexer selects the corresponding write port data (wport1_data, wport2_data, etc.) for writing to the register file based on the write enable signal. The read path multiplexer selects data outputs (rport1_data, rport2_data, ..., rportN_data, etc.) from the register file based on the read enable signals (Read Enable 1, Read Enable 2, ..., Read Enable N). Write pointers (Write Pointer 1, Write Pointer 2, ..., Write Pointer N) track the data write location, while read pointers (Read Pointer 1, Read Pointer 2, ..., ReadPointer N, etc.) track the data read location. Write enable signals (Write Enable 1, Write Enable 2, ..., Write Enable N) control write pointer updates, while read enable signals (RE1, RE2, etc.) control read pointer updates.

The write interface has multiple write ports (wport1, wport2, etc., collectively referred to as wport), and the read interface has multiple read ports (rport1, rport2, etc., collectively referred to as rport).

The interface signals described above include write and read signals. The write signals include i_valid, i_ready, and full, while the read signals include o_valid, o_ready, and empty. i_valid indicates whether the input data is valid, i_ready indicates whether the FIFO is ready to receive new data, and full indicates a full FIFO state, preventing new data from being written. o_valid indicates whether the output data is valid, o_ready indicates whether the receiving end is ready to receive data, and empty indicates an empty FIFO state, preventing data from being read. The circuit described above uses these components and signals to coordinate orderly data writing and reading, ensuring the correct operation of the FIFO in different states.

In a classic multi-port synchronous FIFO design, each read port (rport) has a corresponding read address pointer (Read Pointer1 - N). When a read operation occurs, these read address pointers indicate the location in the register file (RegisterFile) where data is to be read. Because there are multiple read ports, each must select the corresponding data from the numerous storage locations in the register file. Therefore, each read port must pass through a multiplexer (MUX). The MUX's function is to select the correct read data (rport(1-N)_data) required by that read port from various storage locations in the register file based on the signals from the read address pointers.

As the required FIFO depth (DP) increases, the number of storage cells in the register file increases. Because the MUX must select data from these storage cells, the number of MUX input ports also increases accordingly. The MUX internally implements data selection through combinational logic. The more input ports, the more complex its internal logic structure and the longer the signal propagation path. Consequently, the time it takes for a signal to propagate from the MUX input to the output increases. This time is known as the combinational logic delay (Delay1). When the FIFO is connected downstream to very long combinational logic, the delay in the entire signal path is the sum of the delays in each component. Since the delay (Delay1) incurred by the MUX at the read port increases with increasing FIFO depth, it contributes significantly to the overall signal path delay. If this delay is excessive, data cannot be stably transmitted to the downstream logic within the specified clock cycle, affecting the overall system speed and making the read port output a timing bottleneck.

As shown in Figure 2, the existing classic multi-port synchronous FIFO design suffers from data output timing delays for each read data request. For example, multiple read requests may include: read port (rport1), read port (rport2), ..., and read port (rportN). Each read port (rport) has a corresponding read address pointer (Read Pointer1 - N). When a read operation occurs, these read address pointers indicate the location in the register file from which data is to be read. Therefore, each read port must pass through a multiplexer (MUX). The MUX's function is to select the correct read data (rport (1 - N)_data) required by that read port from different storage locations in the register file based on the read address pointer signal. Specifically, an rport1 request corresponds to the output of rport1 read data, an rport2 request corresponds to the output of rport2 read data, and an rportN request corresponds to the output of rportN read data. Because each read port passes through a large MUX selector, this generates a combinational logic delay (Delay1), which in turn reduces the overall system speed and performance.

Based on the above-mentioned defects, the present application provides a multi-port synchronous FIFO timing optimization method. Compared with the related technology, the technical solution in the present application can determine the target address in advance based on the read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck in the downstream long combinational logic, and further improving the overall operation speed and performance of the system.

Please refer to Figure 3, which is a schematic diagram of the structure of an example computer device provided in an embodiment of the present application. As shown in Figure 3, the computer device includes a processor, memory, a network interface, a display screen, and an input device connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium may be, for example, a magnetic disk. The non-volatile storage medium stores files (which may be files to be processed or processed files), an operating system, and computer programs. The internal memory provides an environment for the operating system and computer programs in the non-volatile storage medium to run. The network interface of the computer device is used to communicate with an external terminal via a network connection. When executed by the processor, the computer program implements a multi-port synchronous FIFO data reading method. The display screen of the computer device may be a liquid crystal display or an electronic ink display. The input device of the computer device may be a touch layer covering the display screen, or may be buttons, a trackball, or a touchpad provided on the computer device housing, or may be an external keyboard, touchpad, or mouse.

Please refer to Figure 4. The following embodiment uses the above-mentioned computer device as the execution subject and applies the multi-port synchronous FIFO data reading method provided in the embodiment of the present application to the above-mentioned computer device to perform data reading as an example for specific description. The multi-port synchronous FIFO data reading provided in the embodiment of the present application includes the following steps 201 to 204:

Step 201: When multiple read ports trigger corresponding data read requests in parallel, obtain the read enable signal corresponding to each read port and the current status information of the FIFO; the read enable signal is used to indicate whether the read port performs a read operation.

It should be noted that each read port (rport1-N) corresponds to a read enable signal (RE1-REN). When the read enable signal of a read port is valid, it indicates that the read port needs to read data. The current status information of the FIFO can include empty state, full state, nearly empty state, and nearly full state.

In the process of obtaining the above-mentioned read enable signal, combinational logic can be applied to combine the empty state of the FIFO and the external read request signal. When the FIFO is not empty and there is a data read request, the read enable signal is valid. For example, a logic AND gate is used with the non-empty signal and the external data read request as input, and the output is the read enable signal.

The FIFO structure described above includes a write pointer and a read pointer. The write pointer tracks where data is written, while the read pointer tracks where data is read. The FIFO operates by writing data at one end and reading it at the other. The write pointer points to the next location where data is to be written, and the read pointer points to the next location where data is to be read.

When write operations are faster than read operations, the write pointer will gradually move forward and approach the read pointer. When the write pointer catches up with the read pointer, that is, they point to the same position, it means that all storage units in the FIFO have been written to and there is no free space to store new data, so the FIFO is full.

Under normal circumstances, the read pointer advances as data is read, and the write pointer advances as data is written. When reads outpace writes, the read pointer gradually distances itself from the write pointer. When the read and write pointers become equal again, there are two possible scenarios. One is that the FIFO has never been written to, in which case the FIFO is naturally empty. The other is that the FIFO once had data, but after a series of read and write operations, all the data has been read. In this case, although the FIFO is not empty (because it once had data), there is actually no data left to read, indicating that the FIFO is empty.

Step 202: For each read port, determine a target address according to the read enable signal and the current state information of the FIFO; the target address is used to identify the data read address.

The target address is the address from which data is to be read. This is used to determine the address for the next read operation in advance, allowing for more efficient data reading. Different current state information in the FIFO corresponds to different target addresses.

It is understandable that in the process of determining the target address, in addition to the read enable signal, the current status information of the FIFO needs to be considered. The current status information may also include the current write pointer position, the depth of the FIFO, etc. This information can help determine whether the read port should read data from the register stack or from the write port data.

Step 203: Select target data from the register file or the write port data through a multiplexer according to the target address; the write port data refers to the data currently being written into the FIFO.

It should be noted that the target data referred to above refers to the data to be read. The target data can be represented in various data formats, such as a table, image, text, audio, video, or other formats. The target data can be one, two, or more. Each write port corresponds to a multiplexer. When the multi-port parallel FIFO includes N read ports (rport1-N) and N write ports, it also includes N multiplexers, each of which is used to perform a selection operation.

Specifically, after obtaining the target address, for each read port, the target data can be obtained from the register stack or selected from the write port data through a multiplexer according to the target address. The multiplexer has a selection function and can select the target data from one of the two situations. The target data is the data corresponding to the target address.

Step 204: input the target data into the register through the input port to perform a beat operation and perform a read operation through the data read interface corresponding to the FIFO.

It is understood that the registers described above may be D-type flip-flops (DFFs). A multi-port parallel FIFO contains multiple registers, one corresponding to each multiplexer, and multiple corresponding input ports, each corresponding to a read port and a write port. The multi-port parallel FIFO may also include a data read interface, through which the read target data can be output.

Specifically, after the target data is selected by the multiplexer, it is fed into a register (DFF, D-type flip-flop) for a tap operation. The primary purpose of the tap operation is to synchronize data processing. In digital circuits, due to varying signal transmission delays along different paths, data arrival times may be inconsistent, potentially leading to data instability or errors. By temporarily storing the data for one tap (i.e., one clock cycle), the data stabilizes in the register, ensuring that it can be correctly processed and transmitted in the next clock cycle.

In an embodiment of the present application, a multi-port synchronous FIFO data reading method is provided, the method comprising: when multiple read ports trigger corresponding data read requests in parallel, obtaining a read enable signal corresponding to each read port and the current status information of the FIFO, and for each read port, determining a target address according to the read enable signal and the current status information of the FIFO, and according to the target address, selecting a target from a register stack or write port data through a multiplexer, inputting the target data into a register through an input port to perform a beat operation, and performing a read operation through a data read interface corresponding to the FIFO. The technical solution in the present application can determine the target address in advance according to the obtained read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or the write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck in the downstream long combinational logic, and further improving the overall operating speed and performance of the system.

In an optional embodiment of the present application, the embodiment of the present application provides a specific implementation method for determining the target address according to the read enable signal and the current state information of the FIFO, the method comprising:

When the current status information of the FIFO is full, the corresponding current read address is generated according to the read enable signal, and the current read address is used as the target address; when the current status information of the FIFO is empty and the data write request corresponding to the write port is detected, the write port address is determined according to the read enable signal and used as the target address.

It should be noted that when multiple read port requests occur in a multi-port synchronous FIFO, according to the existing classic FIFO design, the corresponding read address (Read Pointer 1~N) is calculated using the read enable signal (RE1-N) of each read port, and then the corresponding read address (Read Pointer 1~N) is used to select data in the register file. In the embodiment of the present application, the read enable signal (RE1-N) of each read port (rport1-N) is used to calculate the current read address (Read Pointer Next1-N) corresponding to each read port, and this current read address is used as the target address. This current read address can directly select the current read register file data (rport(1-N)_data_reg) of each read port from the register file, thereby obtaining data in advance.

After obtaining the read enable signal and FIFO status information, a specific address calculation logic is used to generate the current read address (Read Pointer Next1 - N) based on the read enable signal and FIFO status information. This calculation logic may be a complex combinational circuit that performs corresponding operations based on different input signals to determine the correct read address for each read port.

For example, one possible calculation method is to add an offset to the current write pointer position when the read enable signal is valid. This offset may be related to factors such as the read port number and the FIFO depth, thereby obtaining the current read address. In this way, the current read register file data (rport(1-N)_data_reg) for each read port can be directly selected from the register file using this current read address.

When the current status information of the FIFO is empty and the data write request corresponding to the write port is detected, the current read address of each read port is determined according to the read enable signal, and a comparison logic judgment is performed based on the current read address of each read port and the write data address (Write Pointer (1-N), so as to determine the write port address according to the comparison result and use it as the target address.

In the embodiments of the present application, the read enable signal determines whether a read operation is permitted based on the read enable signal and the current state information of the FIFO, while the current state information of the FIFO reflects the storage status of the data in the FIFO. By combining these two factors to determine the target address, data underflow caused by performing a read operation when the FIFO is empty and the error of terminating the read operation due to the FIFO being full when not full can be avoided, thereby ensuring that the data read each time is valid and improving the accuracy of data processing.

In an optional embodiment of the present application, as shown in FIG5 , when the current status information of the FIFO is empty and a data write request corresponding to the write port is detected, a corresponding target address is generated according to a read enable signal, including:

Step 301: When the current status information of the FIFO is empty, a data read request corresponding to a read port and a data write request corresponding to a write port occur simultaneously, and the number of read ports and write ports is the same, determine the current read address of each read port according to a read enable signal.

Step 302: Obtain the current write data address of the FIFO.

Step 303: Perform a comparison logic judgment based on the current read address and write data address of each read port, and select a target address from the data of all write ports; the write data address is used to represent the current data address of the FIFO.

It's important to note that when the FIFO is empty and read and write requests occur simultaneously, and the number of read and write requests is the same, some problems may arise. The term "the number of read and write ports is the same" indicates that the number of write and read ports is the same. For example, a FIFO may have one write port with data and one read port with data requesting to read it simultaneously, or two write ports with data and two read ports with data requesting to read it simultaneously, and so on, up to the point where there are N write ports with data and N read ports with data requesting to read it simultaneously. In these cases, because the data has not yet been written to the register file, it cannot be directly read from the register file. Otherwise, incorrect data will be read or no data will be available.

To address this issue, it's necessary to obtain the write data address and perform a logical comparison between each read port's current read address and the existing write data address in the FIFO (Write Pointer (1-N)). This comparison generates N sets of selection signals, which control an N-to-1 multiplexer (MUX). This selects the appropriate data from the write port data (wport (1-N)_data) and directly feeds it into the DFF (flip-flop) input port (port (1-N)_data_nxt). This data is then passed through a 2-to-1 multiplexer to obtain the current read FIFO data (rport (1-N)_data_nxt), ensuring accurate read data even in exceptional circumstances.

In a multi-port synchronous FIFO, the write pointer can be used to obtain the address of the current write data in the FIFO. The write pointer indicates the location of the next data to be written in the FIFO. During a normal write operation, the write pointer points to each address of the FIFO storage unit in sequence. After each write operation, the write pointer is updated to the address of the next storage unit. Therefore, by recording the value of the write pointer, the address of the current write data can be obtained.

For example, in hardware design, the write pointer is usually implemented by a counter. When the write enable signal is valid, the counter will perform a counting operation driven by the clock signal, and the count value represents the address of the write pointer.

In this embodiment, when the current status information of the FIFO is empty, the data read request corresponding to the read port and the data write request corresponding to the write port occur simultaneously, and the number of read ports and write ports is the same, the current read address and write data address of each read port can be comprehensively considered, thereby ensuring that the read data can be correctly obtained even when the data is not completely written to the register stack, overcoming the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and speeding up the read data output speed.

In an optional embodiment of the present application, the above-mentioned comparison and logical judgment based on the current read address and write data address of each read port to select the target address from the data of all write ports includes the following method steps:

The current read address of each read port is compared bit by bit with the write data address to obtain a comparison result; the comparison result is used to indicate whether the current read address is consistent with the write data address; if the current read address is consistent with the write data address, the write data address is used as the target address.

Specifically, for each read port, its current read address (Read Pointer Next1-N) is compared one by one with the existing write data address (Write Pointer (1-N)) in the FIFO to obtain the comparison result. This comparison method is usually performed bit by bit, starting from the highest bit, until a different bit is found or all bits are compared.

For example, if the current read address of read port 1 is 0101, and the write data address corresponding to write port 1 in the FIFO is 0110, then starting from the highest bit, if the first bit is always 0 and the second bit is always 1, then the first and second bits are equal, but the third bit is different. The current read address corresponding to the read port is 0, and the write data address corresponding to the write port is 1. At this time, it can be determined that the address of read port 1 is different from the address of write port 1. Then, a selection signal is generated based on the result of the address comparison.

If the current read address of the read port is equal to a certain write data address, the corresponding selection signal is set to valid (usually high level 1), indicating that the data of the write port needs to be selected, and the write data address corresponding to the write port is used as the target address; if they are not equal, the selection signal is set to invalid (usually low level 0).

For example, if the current read address of read port 2 is found to be equal to the write data address of write port 3, the select signal corresponding to write port 3 in the select signal group is set to 1, and the select signals corresponding to the other write ports are set to 0. This results in N groups of select signals, each corresponding to a write port. These N groups of select signals serve as control signals for an N-to-1 multiplexer (MUX), whose input is the data from each write port (wport(1-N)_data).

In this embodiment, by comparing each read port's current read address with the write data address bit by bit, it is possible to determine whether the current read address of each read port matches the write data address. When the two addresses are completely consistent, the target address is determined, which accurately filters out valid data corresponding to the read port's needs from multiple write data. For a multi-port FIFO, multiple read ports may initiate read requests simultaneously. By performing bit-by-bit comparison, the address comparison operation of each read port can be processed in parallel, allowing each read port to independently and quickly find the corresponding write data, thereby supporting concurrent read and write operations on multiple ports and improving the data processing efficiency of the FIFO.

In an optional embodiment of the present application, the method of selecting target data from a register file or write port data through a multiplexer according to the target address includes the following method steps:

When the target address is the current read address, the current read register file data corresponding to each read port is selected from the register file as the target data;

When the target address is a write data address, data corresponding to the write data address is selected from the write port data as the target data.

As an implementable manner, if the target address is a current read address, corresponding current read register file data is directly selected from the register file according to the current read address as the target data.

As another possible implementation method, when the target address is a write port address, the selection signal generated by the current read address and the write data address can be used to select the corresponding write port data as the target data through the multiplexer MUX and send it to the input port (port (1-N)_data_nxt) of the DFF register.

For example, when the selection signal indicates that the write port data of write port 3 is selected, the N-to-1 MUX will output the write port 3 data wport3_data to the corresponding position in the input port port(1-N)_data_nxt of the register, and the data of other write ports will be ignored.

After receiving the data from the DFF input port, a 2-to-1 multiplexer (MUX) is used to determine the current read FIFO data (rport(1-N)_data_nxt). This 2-to-1 selection typically involves selecting between data directly read from the register file (rport(1-N)_data_reg) and data from the write port (port(1-N)_data_nxt) after selection by the N-to-1 MUX. This selection can be based on other conditions, such as the FIFO status. For example, if the FIFO is not empty and there is no read/write conflict (i.e., the data has been written to the register file), the 2-to-1 MUX selects the data read from the register file as the current read FIFO data. If a read/write conflict occurs (i.e., the data has not yet been written to the register file), the data from the write port after processing by the N-to-1 MUX is selected as the current read FIFO data, with the current read FIFO data being the target data.

In this embodiment, based on the target address, it is possible to accurately select whether to select the corresponding data from the register stack or the write port data, thereby improving the flexibility of data acquisition, ensuring that the correct data is selected at the right time, avoiding errors caused by data conflicts, and avoiding unnecessary data transmission and processing processes, thereby reducing data delays.

In an optional embodiment of the present application, the above method further includes:

When the FIFO is in an empty state and the write enable signal is valid, the data of each write port is assigned as the target data to each input port of the register.

When there is a stored data in the FIFO and the read enable signal is valid, the data of each write port is assigned to each input port of the register as the target data.

When there are two stored data in the FIFO and the read enable signal is valid, the data read from the FIFO is assigned to the first input port in the register as the target data, and the data of the other write ports are assigned to the remaining input ports of the register in sequence as the target data; the other write ports refer to all the write ports except the first write port.

When there are n stored data in the FIFO and the read enable signal is valid, the data read from the FIFO is assigned as the target data to the first n-1 input ports of the register in sequence, and the data written to the port is assigned as the target data to the last input port of the register, n≥1.

Specifically, in a multi-port synchronous FIFO, the rules for updating the data at the register (DFF) input port can be selected based on the different states of the FIFO, the existing storage items (empty, with different numbers of storage items), and the read and write operations. The rules include the following specific contents.

As an optional implementation, when the FIFO is empty and there is a write operation to update the data at the DFF input port, it can be represented by the following text structure:

condi = empty&wen

rdata_nxt_p1 = wdata_p1;

rdata_nxt_p2 = wdata_p2;

...

rdata_nxt_pn = wdata_pn;

It should be noted that the above text structure indicates that the data on the DFF input port is updated only when the FIFO is empty (the empty signal is active) and write is enabled (the wen signal is active). This means that when there is no data in the FIFO and new data is to be written, the subsequent DFF data update operation is triggered. During the data update process, the data from each write port (wdata_p1-wdata_pn) is assigned to the corresponding DFF input port (rdata_nxt_p1-rdata_nxt_pn). That is, the data wdata_p1 from write port 1 is assigned to the data rdata_nxt_p1 of the first input port 1 in the DFF, the data wdata_p2 from write port 2 is assigned to the data rdata_nxt_p2 of the second input port 2 in the DFF, and so on. The data wdata_pn from write port n is assigned to the data rdata_nxt_pn of the last input port n in the DFF. The purpose of this is that when the FIFO is empty, if there is a write operation, the newly written data is directly prepared as the data that can be read at the next moment, and the data is transferred and prepared in advance.

As another optional implementation, when there is one storage item in the FIFO and a read operation updates the data at the DFF input port, it can be represented by the following text structure:

condi = 1entry&ren

rdata_nxt_p1 = wdata_p1;

rdata_nxt_p2 = wdata_p2;

...

rdata_nxt_pn = wdata_pn;

It should be noted that the above text structure indicates that this condition holds true when there is only one entry in the FIFO (the 1entry signal is active) and the read enable signal (the ren signal is active). That is, when there is only one entry in the FIFO and a read request is received, the DFF data must be updated. During the data update process, the data from each write port is assigned to the corresponding DFF input port. Specifically, data from write port 1 (wdata_p1) is assigned to the data on the first input port 1 of the DFF (rdata_nxt_p1), data from write port 2 (wdata_p2) is assigned to the data on the second input port 2 of the DFF (rdata_nxt_p1), and so on. Data from write port n (wdata_pn) is assigned to the data on the last input port n of the DFF (rdata_nxt_pn). This is because when there is only one entry in the FIFO and a read operation is required, the newly written data may need to be prepared in advance to meet continuous reading and writing requirements and avoid data transmission delays.

As another optional implementation, when the FIFO has two storage items and the data at the DFF input port is updated during a read operation, the following text structure can be used to represent it:

condi = 2entry&ren

rdata_nxt_p1 = fifo_r;

rdata_nxt_p2 = wdata_p1;

...

rdata_nxt_pn = wdata_pn;

It should be noted that the above text structure indicates that the DFF input port data is updated only when there are two entries in the FIFO (the 2entry signal is active) and the read enable is active (the ren signal is active). During the data update process, the data on the first input port, rdata_nxt_p0, is assigned to fifo_r, which represents the data read from the FIFO. The other ports (rdata_nxt_p1-rdata_nxt_pn) continue to be assigned to the data on the write ports (wdata_p1-wdata_pn). Specifically, the data read from the FIFO, fifo_r, is assigned to the data on the first input port, rdata_nxt_p1, on the DFF. The data on write port 1, wdata_p1, is assigned to the data on the second input port, rdata_nxt_p2, on the DFF. Finally, the data on write port n, wdata_pn, is assigned to the data on the last input port, rdata_nxt_pn, on the DFF. This may be because when there are two data in the FIFO, the first reading port can read the data directly from the FIFO, while other ports may need to wait for the newly written data or process the data in a specific order.

As another optional implementation, when the FIFO has N storage items and the data at the DFF input port is updated during a read operation, the following text structure can be used to represent it:

condi = Nentry&ren

rdata_nxt_p1 = fifo_r;

rdata_nxt_p2 = fifo_r;

...

rdata_nxt_pn = wdata_pn;

It should be noted that the above text structure indicates that the DFF input data is updated only when there are N items in the FIFO (the Nentry signal is active) and the read enable is active (the ren signal is active). During the data update process, the data from the first n-1 DFF input ports (rdata_nxt_p1 - rdata_nxt_p(n - 1)) is assigned to fifo_r, which is the data read from the FIFO. The last input port n (rdata_nxt_pn) is assigned to the data from the write port (wdata_pn). That is, the data read from the FIFO (fifo_r) is assigned to the data of the first DFF input port 1 (rdata_nxt_p1). The data read from the FIFO (fifo_r) is assigned to the data of the second DFF input port 2 (rdata_nxt_p2), and so on. Finally, the data from write port n (wdata_pn) is assigned to the data of the last DFF input port n (rdata_nxt_pn). This is based on the storage situation and read-write rules of the FIFO. The first n-1 input ports can directly read existing data from the FIFO, while the last input port needs to prepare newly written data to ensure data continuity and correctness.

In this embodiment, the data of the DFF input port can be reasonably selected and updated according to the different states and read and write operations of the FIFO, ensuring that the read and write operations of the data in the FIFO can be performed efficiently and accurately, eliminating the combinational logic delay of the output data.

It should be understood that, although the various steps in the flowchart are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps may be performed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. The execution order of these sub-steps or stages is not necessarily to be performed in sequence, but may be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

On the other hand, the present application also provides a multi-port synchronous FIFO data reading device, as shown in FIG6 , which includes:

The acquisition module 810 is used to obtain the read enable signal corresponding to each read port and the current status information of the FIFO when multiple read ports trigger corresponding data read requests in parallel; the read enable signal is used to indicate whether the read port performs a read operation;

The determination module 820 is used to determine the target address for each read port according to the read enable signal and the current state information of the FIFO; the target address is used to represent the identifier of the data read address;

The selection module 830 is used to select target data from the register file or the write port data through the multiplexer according to the target address; the write port data refers to the data currently being written into the FIFO;

The reading module 840 is used to perform a beat operation on the target data through a register and perform a read operation through a multi-port synchronous FIFO data reading interface.

Each module in the multi-port synchronous FIFO data reading device can be implemented in whole or in part through software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

The multi-port synchronous FIFO data reading device provided in the embodiment of the present application can determine the target address in advance based on the read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck in the downstream long combinational logic, and further improving the overall operation speed and performance of the system.

On the other hand, the present application also provides a multi-port synchronous FIFO data reading system, as shown in Figure 7. The system includes: a register stack, multiple multiplexers, multiple registers, multiple read pointers, and multiple read ports. Each multiplexer establishes a communication connection with the corresponding register, and the data reading interface establishes a communication connection with each register and each read pointer respectively.

Each read pointer is used to: when multiple read ports trigger corresponding data read requests in parallel, obtain the read enable signal corresponding to the read port and the current status information of the FIFO and send them to the corresponding multiplexer; the read enable signal is used to indicate whether the read port performs a read operation; each multiplexer is used to: for each read port, determine the target address based on the read enable signal and the current status information of the FIFO; based on the target address, select the target data from the register stack or the write port data; the target address is used to represent the identifier of the data read address; the write port data refers to the data currently being written to the FIFO; each register is used to: perform a beat operation on the target data and transmit the target data to the data read interface; the data read interface is used to: perform a read operation on the target data.

Specifically, the register file is used to store data and is the core part of the multi-port synchronous FIFO for storing data. It has multiple ports, including multiple write ports (wports) and multiple read ports (rports), which can realize parallel read and write operations.

The system may further include multiple comparison logic modules (Compare Logic). For example, N comparison logic modules may be Compare Logic 1, Compare Logic 2, ..., Compare Logic N. These modules are configured to compare relevant signals, such as a write pointer and a read pointer, to determine a FIFO (first-in-first-out) queue status, such as full or empty.

The above system may also include multiple read pointers. For example, N read pointers (read pointer 1, read pointer 2, ..., read pointer N) are controlled for updating by N read enable signals (RE), such as read enable signal 1 (RE1), read enable signal 2 (RE2), ..., and read enable signal N (REN). Each read pointer indicates the location from which data is read from the register file. The system may also include multiple write pointers. For example, N write pointers (write pointer 1, write pointer 2, ..., write pointer N) are controlled for updating by N write enable signals (WE), such as write enable signal 1 (WE1), write enable signal 2 (WE2), ..., and write enable signal N (WEN). Each write pointer indicates the location from which data is written to the register file.

The multiplexers MUX are used to determine a target address according to a read enable signal and current status information of the FIFO, and select target data from a register file or write port data according to the target address.

The above-mentioned multiple registers are, for example, N DFFs, such as register 1 (DFF1), register 2 (DFF2), register N (DFFN). Each register performs a beat operation on the target data and sends it to the data read interface, so that a read operation is performed through the data read interface.

During a write operation, the write port (wport) receives the write enable signal (WEN), the write pointer (write pointer), and the write data (wport_data). After processing, the data is written to the register file. When the write enable signal is active, the clock is used to store the data at the corresponding address. During a read operation, the read port (rport) has its own read pointer (read pointer). After comparison logic processing, the multiplexer selects the data (rport_data) to be read from the register file and output. Each read port can perform read operations independently.

Optionally, the system also features state detection. When write operations are frequent and the write pointer catches up to the read pointer to a certain extent, the comparison logic outputs a full signal after judgment, indicating that there is no free space in the register stack, which represents a full state. If the read operation is faster than the write operation, the read pointer and the write pointer are equal and meet specific conditions, the comparison logic outputs an empty signal, indicating that there is no valid data to read, that is, the state is empty. Among them, valid is used to indicate the validity of the data, and ready is used to indicate the readiness status of these signals and ports, helping to coordinate read and write operations.

The data reading system of the multi-port synchronous FIFO provided in the embodiment of the present application can determine the target address in advance based on the read enable signal and the current status information of the FIFO when multiple read ports trigger data read requests in parallel, so that the corresponding target data can be directly selected from the register stack or write port data, avoiding the large MUX delay problem caused by the increase in FIFO depth in traditional designs, and performing a beat operation according to the target data through the register to read through the data read interface, alleviating the timing bottleneck in the downstream long combinational logic, and further improving the overall operation speed and performance of the system.

In one embodiment, a computer device is provided, and the internal structure diagram of the computer device can be shown in Figure 3. The computer device includes a processor, a memory, a network interface and a database connected via a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer program is executed by the processor, it implements a multi-port synchronous FIFO data reading method as described above. It includes: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it implements any step in the multi-port synchronous FIFO data reading method as described above.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step in the above multi-port synchronous FIFO data reading method can be implemented.

Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

This application is described with reference to the flowcharts and/or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the application. It should be understood that each process and/or block in the flowchart and/or block diagram, as well as the combination of processes and/or blocks in the flowchart and/or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate a device for implementing the functions specified in one or more processes in the flowchart and/or one or more blocks in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims (9)

1. A method for multi-port synchronous FIFO data reading, the method comprising:

When a plurality of reading ports trigger corresponding data reading requests in parallel, acquiring a reading enabling signal corresponding to each reading port and current state information of the FIFO;

For each reading port, determining a target address according to the reading enabling signal and the current state information of the FIFO, wherein when the current state information of the FIFO is in a full state, generating a corresponding current beat reading address according to the reading enabling signal, and taking the current beat reading address as the target address; when the current state information of the FIFO is in an empty state and a data writing request trigger corresponding to a writing port is detected, determining a writing port address according to the reading enabling signal and taking the writing port address as the target address, wherein the target address is used for representing the identification of a data reading address;

selecting target data from a register file or write port data through a multiplexer according to the target address, wherein the write port data refers to data which is currently written into the FIFO;

and inputting the target data into a register through an input port to execute beat operation and executing read operation through a data read interface corresponding to the FIFO.

2. The method of claim 1, wherein when the current status information of the FIFO is in a null state and a data write request trigger corresponding to a write port is detected, generating a corresponding target address according to the read enable signal comprises:

when the current state information of the FIFO is in an empty state, a data reading request corresponding to the reading port and a data writing request corresponding to the writing port occur simultaneously, and the number of the reading port and the number of the writing port are the same, determining the current beat reading address of each reading port according to the reading enabling signal;

Acquiring the current existing write data address of the FIFO;

And comparing logic judgment is carried out according to the current beat reading address and the write data address of each reading port, the target address is selected from the data of all writing ports, and the write data address is used for representing the current existing data address of the FIFO.

3. The method of claim 2, wherein selecting the target address from the data of all write ports based on the comparison logic determination of the read-while address and the write data address for each read port comprises:

Comparing the current beat address of each read port with the write data address according to the bits to obtain a comparison result, wherein the comparison result is used for representing whether the current beat address is consistent with the write data address or not;

and if the beat-read address is consistent with the write data address, taking the write data address as the target address.

4. The method of claim 2, wherein selecting target data from the register file or the write port data via the multiplexer according to the target address comprises:

When the target address is the read-while address, selecting read-while register file data corresponding to each read port from the register file as the target data;

When the target address is the write data address, selecting data corresponding to the write data address from the write port data as the target data.

5. The method of claim 1, wherein the register comprises a plurality of input ports, the method further comprising:

When the FIFO is in an empty state and a write enable signal is valid, data of each write port are respectively assigned to each input port of the register as target data;

When one of the FIFO stores data and a read enable signal is valid, the data of each write port is used as target data to be respectively assigned to each input port of the register;

When two storage data exist in the FIFO and a read enabling signal is valid, the data read from the FIFO are used as target data to be assigned to a first input port in the register, and the data of other write ports are used as target data to be sequentially assigned to other input ports of the register, wherein the other write ports refer to write ports except the first write port in all write ports;

when n pieces of storage data exist in the FIFO and a reading enabling signal is effective, the data read from the FIFO are sequentially assigned as target data to be the first n-1 input ports in the register, the data of the writing port are assigned as target data to be the last input port of the register, and n is more than or equal to 1.

6. A multi-port synchronous FIFO data reading device, the multi-port synchronous FIFO data reading device comprising:

The system comprises an acquisition module, a reading enabling signal acquisition module and a reading control module, wherein the acquisition module is used for acquiring a reading enabling signal corresponding to each reading port and current state information of a FIFO (first in first out) when a plurality of reading ports trigger corresponding data reading requests in parallel;

The determining module is used for determining a target address according to the read enabling signal and the current state information of the FIFO for each read port, and comprises the steps of generating a corresponding read-in address according to the read enabling signal when the current state information of the FIFO is in a full state and taking the read-in address as the target address;

the selection module is used for selecting target data from a register file or write port data through a multiplexer according to the target address, wherein the write port data refers to data which is currently written into the FIFO;

and the reading module is used for executing beat operation on the target data through a register and executing reading operation through the multi-port synchronous FIFO data reading interface.

7. The multi-port synchronous FIFO data reading system is characterized by comprising a register file, a plurality of multiplexers, a plurality of registers, a plurality of read pointers, a plurality of read ports and a data reading interface, wherein each multiplexer is in communication connection with the corresponding register, and the data reading interface is respectively in communication connection with each register and each read pointer;

each reading pointer is used for acquiring a reading enabling signal corresponding to a plurality of reading ports and the current state information of the FIFO and sending the reading enabling signal and the current state information to a corresponding multiplexer when the corresponding data reading requests are triggered by the plurality of reading ports in parallel;

Each multiplexer is used for determining a target address according to the read enabling signal and the current state information of the FIFO for each read port, and comprises the steps of generating a corresponding read-in address according to the read enabling signal when the current state information of the FIFO is in a full state and taking the read-in address as the target address, determining a write port address according to the read enabling signal and taking the write port address as the target address when the current state information of the FIFO is in an empty state and a data write request trigger corresponding to the write port is detected, selecting target data from a register file or write port data according to the target address, wherein the target address is used for representing the identification of a data read address, the write port data refers to the data currently being written into the FIFO, and the target address is used for representing the identification of the data read address;

Each register is used for executing beat operation on the target data and transmitting the target data to the data reading interface;

the data reading interface is used for executing reading operation on the target data.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the multi-port synchronous FIFO data reading method of any of claims 1 to 5.

9. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the steps of the multi-port synchronous FIFO data reading method of any of claims 1 to 5.