CN120045494A

CN120045494A - Automatic branching method and system for PCIe (peripheral component interconnect express)

Info

Publication number: CN120045494A
Application number: CN202311524456.3A
Authority: CN
Inventors: 李�浩
Original assignee: Sanechips Technology Co Ltd
Current assignee: Sanechips Technology Co Ltd
Priority date: 2023-11-14
Filing date: 2023-11-14
Publication date: 2025-05-27

Abstract

An embodiment of the present invention provides a PCIe automatic branching method and system, the method comprising: for each backplane connected to a baseboard management controller BMC and the transmission bus used, obtaining the backplane identifier of the backplane where each PCIe device is located and the number of the transmission bus used, determining the channel splitting configuration information of each PCIe interface for use by a basic input and output system BIOS according to the obtained backplane identifier and the number of the transmission bus, thereby solving the problem in the related art that the BIOS sets the wrong channel splitting configuration information of the PCIe interface and the need to release a new version of the BIOS when facing a new application scenario, which increases the difficulty of BIOS maintenance, improves the correctness of the branching mode of the PCIe interface set by the BIOS, and reduces the difficulty of system and BIOS maintenance.

Description

Automatic branching method and system for PCIe (peripheral component interconnect express)

Technical Field

The embodiment of the invention relates to the field of computers, in particular to an automatic branching method and system for PCIe (peripheral component interconnect express).

Background

In the server device, the processor and the peripheral device are connected through a peripheral device interconnect expansion bus (PERIPHERAL COMPONENT INTERCONNECT EXPRESS, abbreviated as PCIe). One processor typically has multiple standard PCIe interfaces for connecting different devices, such as Solid state drives (Solid STATE DRIVE, SSD), graphics cards, network cards, data processing units (Data Processing Unit, DPU), and the like.

A standard PCIe interface typically has 16 lanes (lanes) that can be used to connect different PCIe devices simultaneously. To achieve this, a Basic Input/Output System (BIOS) is required to set channel splitting information (PCIe Bifurcation) of the PCIe interface, and divide 16 lanes of the PCIe interface into different communication channels to connect different PCIe devices.

In the prior art, a single BIOS firmware image is used to support different computer systems, in which image PCIe Bifurcation configurations of the different systems are stored to accommodate the hardware design associated with each system. A mapping table is typically provided in the BIOS in which the corresponding PCIe Bifurcation configurations of the different systems are recorded. When the BIOS is powered on, the system type is detected and the correct PCIe Bifurcation is set according to the mapping table. If the BIOS sets the error PCIe Bifurcation, it may cause the system to fail to use the PCIe device installed on the system or cause the PCIe device to run down.

When the server processor is used for 2 different application scenarios and is external to different PCIe devices, it can be considered as 2 different systems. To ensure proper operation of the system, it is necessary to first identify the current system and provide the corresponding correct PCIe Bifurcation settings based on the system. In more and more complex scenarios, this process may result in the BIOS setting up the wrong PCIe Bifurcation configuration, thereby negatively impacting the functionality and performance of the system. In addition, every time a new application scenario occurs, a new version of BIOS needs to be released to support PCIe Bifurcation changes. These potential variations increase the maintenance difficulty of the system and the BIOS itself.

Aiming at the problem that the BIOS setting error PCIe Bifurcation in the related technology and the problem that the BIOS of a new version needs to be released when a new application scene is faced, the difficulty of BIOS maintenance is increased, and no solution is proposed.

Disclosure of Invention

The embodiment of the invention provides an automatic branching method and an automatic branching system for peripheral equipment interconnection expansion bus PCIe, which at least solve the problems that BIOS (basic input output system) setting errors PCIe Bifurcation in the related art and the difficulty of BIOS maintenance is increased due to the fact that a new version of BIOS needs to be released when a new application scene is faced.

According to one embodiment of the present invention, there is provided an automatic branching system for peripheral component interconnect express bus PCIe, including:

The processor is provided with one or more PCIe interfaces and is connected with one or more PCIe devices through the PCIe interfaces; one or more backplates, each of which is configured with a backplate identifier and is used for identifying the maximum link width supported by PCIe devices plugged on the backplate, and each PCIe device is plugged on a corresponding backplate;

The BMC is connected with the backboard inserted with the PCIe device through transmission buses, each transmission bus is provided with a number and is connected to a corresponding backboard in the backboard, a preset corresponding relation exists between the number of each transmission bus and a PCIe interface connected with the PCIe device inserted with the corresponding backboard, the BMC obtains a backboard identifier of the backboard inserted with the PCIe device and the number of the used transmission bus, and channel splitting configuration Bifurcation information of each PCIe interface is determined according to the obtained backboard identifier and the number of the transmission bus so as to be used by a basic input/output system BIOS.

In one exemplary embodiment, determining the channel split configuration Bifurcation information for each PCIe interface according to the acquired backplane identification and the number of the transport bus includes:

For each backboard connected with the BMC and the used transmission bus, the BMC determines the maximum link width supported by the PCIe equipment inserted on the backboard according to the acquired backboard identification, and determines the PCIe interface connected with the PCIe equipment according to the acquired serial number of the transmission bus and the preset corresponding relation between the serial number of the transmission bus and the PCIe interface;

And determining Bifurcation information of each PCIe interface according to the maximum link width supported by each PCIe device connected with each PCIe interface.

In an exemplary embodiment, the system further comprises:

The memory is used for storing Bifurcation information of each PCIe interface set by the BMC;

The BIOS is connected with the processor and is used for reading the Bifurcation information in the memory and setting a branch mode of the PCIe interface in the processor according to the Bifurcation information.

In an exemplary embodiment, the processor is one of a central processing unit CPU, a data processing unit DPU, a graphics processing unit GPU.

In an exemplary embodiment, the transmission bus is one of a serial bi-directional communication interface bus I2C, a serial peripheral interface bus SPI, a universal asynchronous transfer bus URAT.

According to another embodiment of the present invention, there is provided an automatic branching method for peripheral component interconnect express bus PCIe, which is applied to any one of the above-mentioned automatic branching system embodiments, and includes:

For each backboard connected with the BMC and a transmission bus used, obtaining a backboard identification of the backboard where each PCIe device is located and a serial number of the transmission bus used;

And determining Bifurcation information of each PCIe interface according to the acquired backboard identification and the serial number of the transmission bus for the BIOS of the basic input/output system.

In an exemplary embodiment, after determining Bifurcation information of each PCIe interface according to the acquired backplane identifier and the number of the transmission bus, the method further includes:

storing the Bifurcation information to a memory;

And reading the Bifurcation information in the memory through a BIOS, and setting a branch mode of each PCIe interface in the processor according to the Bifurcation information.

In an exemplary embodiment, determining Bifurcation information of each PCIe interface according to the acquired backplane identification and the number of the transmission bus includes:

Determining the maximum link width supported by PCIe equipment plugged in each backboard according to the acquired backboard identification, and determining the PCIe interface connected with the PCIe equipment according to the acquired transmission bus number and the preset corresponding relation between the transmission bus number and each PCIe interface;

In one exemplary embodiment, before the number of the transmission bus used by each PCIe device is obtained, the method further includes:

and setting the corresponding relation between the PCIe interface and the serial numbers of the transmission buses.

In one exemplary embodiment, before obtaining the backplane identifier of the backplane where each PCIe device is located, the method further includes:

And setting the corresponding relation between the maximum link width supported by the PCIe equipment and the backboard identification.

According to a further embodiment of the invention, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In the above embodiment of the present invention, by establishing the correspondence between the backplane ID and the type of PCIe device plugged on the PCIe interface of the CPU and establishing the correspondence between the transmission bus number of the PCIe device and the plugged PCIe interface, the BMC may perform correct PCIe Bifurcation configuration on the PCIe interface of the CPU based on the plugged PCIe device, which avoids the problem that in the related art, setting PCIe Bifurcation according to the mapping table may cause a BIOS setting error and when a new application scenario is faced, the BIOS needs to issue a new version of BIOS, which increases the difficulty of BIOS maintenance, improves the correctness of the branch mode of the PCIe interface set by the BIOS, and reduces the difficulty of system and BIOS maintenance.

Drawings

FIG. 1 is a block diagram of an automatic branching system for peripheral component interconnect expansion bus PCIe, according to an embodiment of the present invention;

FIG. 2 is a flow chart of an automatic branching method for peripheral component interconnect expansion bus PCIe, according to an embodiment of the present invention;

FIG. 3 is a flowchart of an embodiment of an automatic branching system implementation of peripheral component interconnect expansion bus PCIe, according to the present invention.

Detailed Description

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

In the existing server device, a CPU and a peripheral device are connected through PCIe, one CPU usually has multiple standard PCIe interfaces for connecting to devices such as SSDs, graphics cards, network cards, DPUs, etc., one standard PCIe interface usually has 16 lanes, one standard PCIe interface may be used for connecting to different PCIe devices at the same time, and the PCIe 16 lanes need to be split into different communication channels through BIOS settings PCIe Bifurcation to connect to different PCIe devices.

In order to solve the problem that may cause the BIOS to set up wrong PCIe Bifurcation configurations in a complex scenario, the present invention provides an implementation of PCIe auto-branching in the following embodiments.

Example 1

According to an embodiment of the present invention, there is provided an automatic branching system for a peripheral component interconnect expansion bus PCIe, and fig. 1 is a block diagram of the automatic branching system for a peripheral component interconnect expansion bus PCIe according to an embodiment of the present invention, as shown in fig. 1, including:

A processor 101, providing one or more (only two are shown in FIG. 1) PCIe interfaces 108a and 108b, through which PCIe interface 108b one or more (only two are shown in FIG. 1) PCIe devices 102a and 102b are connected (only one PCIe interface is shown in FIG. 1 connected to 2 PCIe devices);

One or more backplanes (only two are shown in fig. 1) 103a and 103b, where the two backplanes 103a and 103b have an identifier (e.g., 1 and 0) thereon, where the identifier is used to identify a maximum link width supported by a PCIe device plugged onto the backplanes, the PCIe devices 102a and 102b plug onto the backplanes 103a and 103b, obtain the identifiers of the backplanes 103a and 103b and the numbers of the transmission buses 104a and 104b, determine channel split configuration information of the PCIe interface 108b according to the obtained identifiers of the backplanes 103a and 103b and the numbers of the transmission buses 104a and 104b, and store the channel split configuration information of the PCIe interface 108b in a memory 109 for use by the BIOS107, where the memory 109 is connected to the BMC106 and the BIOS107, respectively.

In this embodiment, by establishing a correspondence between the backplane ID and the type of PCIe device plugged on the PCIe interface of the CPU and establishing a correspondence between the transmission bus number of the PCIe device and the plugged PCIe interface, the BMC may perform correct PCIe Bifurcation configuration on the PCIe interface of the CPU based on the plugged PCIe device.

In one exemplary embodiment, determining the lane splitting configuration information of the PCIe interface 108b based on the identification of the backplanes 103a and 103b and the number of the transport buses 104a and 104b includes:

The BMC 106 determines, according to the acquired backplane identifier (e.g. 0) of the backplane 103a, a maximum link width (e.g. x 8) supported by the PCIe device 102a plugged into the backplane 103a, and determines, according to the acquired transmission bus number (e.g. 1 a) and the preset correspondence between the transmission bus number and the PCIe108b interface, that the PCIe interface connected to the PCIe device 102a is PCIe108b. Similarly, the BMC 106 determines, according to the acquired backplane identifier (e.g. 1) of the backplane 103b, a maximum link width (e.g. x 4) supported by the PCIe device 102b plugged into the backplane 103b, and determines, according to the acquired transmission bus number (e.g. 1 b) and the preset correspondence between the transmission bus number and the PCIe108b interface, that the PCIe interface connected to the PCIe device 102b is the PCIe interface 108b.

The lane splitting configuration information (x8+x4+x4) for the PCIe interface 108 is determined based on the maximum link widths (e.g., x8, x 4) supported by the PCIe devices 102a, 102b to which the PCIe interface 108 is connected.

In an exemplary embodiment, the memory 109 is configured to store channel split information of the PCIe interfaces 108a and 108b configured by the BMC 106. That is, the BMC106 outputs a different PCIe Bifurcation to memory 109 and to BIOS for use, eliminating the need for BIOS to fetch PCIe Bifurcation from the back of the mapping table, and reducing the likelihood of configuration errors resulting in PCIe devices being disabled or running at reduced speeds.

In an exemplary embodiment, the BIOS107 is coupled to the processor 101 and configured to read the channel split information in the memory 109 and set a branching mode of the PCIe interface in the processor 101 according to the channel split information.

In an exemplary embodiment, the processor 101 may be a central processing unit (Central Processing Unit, CPU for short), a data processing unit (Data Processing Unit, DPU for short), DPU, or graphics processing unit (Graphics Processing Unit, GPU for short).

In an exemplary embodiment, the transmission buses 104a and 104b may employ, for example, a serial bi-directional communication interface bus (Inter-INTEGRATED CIRCUIT, abbreviated as I2C), a serial peripheral interface bus (SERIAL PERIPHERAL INTERFACE, abbreviated as SPI), or a universal asynchronous transfer bus (Universal Asynchronous RECEIVER TRANSMITTER, abbreviated as URAT).

Example 2

According to another embodiment of the present invention, there is provided an automatic branching method for a peripheral component interconnect expansion bus PCIe, which is applied to any one of the above-mentioned automatic branching system embodiments, and fig. 2 is a flowchart of an automatic branching method for a peripheral component interconnect expansion bus PCIe according to an embodiment of the present invention, as shown in fig. 2, the flowchart includes the steps of:

In step S202, when the BMC 106 detects that the BMC 106 is connected to the backplane 103a, 103b to which the PCIe devices 102a, 102b are plugged, the BMC 106 obtains the backplane identifications of the backplane 103a, 103b where the PCIe devices 102a, 102b are located, and the numbers of the transmission buses 104a, 104b connected to the PCIe devices 102a, 102 b.

The BMC106, upon detecting that it is connected to the backplanes 103a and 103b, includes the BMC acquiring signals from the backplanes 103a and 103b via the transport buses 104a, 104 b.

In step S204, the BMC 106 sets the channel splitting information of the PCIe interface 108b according to the obtained identifications of the backplanes 103a and 103b and the numbers of the transmission buses 104a and 104 b.

Specifically, the maximum link widths supported by the PCIe devices 102a and 102b are determined according to the backplane 103a and 103b identifications, respectively, and the PCIe interfaces 108b to which the PCIe devices 102a and 102b are connected are determined according to the numbers of the transport buses 104a and 104b, respectively.

For example, the BMC 106 may determine that the maximum link widths supported by the PCIe devices 102a and 102b are x8 and x4, respectively, based on the backplane identification, and determine that the PCIe devices 102a and 102b are both plugged onto the PCIe interface 108b based on the transport bus number, and thus the BMC 106 may configure the lane splitting information of the PCIe interface 108b as x8 +x4.

The relationship between the maximum link widths supported by 102a and 102b and the channel split configuration information of the PCIe interface 108b is shown in table 1:

TABLE 1

In step S206, the channel split information is stored in the memory 109 for use by the BIOS107, and the memory 109 is connected to the BMC106 and the BIOS107, respectively. For example, the channel split information x8+x4+x4 of the PCIe interface 108b is saved to the memory 109, so that the BIOS does not need to fetch PCIe Bifurcation from the back of the mapping table, and configuration errors are reduced.

In an exemplary embodiment, step 208 is further included:

In step S208, after the processor is powered on, the BIOS107 reads the channel splitting information in the memory 109, and sets a PCIe branch mode in the processor 101 according to the channel splitting information, so that PCIe devices plugged on the PCIe interface may work normally. For example, the BIOS may set the branch mode of PCIe interface 108b to x8+x4+x4 in the process based on the channel split information x8+x4+x4 stored in memory 109.

In this embodiment, before executing step S202, a correspondence between the PCIe interface and the serial number of the transmission bus and a correspondence between the maximum link width supported by the PCIe device and the backplane identifier may be preset.

FIG. 3 is a flowchart of an embodiment of an automatic branching system implementation of peripheral component interconnect expansion bus PCIe, according to the present invention. As shown in fig. 3, includes:

Step S300, setting a corresponding relation between the PCIe interface and the serial numbers of the transmission buses, wherein the corresponding relation can be that the transmission bus of PCIe108a is set to 0a/0b/0c/0d, the serial numbers of the transmission buses of PCIe108b are set to 1a/1b/1c/1d, and the serial numbers of the Lane0-Lane3, lane4-Lane7, lane8-Lane11 and Lane12-Lane15 sequentially correspond to PCIe108 a/b;

Setting a corresponding relation between the maximum link width supported by the PCIe equipment and the backboard identification, wherein the corresponding relation can be that the maximum link width x8 supported by the PCIe equipment is correspondingly spliced at the backboard number 1 of the equipment, and the maximum link width x4 supported by the PCIe equipment is correspondingly spliced at the backboard number 0 of the equipment;

In this embodiment, when two PCIe devices 102a and 102b (the maximum link widths are x8 and x4 respectively) are externally connected to the processor, the backplanes with different numbers are selected according to the maximum link widths of the PCIe devices, the PCIe device 102a is plugged into the backplane with the backplate number 1, the PCIe device 102b is plugged into the backplane with the backplate number 0, the transmission buses with different numbers are selected according to the connected PCIe interfaces, the two PCIe devices are connected to the PCIe interface 108b, and the two transmission buses with the numbers 1a and 1b are selected to connect the two PCIe devices with the BMC 106. The BMC106, upon detecting that it is connected to the backplanes 103a and 103b, includes the BMC acquiring signals from the backplanes 103a and 103b via the transport buses 104a, 104 b.

Step S302, determining that the maximum link widths supported by the PCIe devices 102a, 102b are x8 and x4 according to the back plane 103a, 103b identifiers (1 and 0), and determining that the PCIe interfaces to which the PCIe devices 102a, 102b are connected are PCIe interfaces 108b according to the serial numbers (1 a and 1 b) of the transmission buses 104a, 104 b;

in step S304, the channel splitting information of the PCIe interface 108b is set to be x8+x4+x4 according to the maximum link widths x8 and x4 supported by the PCIe devices 102a and 102b and the PCIe interface 108 b.

In step S306, the channel split information is stored in the memory 109 for use by the BIOS107, and the memory 109 is connected to the BMC106 and the BIOS 107.

In step S308, after the processor is powered on, the BIOS107 fetches the channel splitting information in the memory 109 and sets the branch mode of the PCIe interface in the processor.

In the above embodiment of the present invention, each peripheral is plugged into a backplane, the ID of each backplane is different, each backplane communicates with the BMC through I2C, the BMC can determine the device that is X4/X8/X16 according to the ID of the backplane, the BMC can determine which group of X16 interfaces the backplane is plugged into according to the I2C number, and finally, each group of standard PCIe interfaces is set to a correct branching mode in the BIOS stage;

The corresponding relation between the PCIe interfaces and the number of PCIe devices is shown in table 2:

TABLE 2

As can be seen from table 2, in the table corresponding to the embodiment, when the maximum link width supported by the N PCI devices is (x 8, x 4), the PCIe interface connected to the transmission bus number (1 a, 1 b) is PCIe108b, and the channel splitting information of the PCIe108b interface is (x8+x4+x4). Compared with the prior art, the technical scheme provided by the invention is very flexible to use, the BIOS of a new version is released to adapt to PCIe Bifurcation changes because of the changes of the external PCIe equipment of the CPU of the server, in addition, the BMC outputs different PCIe Bifurcation to the RAM of the CPLD and to the BIOS for use according to the changes of the external equipment of the CPU, the BIOS is not required to be taken out PCIe Bifurcation from the inner surface of the mapping surface, and the possibility that the PCIe equipment cannot be used or runs at a reduced speed due to configuration errors is also reduced.

Embodiments of the present invention also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An automatic branching system for a peripheral device interconnection expansion bus PCIe, characterized in that it includes:

A processor is provided with one or more PCIe interfaces and is connected to one or more PCIe devices through the PCIe interfaces;

One or more backplanes, each of which is configured with a backplane identifier and is used to identify the maximum link width supported by a PCIe device plugged into the backplane, and each of which is plugged into a corresponding backplane;

A baseboard management controller BMC is connected to the backplane to which the PCIe device is plugged through a transmission bus, each transmission bus is provided with a number and connected to a corresponding one of the backplanes, and there is a preset corresponding relationship between the number of each transmission bus and the PCIe interface to which the PCIe device plugged into its corresponding backplane is connected. The BMC obtains the backplane identifier of the backplane to which the PCIe device is plugged and the number of the used transmission bus, and determines the channel splitting configuration Bifurcation information of each PCIe interface according to the obtained backplane identifier and the number of the transmission bus for use by the basic input and output system BIOS.

2. The system according to claim 1, characterized in that it comprises:

For each backplane connected to the BMC and the transmission bus used, the BMC determines the maximum link width supported by the PCIe device plugged into the backplane according to the acquired backplane identifier, and determines the PCIe interface to which the PCIe device is connected according to the acquired number of the transmission bus and the preset correspondence between the number of the transmission bus and the PCIe interface;

Bifurcation information of each PCIe interface is determined according to the maximum link width supported by each PCIe device connected to each PCIe interface.

3. The system according to claim 1, characterized in that the system further comprises:

The memory is used to store the Bifurcation information of each PCIe interface set by the BMC;

The BIOS is connected to the processor and is used to read the Bifurcation information in the memory and set the branch mode of the PCIe interface in the processor according to the Bifurcation information.

4 . The system according to claim 1 , wherein the processor is one of the following: a central processing unit (CPU), a data processing unit (DPU), or a graphics processing unit (GPU).

5. The system according to claim 1 is characterized in that the transmission bus is one of the following: a serial bidirectional communication interface bus I2C, a serial peripheral interface bus SPI, and a universal asynchronous receiver-transmitter bus URAT.

6. An automatic branching method for a peripheral interconnection expansion bus PCIe, applied to an automatic branching system of PCIe, characterized in that the method comprises:

For each backplane connected to the BMC and the transmission bus used, obtain the backplane identifier of the backplane where each PCIe device is located and the number of the transmission bus used;

The Bifurcation information of each PCIe interface is determined according to the acquired backplane identifier and the number of the transmission bus for use by BIOS.

7. The method according to claim 6, characterized in that after determining the Bifurcation information of each PCIe interface according to the acquired backplane identifier and the number of the transmission bus, it also includes:

Storing the Bifurcation information in a memory;

The Bifurcation information in the memory is read through BIOS, and the branch mode of each PCIe interface is set in the processor according to the Bifurcation information.

8. The method according to claim 6, characterized in that determining the Bifurcation information of each PCIe interface according to the acquired backplane identifier and the number of the transmission bus comprises:

Determine the maximum link width supported by the PCIe device plugged into each backplane according to the acquired backplane identifier, and determine the PCIe interface to which the PCIe device is connected according to the acquired transmission bus number and the preset correspondence between the transmission bus number and each PCIe interface;

9. The method according to claim 7, characterized in that before obtaining the number of the transmission bus used, it also includes:

A corresponding relationship between the numbers of the PCIe interface and the transmission bus is set.

10. The method according to claim 7, characterized in that before obtaining the backplane identifier of the backplane where each PCIe device is located, it also includes:

The correspondence between the maximum link width supported by the PCIe device and the backplane identifier is set.

11. A computer-readable storage medium, characterized in that a computer program is stored in the storage medium, wherein the computer program is configured to execute the method described in any one of claims 6 to 10 when running.