CN120091561A - OTP device and preparation method thereof - Google Patents
OTP device and preparation method thereof Download PDFInfo
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- CN120091561A CN120091561A CN202510238533.1A CN202510238533A CN120091561A CN 120091561 A CN120091561 A CN 120091561A CN 202510238533 A CN202510238533 A CN 202510238533A CN 120091561 A CN120091561 A CN 120091561A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
- H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links
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Abstract
The invention provides an OTP device and a preparation method thereof, the OTP device comprises an active region and an X-direction active region extension part, the projection of the first contact hole on the substrate falls into the X-direction active region extension. The first contact hole is arranged at a position without the thickness superposition of the interlayer dielectric layers through the optimization of the active region and the first contact hole layout, the position is exactly a narrow crack formed by the interlayer dielectric layers covering two adjacent floating gates, and the narrow crack is not formed at the position without the floating gates covered by the interlayer dielectric layers. The first contact hole is designed in a Y-direction extending area of a gap neutral gear between two adjacent floating gates in the X direction, so that the crack position of the two adjacent floating gates in the Y direction is avoided, the first contact hole is of the same width up and down, the contact performance is optimized, the bit line contact resistance formed by filling a metal layer in the first contact hole is normal, and the performance of an OTP device is ensured. The first contact hole is not easy to form a cavity when the interlayer dielectric layer is filled, so that the first contact hole is ensured to be normal.
Description
Technical Field
The invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to an OTP device and a preparation method thereof.
Background
OTP (one time programmable) devices, i.e., one-time programmable devices, which are assigned to non-volatile memories, are not reversible in their programming process relative to multiple-time programmable devices (MTP), and are suitable for applications where the program is fixed. As the Floating Gate (FG) to floating gate spacing of the OTP is continually shrinking, e.g., less than 0.4 μm, the contact hole problem for the bit line develops. As shown in fig. 1, a deposited interlayer dielectric layer (e.g., a silicon nitride layer) covers the gaps between the floating gates and adjacent floating gates, the silicon nitride layer including a first portion of silicon nitride 01a covering the gaps between adjacent floating gates and a second portion of silicon nitride 01b covering the top and sidewalls of the floating gates. The lateral spacing between adjacent silicon nitride second portions 01b is only 0.13 μm at a Floating Gate (FG) to floating gate spacing of 0.47 μm, and the floating gate to floating gate spacing will be smaller in the future. The silicon nitride layer is a stop layer of a main etching part in the step of etching the contact hole, after the sum of the thicknesses of the first silicon nitride part 01a and the second silicon nitride part 01b, namely the vertical height reaches 1000 angstroms (normally only 400 angstroms), the contact hole etching at the gap between the adjacent second silicon nitride parts 01b cannot be etched to the bottom, so that poor contact is caused, the contact resistance is larger, and if the exposure and the alignment of the contact hole photoresist are offset, the contact hole is worse.
Fig. 2 is an ideal schematic diagram of etching the contact hole 02 of the OTP device, and fig. 3 is an actual schematic diagram of etching the contact hole 02 of the OTP device. As shown in FIG. 2, the contact hole 02 is etched vertically from the top to the substrate with the same width, but as shown in FIG. 3, the actual etching is that the adjacent silicon nitride second part 01b (the inner end of the red circle in FIG. 1) exists, and the thickness superposition of the silicon nitride layer in the vertical direction is larger than the pre-designed thickness, the effective contact width of the bottom of the contact hole 02 with the width of 0.16 μm is smaller than or equal to 0.13 μm, the bottom is narrowed, namely the contact hole 02 is wider up and narrower down, the contact area of the bottom of the contact hole 02 is reduced, so that the contact resistance of a bit line formed by filling a metal layer in the contact hole 02 is larger, the contact resistance is increased by about 30%, and the performance of the OTP device is affected. In addition, since the gaps between the adjacent silicon nitride second portions 01b are small, voids (filling voids) are easily formed at the gap positions when filling the oxide layer when forming the oxide layer covering the silicon nitride layer later, resulting in abnormality of the first contact holes.
Disclosure of Invention
The invention aims to provide an OTP device and a preparation method thereof, wherein a first contact hole is designed in a Y-direction extending area of a gap neutral gear between two adjacent floating gates in an X direction, and the crack position of the two adjacent floating gates in the Y direction is avoided, so that the first contact hole has the same width up and down, the contact performance of the first contact hole is optimized, the bit line contact resistance formed by filling a metal layer in the first contact hole is normal, and the performance of the OTP device is ensured. And meanwhile, the first contact hole is not easy to form a cavity when the interlayer dielectric layer is filled, so that the first contact hole is ensured to be normal.
The invention provides a preparation method of an OTP device, which comprises the following steps:
a substrate defining an X direction and a Y direction perpendicular to each other in a plane parallel to an upper surface of the substrate; the substrate is provided with a plurality of active areas which are arranged in parallel at intervals along the X direction, wherein the active areas extend out of Y-direction active area extending parts along the Y direction, and each Y-direction active area extending part extends out of X-direction active area extending parts along the X direction;
the floating gates are distributed in a one-to-one correspondence manner with the active areas, the projection of the floating gates on the substrate falls into the active areas, and the X-direction active area extension part is positioned at one side of the floating gates far away from the selection gates;
the interlayer dielectric layer covers the floating gate, the selection gate and the substrate;
The first contact holes penetrate through the interlayer dielectric layer to expose the substrate, a plurality of first contact holes are formed in the X direction at intervals and distributed in a one-to-one correspondence with the X-direction active area extending parts, projections of the first contact holes on the substrate fall into the X-direction active area extending parts, and the first contact holes are located in Y-direction extending areas of gap neutral gears between two adjacent floating gates in the X direction.
Further, a first metal layer is filled in the first contact hole, and a bit line is led out.
Further, a common active region extending along the X direction is formed in the substrate at one side of the selection gate far away from the floating gate, and the common active region is respectively connected with a plurality of active regions;
And a second contact hole is formed above the substrate, the projection of the second contact hole on the substrate falls into the public active area, a second metal layer is filled in the second contact hole, and a source line is led out.
The active region, the floating gate and the selection gate are distributed on two sides of the X-direction active region extension part in a mirror image mode in the Y direction;
The Y-direction active region extension portion is connected with the active regions located on two sides of the X-direction active region extension portion in the Y direction.
Further, a metal silicide is formed at a position where the first contact hole exposes the substrate, and the first metal layer is electrically connected with the metal silicide.
Further, a memory cell of the OTP device comprises the floating gate, the selection gate, the bit line and the source line, and oxide layers are formed between the floating gate and the substrate and between the selection gate and the substrate.
Further, the OTP device comprises a plurality of storage units, wherein the storage units in the same row in the X direction share the selection gate and the source line, and the storage units in the same column in the Y direction share the bit line.
The invention also provides a preparation method of the OTP device, which comprises the following steps:
The method comprises the steps of providing a substrate, defining an X direction and a Y direction which are perpendicular to each other in a plane parallel to the upper surface of the substrate, forming a plurality of active areas which are arranged in parallel at intervals along the X direction in the substrate, extending Y-direction active area extending parts along the Y direction, and extending X-direction active area extending parts along the X direction by each Y-direction active area extending part;
Forming a selection gate and a floating gate which are positioned above the substrate, wherein the selection gate extends along the X direction and spans a plurality of active regions, a plurality of floating gates which are distributed at intervals are formed along the X direction, the floating gates are distributed in one-to-one correspondence with the active regions, the projection of the floating gate on the substrate falls into the active regions, and the X-direction active region extension part is positioned at one side of the floating gate far away from the selection gate;
forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the floating gate, the selection gate and the substrate;
The method comprises the steps of forming a first contact hole, forming a plurality of first contact holes which are distributed at intervals along the X direction, wherein the first contact holes penetrate through an interlayer dielectric layer to expose the substrate, the first contact holes are distributed in one-to-one correspondence with the X-direction active area extending parts, the projection of the first contact holes on the substrate falls into the X-direction active area extending parts, and the first contact holes are located in the Y-direction extending areas of gap neutral gears between two adjacent floating gates in the X direction.
Further, the interlayer dielectric layer comprises a silicon nitride layer and an oxide layer from bottom to top.
Further, the floating gate and the select gate are formed in the same polysilicon layer.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides an OTP device and a preparation method thereof, the OTP device comprises an active region and an X-direction active region extension part, the projection of the first contact hole on the substrate falls into the extension part of the X-direction active region, and the first contact hole is positioned in the Y-direction extension region of the gap neutral position between two adjacent floating gates in the X-direction. According to the invention, the first contact hole is arranged at a position without overlapping the thickness of the interlayer dielectric layer through the optimization of the active region and the first contact hole layout, namely, the narrow position of the end head of the adjacent interlayer dielectric layer is exactly a narrow position of a crack formed by the interlayer dielectric layer covering two adjacent floating gates in the Y direction, and the narrow position of the crack is not formed at the position without the floating gate covered by the interlayer dielectric layer. According to the invention, the first contact hole is designed in the Y-direction extending area of the gap neutral gear between two adjacent floating gates in the X direction, and the crack position of the two adjacent floating gates in the Y direction is avoided, so that the first contact hole has the same width up and down, the contact performance of the first contact hole is optimized, the bit line contact resistance formed by filling a metal layer in the first contact hole is normal, and the performance of an OTP device is ensured. And meanwhile, the first contact hole is not easy to form a cavity when the interlayer dielectric layer is filled, so that the first contact hole is ensured to be normal.
Drawings
Fig. 1 is a schematic cross-sectional view of an OTP device.
Fig. 2 is an ideal schematic diagram of contact hole etching of an OTP device.
Fig. 3 is a schematic diagram of an OTP device contact hole etching.
Fig. 4 is a schematic diagram of a layout of an OTP device according to an embodiment of the invention.
Fig. 5 is another layout diagram of an OTP device according to an embodiment of the invention.
Fig. 6 is a schematic diagram of a partial layout of the pre-retrofit OTP device corresponding to fig. 1.
Fig. 7 is a flowchart of a method for fabricating an OTP device according to an embodiment of the invention.
Wherein, the reference numerals are as follows:
01 a-silicon nitride first portion, 01 b-silicon nitride second portion, 02-contact hole;
11-active area, 12-Y active area extension, 13-X active area extension, 14-common active area, 21-floating gate, 22-select gate, 31-first contact hole, 32-second contact hole.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are not to scale precisely, but rather merely for the purpose of facilitating and clearly aiding in the description of the embodiments of the invention.
For ease of description, some embodiments of the application may use spatially relative terms, such as "above," "below," "top," "below," and the like, to describe one element or component's relationship to another element(s) or component(s) as illustrated in the figures of the embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or components described as "below" or "beneath" other elements or components would then be oriented "above" or "over" the other elements or components. The terms "first," "second," and the like, herein below, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances.
An embodiment of the present invention provides an OTP device, as shown in fig. 4 and 5, including:
the substrate is provided with a plurality of active areas 11 which are arranged in parallel at intervals along the X direction, wherein the active areas 11 extend out of Y-direction active area extending parts 12 along the Y direction, and each Y-direction active area extending part 12 extends out of X-direction active area extending parts 13 along the X direction;
The floating gate (21) is distributed with the active areas (11) in a one-to-one correspondence, the projection of the floating gate (21) on the substrate falls into the active areas (11), and the X-direction active area extension part (13) is positioned at one side of the floating gate (21) far away from the active areas (22);
An interlayer dielectric layer covering the floating gate 21, the selection gate 22 and the substrate;
The first contact holes 31 penetrate through the interlayer dielectric layer to expose the substrate, a plurality of first contact holes 31 are formed in the X direction at intervals, the first contact holes 31 are distributed in one-to-one correspondence with the X-direction active region extending parts 13, the projection of the first contact holes 31 on the substrate falls into the X-direction active region extending parts 13, and the first contact holes 31 are located in the Y-direction extending area of a gap between two adjacent floating gates 21 in the X direction.
Specifically, the substrate includes an OTP region and other regions, and a select gate 22 and a floating gate 21 are formed on the semiconductor substrate at the location of the OTP region. The substrate is illustratively used to form an OTP device and may be any suitable substrate material known in the art, such as at least one of silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbon (SiC), silicon carbon germanium (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, and also include multilayer structures of these semiconductors, or may be silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or may also be a double-sided polished silicon wafer. The substrate in this embodiment is, for example, a silicon wafer. The active region 11 has a predetermined width in the X direction and a predetermined length in the Y direction. In the Y direction, the floating gate 21 is spaced apart from the select gate 22.
The first contact hole 31 is filled with a first metal layer, and a bit line is led out. The first contact hole exposes the substrate, and a metal silicide is formed at the position of the exposed substrate, and the first metal layer is electrically connected with the metal silicide. A common active region 14 extending in the X direction is formed in the substrate on the side of the select gate 22 remote from the floating gate 21, the common active region 14 being connected to the plurality of active regions 11, respectively. A second contact hole 32 is formed above the substrate, the projection of the second contact hole 32 on the substrate falls into the common active region 14, a second metal layer is filled in the second contact hole 32, and a source line is led out.
The X-direction active region extending parts 13 are distributed at intervals along the X direction, active regions 11, floating gates 21 and selection gates 22 are distributed on two sides of the X-direction active region extending part 13 in a mirror image mode, and the Y-direction active region extending parts 12 are connected with the active regions 11 located on two sides of the X-direction active region extending part 13 in the Y direction.
The interlayer dielectric layer covers the floating gate 21, the select gate 22, the substrate and the first metal layer in the first contact hole 31. The interlayer dielectric layer may comprise a bottom-up silicon nitride layer and an oxide layer. The OTP device further includes a BPSG (borophosphosilicate glass) layer overlying the inter-layer dielectric layer.
Illustratively, one memory cell of the OTP device is formed from 2 standard PMOS in series. One of which is a select transistor and the other is a standard PMOS transistor, but the gates are not connected, but are suspended, called floating gates, i.e. used as data storage. As shown in fig. 5, one memory cell of the OTP device includes a floating gate 21, a select gate 22, a bit line, and a source line, the floating gate 21 and the select gate 22 may be formed in the same polysilicon layer, oxide layers are formed between the floating gate 21 and the substrate, and between the select gate 22 and the substrate, the bit line is drawn from a first metal layer filled in a first contact hole 31, and the source line is drawn from a second metal layer filled in a second contact hole 32. The OTP device includes a plurality of memory cells, the memory cells in the same row in the X direction share the select gate 22 and the source line, and the memory cells in the same column in the Y direction share the bit line.
Fig. 6 is a schematic diagram of a partial layout of the pre-retrofit OTP device corresponding to fig. 1. Fig. 1 and 3 are sectional views of fig. 6 along the Y direction. As shown in fig. 1, 3 and 6, the bottom of the OTP device contact hole 02 before modification is formed at the overlapping position of the thickness of the silicon nitride layer, that is, at the narrow position of the end of the adjacent silicon nitride layer, which is just the narrow position of the crack formed by the silicon nitride layer covering the adjacent two floating gates in the Y direction.
As shown in fig. 4 and 5, the OTP device of the invention includes an active area 11 and an X-direction active area extension 13, and the projection of the first contact hole 31 on the substrate falls into the X-direction active area extension 13, and the first contact hole 31 is located in the Y-direction extension region of the gap between two adjacent floating gates 21 in the X-direction. According to the invention, the first contact hole 31 is arranged at a position without overlapping thickness of an interlayer dielectric layer through layout optimization of the active region 11 and the first contact hole 31, namely, a narrow position of the end of an adjacent interlayer dielectric layer, wherein the narrow position is just a narrow position of a crack formed by covering interlayer dielectric layers of two adjacent floating gates in the Y direction, the narrow position of the crack is not formed at the position without the floating gate 21 covered by the interlayer dielectric layer, and the first contact hole 31 is designed in a Y-direction extending area of a gap neutral gear between two adjacent floating gates 21 in the X direction, so that the crack position of two adjacent floating gates in the Y direction is avoided, the upper width and the lower width of the first contact hole 31 are not reduced, the contact area of the bottom of the first contact hole 31 is not reduced, the contact performance of the first contact hole 31 is optimized, the contact resistance of a bit line formed by filling a metal layer in the first contact hole 31 is normal, and the performance of an OTP device is ensured. Meanwhile, the first contact hole 31 is not easy to form a cavity when the interlayer dielectric layer is filled, so that the first contact hole 31 is ensured to be normal.
The invention also provides a preparation method of the OTP device, as shown in FIG. 7, comprising the following steps:
S1, providing a substrate, defining an X direction and a Y direction which are perpendicular to each other in a plane parallel to the upper surface of the substrate, forming a plurality of active areas which are arranged in parallel at intervals along the X direction in the substrate, wherein the active areas extend out of Y-direction active area extending parts along the Y direction, and each Y-direction active area extending part extends out of X-direction active area extending parts along the X direction;
s2, forming a selection gate and a floating gate which are positioned above the substrate, wherein the selection gate extends along the X direction and spans a plurality of active regions, and a plurality of floating gates which are distributed at intervals are formed along the X direction;
S3, forming an interlayer dielectric layer, wherein the interlayer dielectric layer covers the floating gate, the selection gate and the substrate;
S4, forming first contact holes, wherein the first contact holes penetrate through the interlayer dielectric layer to expose the substrate, a plurality of first contact holes are formed in an interval mode along the X direction and are distributed in one-to-one correspondence to the X-direction active area extending parts, projection of the first contact holes on the substrate falls into the X-direction active area extending parts, and the first contact holes are located in Y-direction extending areas of gap neutral gear between two adjacent floating gates in the X direction.
The interlayer dielectric layer comprises a silicon nitride layer and an oxide layer from bottom to top. The floating gate and the select gate are formed in the same polysilicon layer.
In summary, the invention provides an OTP device and a method for manufacturing the same, where the OTP device includes an active area and an X-direction active area extension, a projection of a first contact hole on a substrate falls into the X-direction active area extension, and the first contact hole is located in a Y-direction extension area of a gap between two adjacent floating gates in the X-direction. According to the invention, the first contact hole is arranged at a position without overlapping the thickness of the interlayer dielectric layer through the optimization of the active region and the first contact hole layout, namely, the narrow position of the end head of the adjacent interlayer dielectric layer is exactly a narrow position of a crack formed by the interlayer dielectric layer covering two adjacent floating gates in the Y direction, and the narrow position of the crack is not formed at the position without the floating gate covered by the interlayer dielectric layer. According to the invention, the first contact hole is designed in the Y-direction extending area of the gap neutral gear between two adjacent floating gates in the X direction, and the crack position of the two adjacent floating gates in the Y direction is avoided, so that the first contact hole has the same width up and down, the contact performance of the first contact hole is optimized, the bit line contact resistance formed by filling a metal layer in the first contact hole is normal, and the performance of an OTP device is ensured. And meanwhile, the first contact hole is not easy to form a cavity when the interlayer dielectric layer is filled, so that the first contact hole is ensured to be normal.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the method disclosed in the embodiment, the description is relatively simple since it corresponds to the device disclosed in the embodiment, and the relevant points refer to the description of the method section.
The foregoing description is only illustrative of the preferred embodiments of the present invention, and is not intended to limit the scope of the claims, and any person skilled in the art may make any possible variations and modifications to the technical solution of the present invention using the method and technical content disclosed above without departing from the spirit and scope of the invention, so any simple modification, equivalent variation and modification made to the above embodiments according to the technical matter of the present invention fall within the scope of the technical solution of the present invention.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510238533.1A CN120091561A (en) | 2025-02-28 | 2025-02-28 | OTP device and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202510238533.1A CN120091561A (en) | 2025-02-28 | 2025-02-28 | OTP device and preparation method thereof |
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| Publication Number | Publication Date |
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| CN120091561A true CN120091561A (en) | 2025-06-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202510238533.1A Pending CN120091561A (en) | 2025-02-28 | 2025-02-28 | OTP device and preparation method thereof |
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| CN (1) | CN120091561A (en) |
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- 2025-02-28 CN CN202510238533.1A patent/CN120091561A/en active Pending
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