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CN120110345B - An operational amplifier clamping circuit - Google Patents

An operational amplifier clamping circuit

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Publication number
CN120110345B
CN120110345B CN202510596175.1A CN202510596175A CN120110345B CN 120110345 B CN120110345 B CN 120110345B CN 202510596175 A CN202510596175 A CN 202510596175A CN 120110345 B CN120110345 B CN 120110345B
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CN
China
Prior art keywords
transistor
differential input
voltage
common
operational amplifier
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Application number
CN202510596175.1A
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Chinese (zh)
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CN120110345A (en
Inventor
翟源宏
张鑫
刘炽锋
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Guangzhou Huizhi Microelectronics Co ltd
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Guangzhou Huizhi Microelectronics Co ltd
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Priority to CN202510596175.1A priority Critical patent/CN120110345B/en
Publication of CN120110345A publication Critical patent/CN120110345A/en
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Publication of CN120110345B publication Critical patent/CN120110345B/en
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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45273—Mirror types

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

本公开提供了一种运放钳位电路，包括：运算放大器和钳位电压控制电路。运算放大器包括共源共栅电流镜和第一差分输入晶体管。其中，第一差分输入晶体管的第一端，连接述共源共栅电流镜中第一共栅管和第一共源管的连接节点；第一差分输入晶体管的第二端接地；第一差分输入晶体管的控制端和钳位电压控制电路，均接收第一差分输入信号；钳位电压控制电路，连接第一共栅管的控制端，被配置为向第一共栅管输出第一偏置电压，以及，基于第一差分输入信号调节第一偏置电压；其中，第一偏置电压与所述第一差分输入信号的电压正相关。从而，提高运放钳位电路的可靠性，减少因过压或异常信号导致的故障。

The present disclosure provides an operational amplifier clamp circuit, comprising: an operational amplifier and a clamp voltage control circuit. The operational amplifier comprises a cascode current mirror and a first differential input transistor. The first end of the first differential input transistor is connected to the connection node of the first common-gate transistor and the first common-source transistor in the cascode current mirror; the second end of the first differential input transistor is grounded; the control end of the first differential input transistor and the clamp voltage control circuit both receive a first differential input signal; the clamp voltage control circuit is connected to the control end of the first common-gate transistor and is configured to output a first bias voltage to the first common-gate transistor, and to adjust the first bias voltage based on the first differential input signal; the first bias voltage is positively correlated with the voltage of the first differential input signal. Thus, the reliability of the operational amplifier clamp circuit is improved and faults caused by overvoltage or abnormal signals are reduced.

Description

Operational amplifier clamping circuit
Technical Field
The disclosure relates to the technical field of integrated circuits, in particular to an operational amplifier clamping circuit.
Background
The operational amplifier clamping circuit mainly utilizes the characteristics of an operational amplifier to clamp or limit an input signal, so that the signal is ensured to be kept in a preset range. The circuit structure is widely applied to various electronic devices to improve the stability and reliability of the circuit.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide an operational amplifier clamping circuit to improve the reliability of the operational amplifier in the limit working state.
The technical scheme of the embodiment of the disclosure is realized as follows:
The embodiment of the disclosure provides an operational amplifier clamping circuit which comprises an operational amplifier and a clamping voltage control circuit, wherein the operational amplifier comprises a cascode current mirror and a first differential input transistor, a first end of the first differential input transistor is connected with a connecting node of the first common gate transistor and the first common source transistor in the cascode current mirror, a second end of the first differential input transistor is grounded, a control end of the first differential input transistor and the clamping voltage control circuit are respectively used for receiving a first differential input signal, the clamping voltage control circuit is connected with the control end of the first common gate transistor and is configured to output a first bias voltage to the first common gate transistor, and the first bias voltage is regulated based on the first differential input signal, wherein the first bias voltage is positively correlated with the voltage of the first differential input signal.
In the scheme, the clamping voltage control circuit comprises a first transistor, wherein a control end of the first transistor receives the first differential input signal, a first end of the first transistor is connected with a control end of the first common grid tube, the first differential input signal is used for controlling the conduction degree of the first transistor, and the voltage of the first differential input signal is positively correlated with the conduction degree of the first transistor.
In the scheme, the first transistor is turned on when the difference value between the voltage of the first differential input signal and the power supply voltage is smaller than or equal to a first preset value, or is turned off when the difference value between the voltage of the first differential input signal and the power supply voltage is larger than a second preset value, wherein the first preset value is smaller than the second preset value.
In the scheme, the clamping voltage control circuit further comprises a second transistor, a first voltage reducing element, a second voltage reducing element and a first current source, wherein the first end of the second transistor receives the power supply end, the second end and the control end of the second transistor are connected with the first end of the first voltage reducing element, the second end of the first voltage reducing element and the first end of the second voltage reducing element are connected with the second end of the first transistor, the second end of the second voltage reducing element and the first end of the first transistor are connected with the first end of the first current source, and the second end of the first current source is grounded.
In the above scheme, the second transistor, the first common-source transistor and the first common-gate transistor, and the equivalent dimensions of the first common-source transistor and the second common-gate transistor are equal.
In the scheme, the operational amplifier clamping circuit further comprises a clamping circuit, wherein the clamping circuit is configured to isolate the first differential input transistor under the condition that the voltage of the first differential input signal and the power supply voltage are smaller than a third preset value, and the third preset value is larger than the first preset value.
In the scheme, the clamping circuit comprises a third transistor, wherein the first end of the third transistor is connected with the first end of the first differential input transistor, the second end of the third transistor is connected with the second end of the second differential input transistor, and the control end of the third transistor receives the second bias voltage.
The operational amplifier clamping circuit further comprises a second clamping circuit, wherein the second clamping circuit is connected with the operational amplifier and is configured to receive a first differential input signal and adjust the first differential input signal from a first voltage to a second voltage, and the clamping voltage control circuit is connected with the second clamping circuit and is further configured to adjust the voltage difference between the first voltage and the second voltage.
In the scheme, the clamping circuit comprises a third transistor, wherein the first end of the third transistor is connected with the first end of the first differential input transistor, the second end of the third transistor is connected with the second end of the second differential input transistor, and the control end of the third transistor receives the second bias voltage.
In the scheme, the operational amplifier further comprises a second differential input transistor, wherein the control end of the second differential input transistor receives a second differential input signal, the first end of the second differential input transistor is grounded, and the second ends of the second differential input transistor are connected with the connection nodes of the second common gate transistor and the second common source transistor in the common source common gate current mirror.
In the scheme, the first ends of the first common-source tube and the second common-source tube are connected with the power end, the second end of the first common-source tube is connected with the first end of the first common-gate tube, the second end of the second common-source tube is connected with the first end of the second common-gate tube, the control end of the first common-source tube is respectively connected with the control end of the second common-source tube and the second end of the first common-gate tube, the control end of the second common-gate tube is connected with the clamping voltage control circuit and receives the first bias voltage, and the second ends of the first common-gate tube and the second common-gate tube are grounded.
The operational amplifier clamping circuit is applied to a current mirror circuit, wherein the current mirror circuit comprises a first current mirror, a second current source and a load circuit, wherein the output end of an operational amplifier is respectively connected with the control ends of an input transistor and an output transistor in the first current mirror, the first differential input end of the operational amplifier is respectively connected with the second end of the input transistor in the first current mirror and the first end of the second current source, the second differential input end of the operational amplifier is respectively connected with the second end of the output transistor in the first current mirror and the first end of the load circuit, the first ends of the input transistor and the output transistor in the first current mirror receive power supply voltages, and the second ends of the load circuit and the second current source are grounded.
Drawings
Fig. 1 is a schematic diagram of a first operational amplifier clamping circuit according to an embodiment of the disclosure;
Fig. 2 is a schematic diagram of an operational amplifier according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of a clamp voltage control circuit according to an embodiment of the disclosure;
Fig. 4 is a schematic structural diagram of a clamp circuit according to an embodiment of the disclosure;
fig. 5 is a schematic diagram of a second structure of an operational amplifier according to an embodiment of the disclosure;
Fig. 6 is a second schematic structural diagram of an operational amplifier clamping circuit according to an embodiment of the present disclosure;
FIG. 7 is a schematic diagram of a current mirror circuit according to an embodiment of the disclosure;
fig. 8 is a schematic diagram of a second structure of the current mirror circuit according to the embodiment of the disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Fig. 1 is a schematic diagram of an optional op amp clamp 100 according to an embodiment of the present disclosure, and referring to fig. 1, the op amp clamp 100 includes an operational amplifier 10. The operational amplifier 10 may be any one of a two-stage operational amplifier, a folded cascode operational amplifier, a fully differential operational amplifier, and the like.
Referring to fig. 1, the operational amplifier 10 receives a first differential input signal and a second differential input signal. The operational amplifier 10 is used for amplifying a voltage difference between the first differential input signal and the second differential input signal. Under the influence of power supply fluctuations or external disturbances, the first differential input signal may exhibit an excessively high voltage, e.g. the first differential input signal is close to the power supply voltage VDD. However, the operational amplifier 10 has a limitation on the input range of the voltage, and the voltage of the first differential input signal exceeds the allowable input voltage range of the operational amplifier 10, which affects the normal operation of the operational amplifier 10 and may cause output distortion or other situations where the operational amplifier cannot operate normally.
Fig. 2 is a schematic diagram of an optional operational amplifier 10 according to an embodiment of the disclosure, where the operational amplifier 10 in fig. 2 illustrates only the cascode current mirror 11 and transistors M1 and M2 of the input stage of the operational amplifier 10. The remaining structure of the operational amplifier 10 can be understood with reference to any one of the operational amplifiers corresponding to the two-stage operational amplifier, the folded cascode operational amplifier, the fully differential operational amplifier, and the like. Fig. 2 illustrates that the first differential input transistor M1 and the second differential input transistor M2 are NMOS transistors, the first common-source transistor M4, the second common-source transistor M3, the first common-gate transistor M6 and the first common-source transistor M5 are PMOS transistors, and the M1-M6 may be other types of transistors such as bipolar transistors, which are not limited herein.
In the disclosed embodiment, referring to fig. 2, the operational amplifier 10 includes a first differential input transistor M1, a second differential input transistor M2, and a cascode current mirror 11. The control terminal of the first differential input transistor M1 receives the first differential input signal Vn. The first terminal of the first differential input transistor M1 is connected to the connection node a of the first cascode current mirror 11 and the first cascode transistor M6. That is, the voltage of the connection node a of the first common-gate transistor M6 and the first common-source transistor M4 is the same as the voltage of the first terminal of the first differential input transistor M1.
In the disclosed embodiment, referring to fig. 1, the op amp clamp circuit 100 further includes a clamp voltage control circuit 30. The clamp voltage control circuit 30 is connected to the control terminal of the first common-gate transistor M6, and is configured to output the first bias voltage Vb1 to the first common-gate transistor M6. In this way, the first bias voltage Vb1 output by the clamp voltage control circuit 30 can control the gate voltage of the first common-gate transistor M6, and since the common-gate transistor operates in the saturation region, the present disclosure can adjust the voltage (V A=Vb1+VGS) of the connection node a of the first common-gate transistor M6 and the first common-source transistor M4, and thus adjust the drain-source voltage V DS of the first differential input transistor M1 by adjusting the gate voltage of the first common-gate transistor M6.
It should be noted that, referring to fig. 3, if the voltage of the first differential input signal is within the range where the operational amplifier 10 can normally operate, if the drain-source voltage V DS of the clamp voltage control circuit 30 is continuously used for the first differential input transistor M1, the drain-source voltage V DS of the first common-source tube/the second common-source tube may be too small, so that the first common-source tube M4 or the second common-source tube M3 is separated from the saturation region, which results in a gain drop and poor mismatch resistance.
In the disclosed embodiment, referring to fig. 1, the clamp voltage control circuit 30 is further configured to adjust the first bias voltage Vb1 based on the first differential input signal. For example, the clamp voltage control circuit 30 may include a transistor. The first differential input signal may adjust the gate voltage of the transistor in the clamp voltage control circuit 30 to change the conduction degree of the transistor, thereby adjusting the first bias voltage Vb1 output from the clamp voltage control circuit 30. In this way, in the case that the first differential input signal approaches the power supply voltage VDD, the clamp voltage control circuit 30 may increase the first bias voltage Vb1 to increase the drain-source voltage V DS of the first differential input transistor M1, thereby avoiding gain degradation caused by the first differential input transistor M1 entering the linear region. When the voltage of the first differential input signal is within the allowable range of the first differential input transistor M1, the first bias voltage Vb1 output by the clamp voltage control circuit 30 does not change with the voltage of the first differential input signal, so that the voltage at the point a is kept constant, that is, the V DS of the first common source transistor M4 is kept at a constant appropriate value, and the operational amplifier bias point is better.
In some embodiments of the present disclosure, referring to fig. 2, the control terminal of the second differential input transistor M2 receives the second differential input signal Vp. The first terminal of the second differential input transistor M2 is connected to the connection node B of the second cascode transistor M5 and the second cascode transistor M3 in the cascode current mirror 11. That is, the voltage of the connection node B of the second cascode transistor M5 and the second cascode transistor M3 is the same as the voltage of the first terminal of the second differential input transistor M2. In this way, the first bias voltage Vb1 output by the clamp voltage control circuit 30 can control the gate voltage of the second common-gate transistor M5 to adjust the voltage of the connection node B of the second common-gate transistor M5 and the second common-source transistor M3, thereby adjusting the drain-source voltage V DS of the second differential input transistor M2, and avoiding gain drop caused by the second differential input transistor M2 entering the linear region.
Fig. 3 is a schematic diagram of an alternative clamp voltage control circuit 30 according to an embodiment of the present disclosure.
In some embodiments of the present disclosure, referring to fig. 3, the clamp voltage control circuit 30 includes a first transistor M7. The second terminal of the first transistor M7 is connected to the control terminal of the first common-gate transistor M6. The control terminal of the first transistor M7 receives the first differential input signal. The first differential input signal is used to control the degree of conduction of the first transistor M7. For example, in the case where the first differential input signal is close to the power supply voltage VDD, the first transistor M7 is turned on. For another example, the first transistor M7 is turned off in the case where the second differential input signal is within the allowable range of the first differential input transistor M1.
That is, the first bias voltage Vb1 in the clamp voltage control circuit 30 controls the drain voltage of the first differential input transistor M1. In this way, when the voltage of the first differential input signal approaches the power supply voltage VDD, the first bias voltage Vb1 can make the first transistor M7 be in the on state, so that the drain voltage of the first differential input transistor M1 can establish enough V DS, thereby avoiding that the voltage of the first differential input signal exceeds the allowable range of the operational amplifier 10, and further reducing the malfunction caused by the overvoltage or the abnormal signal.
In addition, in the case where the voltage of the first differential input signal is in the range allowed by the first differential input transistor M1, the first transistor M7 is in an off state. In this way, the embodiment of the disclosure can avoid the influence of the first bias voltage Vb1 on the drain voltage of the first common-source transistor M3, and avoid the situation that the first common-source transistor is separated from the saturation region.
The voltage of the first differential input signal is positively correlated with the conduction degree of the first transistor M7. That is, as the first differential input signal gets closer to the power supply voltage VDD, the degree of conduction of the first transistor M7 increases, and the first bias voltage Vb1 increases.
In some embodiments of the present disclosure, referring to fig. 3, the first transistor M7 is turned on when a difference between a voltage of the first differential input signal and a power supply voltage is less than or equal to a first preset value. For example, the voltage of the power supply voltage VDD may be 3 to 5v, and the first preset value may be 100 to 200mv. In the case that the difference between the voltage of the first differential input signal and the power supply voltage VDD is less than or equal to the first preset value, that is, the voltage of the first differential input signal approaches the power supply voltage VDD, the clamp voltage control circuit 30 may turn on the first transistor M7. In this way, the present disclosure can increase the drain-source voltage V DS of the first differential input transistor M1, thereby avoiding significant gain degradation caused by the first differential input transistor M1 entering the linear region.
In the embodiment of the disclosure, referring to fig. 3, when the voltage difference between the voltage of the first differential input signal and the power supply voltage VDD is smaller than the first preset value, or greater than or equal to the second preset value, the first transistor M7 is turned off. For example, the voltage of the power supply voltage VDD may be 3-5 v, the first preset value may be 100-200 mV, and the second preset value may be 300mV. In this way, when the first transistor M7 is turned off, the voltage of the first differential input signal does not affect the value of the first bias voltage Vb1, and thus the first bias voltage Vb1 is prevented from affecting the drain voltage of the first differential input transistor M1.
In some embodiments of the present disclosure, referring to fig. 3, the clamp voltage control circuit 30 further includes a second transistor M8, a first step-down element 31, a second step-down element 32, and a first current source 33. For example, the first voltage reducing element 31 may include a first resistor R1, and the second voltage reducing element 32 may include a second resistor R2. The first terminal of the second transistor M8 receives the power supply voltage VDD. A second terminal of the second voltage reducing element 32 and a first terminal of the first transistor M7 are connected to a first terminal of the first current source 33. The second terminal of the first current source 33 is grounded.
In the disclosed embodiment, referring to fig. 2, a first current source 33 is used to provide a bias current I bias. The second terminal and the control terminal of the second transistor M8 are both connected to the first terminal of the first voltage dropping element 31. The second terminal of the first voltage reducing element 31 and the first terminal of the second voltage reducing element 32 are both connected to the second terminal of the first transistor M7. When the voltage of the first differential input signal approaches the power supply voltage VDD, the bias voltage provided by the first differential input signal can make the first transistor M7 in an on state, and short-circuit the second voltage-reducing element 32, so that the first transistor M7 can adjust the first bias voltage Vb1 according to the voltage of the first differential input signal, and further, the drain voltage of the first differential input transistor M1 can be adjusted to establish enough V DS, thereby avoiding that the voltage of the first differential input signal exceeds the allowable range of the operational amplifier 10, and further, reducing faults caused by overvoltage or abnormal signals.
In addition, in the case where the voltage of the first differential input signal is far from the power supply voltage VDD, the first transistor M8 is completely turned off. In this way, in the case where the first transistor M7 is turned off, the first transistor M7 is made not to flow a current, the voltage of the first differential input signal is prevented from affecting the first bias voltage Vb1,
Note that the first voltage reducing element 31 and the second voltage reducing element 32 illustrated in fig. 3 are both resistors. The first voltage reducing element 31 and the second voltage reducing element 32 may also be transistors, without limitation. In some embodiments, the clamp voltage control circuit 30 may only provide the second step-down element 32.
In some embodiments of the present disclosure, referring to fig. 3, the equivalent dimensions of the second transistor M8, the first common-gate transistor M4, and the second common-gate transistor M3 are equal. Thus, if the currents flowing through the second transistor M8, the first common-gate transistor M4, and the second common-gate transistor M3 are equal, the gate-source voltages V GS of the three are equal.
Fig. 4 is a schematic diagram of an alternative clamping circuit according to an embodiment of the present disclosure.
In some embodiments of the present disclosure, referring to fig. 4, the op amp clamp circuit 100 further includes a clamp circuit 20. The clamp circuit 20 is configured to isolate the first differential input transistor M1 if the difference between the voltage of the first differential input signal and the power supply voltage VDD is less than a third preset value. Wherein the third preset value is greater than the second threshold.
It should be noted that, referring to fig. 4, in a case where a difference between the voltage of the first differential input signal and the power supply voltage VDD is greater than a third preset value, the voltage of the first differential input signal may cause damage to the first differential input transistor. For example, the voltage of the power supply voltage VDD may be 3-5V, the third preset value may be 2.5V, and the voltage of the first differential input signal may be 500mV. In this way, the voltage of the first differential input signal approaches the ground voltage, and the first differential input transistor M1 may deviate from the normal operation state or even be damaged due to the excessive drain-source voltage V DS.
In the embodiment of the present disclosure, referring to fig. 4, in the case that the voltage of the first differential input signal is too low, the embodiment of the present disclosure may isolate the first differential input transistor M1 by the clamp circuit 20, that is, the clamp circuit 20 shorts the first differential input transistor M1. For example, a plurality of diode strings are connected in parallel in the opposite direction between the source and the drain of the first differential input transistor M1, and voltage clamping is realized by the low impedance characteristic when the diodes are turned on. For another example, the clamp circuit 20 may include a transistor that becomes a differential input stage of the operational amplifier 10 instead of the first differential input transistor M1 when the first differential input signal is too low. As such, in the event that the voltage of the first differential input signal is too low, embodiments of the present disclosure may isolate the first differential input transistor M1 using the clamp circuit 20. Therefore, the voltage of the first differential input signal is prevented from being too low, so that the differential input tube VDS is prevented from being too large and deviating from the normal working range.
In some embodiments of the present disclosure, referring to fig. 4, the clamp circuit 20 includes a third transistor M20. Wherein, the first end of the third transistor M20 is connected to the first end of the first differential input transistor M1. A second terminal of the third transistor M20 is connected to the second terminal of the first differential input transistor M1. The control terminal of the third transistor M20 receives the second bias voltage Vb2.
In the embodiment of the disclosure, referring to fig. 4, in a case where the voltage of the first differential input signal is too low (for example, the voltage of the first differential input signal approaches the ground voltage), the third transistor M20 is in an on state after receiving the second bias voltage Vb2, and further, the clamp circuit 20 may short-circuit the first differential input transistor M1. Thus, the differential input tube VDS can be prevented from being excessively large to deviate from the normal operating range or even be damaged. It should be further noted that the control terminal of the first differential input transistor M2 may receive the second bias voltage Vb2, so as to avoid the drain-source voltage of the second differential input transistor M2 from being too high.
Fig. 5 is a schematic structural diagram of an alternative folded cascode operational amplifier according to an embodiment of the present disclosure, and fig. 6 specifically illustrates a connection relationship between the folded cascode operational amplifier in fig. 5 and the clamp circuit 20 and the clamp voltage control circuit 30.
It should be noted that the functions of the transistors M13, M14, M9, M10, M11, and M12 in fig. 5 can be understood with reference to the first current source for providing the tail current. The bias voltages Vb3, vb4 drive the corresponding transistors, respectively.
The principle of the operational amplifier 10, the clamp circuit 20, and the clamp voltage control circuit 30 will be described below by taking the folded cascode operational amplifier illustrated in fig. 5 and 6 as an example:
In the disclosed embodiment, and in conjunction with fig. 5 and 6, the two inputs Vp and Vn of the op-amp have the same voltage to produce a zero output in an ideal case. However, due to mismatch in the actual circuit, such as differences in transistor size, threshold voltage, etc., there is an input offset voltage Δvoffset. Under the condition that the voltage of the first differential input signal is close to the power supply voltage VDD, the first differential input transistor M1 and the second differential input transistor M2 may be in a linear region, and the transconductance (gm) thereof may be significantly reduced, so that the influence of the input offset voltage may be further increased, and further, the problems of reduced open loop gain, poor stability and the like of the operational amplifier 10 may occur.
Further, the clamp voltage control circuit 30 can adjust the source-drain voltage V DS of the first differential input transistor M1 when the voltage of the first differential input signal is close to the power supply voltage VDD, so as to prevent the first differential input transistor M1 and the second differential input transistor M2 from entering the linear region, thereby improving the reliability of the op amp clamp circuit and reducing the faults caused by overvoltage or abnormal signals.
In addition, in the case that the voltage of the first differential input signal is far from the power supply voltage VDD, the clamp voltage control circuit 30 may turn off the first transistor M7, so as to avoid the first common gate transistor M6 from affecting the drain voltage of the first differential input transistor M1. Thus, signal integrity is ensured and signal clipping or distortion due to improper clamping is avoided.
Fig. 7 is a schematic structural diagram of the op amp clamp circuit 100 applied to the current mirror circuit 200 according to the embodiment of the present disclosure, and it should be noted that fig. 7 illustrates that the op amp clamp circuit 100 is applied to the current mirror circuit 200. The op amp clamp circuit 100 may also be applied to other types of circuits, such as interface circuits, without limitation.
Fig. 8 is a schematic diagram of an alternative current mirror circuit 200 according to an embodiment of the present disclosure, and the principle of the operational amplifier clamping circuit 100 acting on the current mirror circuit 200 will be described with reference to the current mirror circuit 200 illustrated in fig. 8:
In the disclosed embodiment, in conjunction with fig. 7 and 8, the current mirror circuit 200 includes a first current mirror 201, a second current source 202, and a load circuit 203. The output terminal Vo of the operational amplifier 10 is connected to the control terminals of the input transistor M31 and the output transistor M32 in the first current mirror 201, respectively. The first differential input terminal of the operational amplifier 10 is connected to the second terminal of the input transistor M31 in the first current mirror 201 and the first terminal of the second current source 202, respectively. The second differential input terminal of the operational amplifier 10 is connected to the second terminal of the output transistor M32 in the first current mirror 201 and the first terminal of the load circuit 203, respectively. The first terminals of the input transistor M31 and the output transistor M32 in the first current mirror 201 receive the power supply voltage VDD. The second current source 202 and the second terminal of the load circuit 203 are grounded.
In the disclosed embodiment, referring to fig. 7 and 8, the inverting input terminal of the op amp clamp circuit 100 may receive the first differential input signal Vn. The non-inverting input of the op amp clamp 100 may receive a second differential input signal Vp. In the case where the voltage of the first differential input signal Vn approaches the power supply voltage VDD, the loop gain is significantly reduced, and the differential input transistor in the op-amp clamp circuit 100 may approach its linear region, resulting in a reduced transconductance and an increased offset voltage, and further, the image current Iout output by the first current mirror 201 in the current mirror circuit 200 may be amplified due to Δviffset in the op-amp clamp circuit 100. The closer the voltage of the first differential input signal is to the power supply voltage VDD, the larger the amplification factor of the mirror current Iout is, and further, the excessive output current may damage the subsequent circuit. That is, random mismatch (e.g., transistor size mismatch) can cause the mirror ratio of the current mirror circuit 200 to deviate from ideal. In the event that the loop gain of the current mirror circuit 200 drops to some extent, the current mirror circuit 200 may not be able to effectively adjust to counteract this random mismatch, causing the loop of the current mirror circuit 200 to enter a locked state.
Further, in the case that the voltage of the first differential input signal is close to the power supply voltage VDD, the clamp circuit in the op amp clamp circuit 100 may adjust V DS of the transistor in the op amp clamp circuit 100 that receives the first differential input signal, so as to avoid the transistor from entering the linear region. In this way, the embodiment of the disclosure can avoid the current mirror circuit 200 from entering the limit working condition (such as too low loop gain and too large offset voltage), and improve the reliability of the current mirror circuit 200 under the limit working condition.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure.

Claims (9)

1.一种运放钳位电路，其特征在于，包括：运算放大器和钳位电压控制电路；其中，1. An operational amplifier clamp circuit, comprising: an operational amplifier and a clamp voltage control circuit; wherein: 所述运算放大器包括：共源共栅电流镜和第一差分输入晶体管；其中，所述第一差分输入晶体管的第一端，连接所述共源共栅电流镜中第一共栅管和第一共源管的连接节点；所述第一差分输入晶体管的第二端接地；The operational amplifier comprises: a cascode current mirror and a first differential input transistor; wherein a first terminal of the first differential input transistor is connected to a connection node between a first common-gate transistor and a first common-source transistor in the cascode current mirror; and a second terminal of the first differential input transistor is grounded; 所述第一差分输入晶体管的控制端和所述钳位电压控制电路，均接收第一差分输入信号；The control terminal of the first differential input transistor and the clamping voltage control circuit both receive a first differential input signal; 所述钳位电压控制电路，连接所述第一共栅管的控制端，被配置为向所述第一共栅管输出第一偏置电压，以及，基于所述第一差分输入信号调节所述第一偏置电压；其中，所述第一偏置电压与所述第一差分输入信号的电压正相关；The clamp voltage control circuit is connected to the control terminal of the first common-gate transistor and is configured to output a first bias voltage to the first common-gate transistor, and adjust the first bias voltage based on the first differential input signal; wherein the first bias voltage is positively correlated with the voltage of the first differential input signal; 所述钳位电压控制电路包括：第一晶体管；其中，The clamping voltage control circuit includes: a first transistor; wherein, 所述第一晶体管的控制端接收所述第一差分输入信号，所述第一晶体管的第一端，连接所述第一共栅管的控制端；The control terminal of the first transistor receives the first differential input signal, and the first terminal of the first transistor is connected to the control terminal of the first common-gate transistor; 所述第一差分输入信号用于控制所述第一晶体管的导通程度；其中，所述第一差分输入信号的电压与所述第一晶体管的导通程度正相关。The first differential input signal is used to control the conduction degree of the first transistor; wherein the voltage of the first differential input signal is positively correlated with the conduction degree of the first transistor. 2.根据权利要求1所述的运放钳位电路，其特征在于，在所述第一差分输入信号的电压与电源电压的差值小于等于第一预设值的情况下，所述第一晶体管导通；或者，在所述第一差分输入信号的电压与电源电压的差值大于第二预设值的情况下，所述第一晶体管关断；其中，所述第一预设值小于所述第二预设值。2. The operational amplifier clamp circuit according to claim 1, wherein the first transistor is turned on when the difference between the voltage of the first differential input signal and the power supply voltage is less than or equal to a first preset value; or the first transistor is turned off when the difference between the voltage of the first differential input signal and the power supply voltage is greater than a second preset value; wherein the first preset value is less than the second preset value. 3.根据权利要求2所述的运放钳位电路，其特征在于，所述钳位电压控制电路还包括：第二晶体管、第一降压元件、第二降压元件和第一电流源；其中，3. The operational amplifier clamp circuit according to claim 2, wherein the clamp voltage control circuit further comprises: a second transistor, a first voltage-dropping element, a second voltage-dropping element, and a first current source; wherein, 所述第二晶体管的第一端接收电源电压；所述第二晶体管的第二端和控制端，均连接所述第一降压元件的第一端；所述第一降压元件的第二端和所述第二降压元件的第一端，均连接所述第一晶体管的第二端；所述第二降压元件的第二端和所述第一晶体管的第一端，连接所述第一电流源的第一端；所述第一电流源的第二端接地。The first end of the second transistor receives a power supply voltage; the second end and the control end of the second transistor are both connected to the first end of the first voltage-dropping element; the second end of the first voltage-dropping element and the first end of the second voltage-dropping element are both connected to the second end of the first transistor; the second end of the second voltage-dropping element and the first end of the first transistor are connected to the first end of the first current source; and the second end of the first current source is grounded. 4.根据权利要求3所述的运放钳位电路，其特征在于，所述运放钳位电路还包括：钳位电路；其中，4. The operational amplifier clamp circuit according to claim 3, characterized in that the operational amplifier clamp circuit further comprises: a clamp circuit; wherein, 所述钳位电路，被配置为在所述第一差分输入信号的电压与电源电压的差值小于第三预设值的情况下，隔离所述第一差分输入晶体管；其中，所述第三预设值大于所述第一预设值。The clamp circuit is configured to isolate the first differential input transistor when a difference between a voltage of the first differential input signal and a power supply voltage is less than a third preset value; wherein the third preset value is greater than the first preset value. 5.根据权利要求4所述的运放钳位电路，其特征在于，所述钳位电路包括：第三晶体管；其中，5. The operational amplifier clamp circuit according to claim 4, characterized in that the clamp circuit comprises: a third transistor; wherein, 所述第三晶体管的第一端，连接所述第一差分输入晶体管的第一端；所述第三晶体管的第二端，连接所述第一差分输入晶体管的第二端；所述第三晶体管的控制端，接收第二偏置电压。The first end of the third transistor is connected to the first end of the first differential input transistor; the second end of the third transistor is connected to the second end of the first differential input transistor; and the control end of the third transistor receives a second bias voltage. 6.根据权利要求3所述的运放钳位电路，其特征在于，所述运算放大器还包括：第二差分输入晶体管；其中，6. The operational amplifier clamp circuit according to claim 3, wherein the operational amplifier further comprises: a second differential input transistor; 所述第二差分输入晶体管的控制端，接收第二差分输入信号；The control terminal of the second differential input transistor receives a second differential input signal; 所述第二差分输入晶体管的第一端接地；所述第二差分输入晶体管的第二端均连接所述共源共栅电流镜中第二共栅管和第二共源管的连接节点。The first end of the second differential input transistor is grounded; the second end of the second differential input transistor is connected to the connection node of the second common-gate transistor and the second common-source transistor in the common-source current mirror. 7.根据权利要求6所述的运放钳位电路，其特征在于，7. The operational amplifier clamp circuit according to claim 6, wherein: 所述第一共源管和所述第二共源管的第一端均接收电源电压；The first ends of the first common-source transistor and the second common-source transistor both receive a power supply voltage; 所述第一共源管的第二端连接所述第一共栅管的第一端，所述第二共源管的第二端连接所述第二共栅管的第一端；所述第一共源管的控制端，分别连接所述第二共源管的控制端和所述第一共栅管的第二端；所述第二共栅管的控制端连接所述钳位电压控制电路，接收所述第一偏置电压；The second end of the first common-source transistor is connected to the first end of the first common-gate transistor, and the second end of the second common-source transistor is connected to the first end of the second common-gate transistor; the control end of the first common-source transistor is respectively connected to the control end of the second common-source transistor and the second end of the first common-gate transistor; the control end of the second common-gate transistor is connected to the clamping voltage control circuit to receive the first bias voltage; 所述第一共栅管和所述第二共栅管的第二端均接地。The second ends of the first common-gate transistor and the second common-gate transistor are both grounded. 8.根据权利要求7所述的运放钳位电路，其特征在于，所述第二晶体管，所述第一共栅管，以及，所述第二共栅管的等效尺寸相等。8 . The operational amplifier clamp circuit according to claim 7 , wherein the second transistor, the first common-gate transistor, and the second common-gate transistor have the same equivalent size. 9.根据权利要求1所述的运放钳位电路，其特征在于，所述运放钳位电路应用于电流镜电路；其中，9. The operational amplifier clamp circuit according to claim 1, wherein the operational amplifier clamp circuit is applied to a current mirror circuit; wherein, 所述电流镜电路包括：第一电流镜、第二电流源和负载电路；其中，The current mirror circuit includes: a first current mirror, a second current source and a load circuit; wherein, 所述运算放大器的输出端，分别连接所述第一电流镜中输入晶体管和输出晶体管的控制端；The output end of the operational amplifier is connected to the control end of the input transistor and the output transistor in the first current mirror respectively; 所述运算放大器的第一差分输入端，分别连接所述第一电流镜中输入晶体管的第二端和所述第二电流源的第一端；The first differential input terminal of the operational amplifier is connected to the second terminal of the input transistor in the first current mirror and the first terminal of the second current source respectively; 所述运算放大器的第二差分输入端，分别连接所述第一电流镜中输出晶体管的第二端和所述负载电路的第一端；The second differential input terminal of the operational amplifier is connected to the second terminal of the output transistor in the first current mirror and the first terminal of the load circuit respectively; 所述第一电流镜中输入晶体管和输出晶体管的第一端连接电源端；所述负载电路和所述第二电流源的第二端接地。The first ends of the input transistor and the output transistor in the first current mirror are connected to the power supply end; the second ends of the load circuit and the second current source are grounded.
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