CN120124570A

CN120124570A - A method for extracting netlist of digital-analog hybrid integrated circuit

Info

Publication number: CN120124570A
Application number: CN202510196810.7A
Authority: CN
Inventors: 宋伟涛; 杨传宝
Original assignee: Guanzhou Microelectronics Shanghai Co ltd
Current assignee: Guanzhou Microelectronics Shanghai Co ltd
Priority date: 2025-02-21
Filing date: 2025-02-21
Publication date: 2025-06-10

Abstract

A method for extracting a netlist of a digital-analog hybrid integrated circuit includes the following steps: step 1. finding a simulation library called by a digital-analog hybrid integrated circuit whose netlist needs to be extracted; step 2. finding each submodule that directly calls a device in the simulation library; step 3. deleting the submodule netlist of all submodules in set A found in step 2; step 4. extracting the digital-analog hybrid integrated circuit netlist; step 5. finding the pin description in the digital-analog hybrid integrated circuit netlist; step 6. rewriting the internal netlist of each submodule in set A; step 7. merging to obtain a complete digital-analog hybrid integrated circuit netlist. The present invention uses the underlying module netlist in the form of name mapping directly extracted by a computer, and does not need to manually edit pin definitions and check and modify them, thereby improving the efficiency and accuracy of digital-analog hybrid integrated circuits in digital function simulation.

Description

Method for extracting netlist of digital-analog hybrid integrated circuit

Technical Field

The invention belongs to the technical field of integrated circuits, relates to an integrated circuit simulation technology, and in particular relates to a method for extracting a digital-analog hybrid integrated circuit netlist.

Background

The digital-analog hybrid integrated circuit refers to an integrated circuit with both analog circuits and a large number of digital logic circuits, and when the digital-analog hybrid integrated circuit performs simulation, the conventional mode is to instantiate a code coded in verilog computer language representing the functions of the digital logic circuits and an analog circuit netlist formed by a spice language representing the analog circuits, and then perform simulation by a test platform, but the workload and the simulation time for instantiating a netlist in spice form are too long.

In order to overcome the defects, one improvement way is to directly export the analog circuit in a verilog language model (verilog_module) way through virtuoso software without performing the spice netlist instantiation. The verilog code representing the digital logic circuit and the verilog language model representing the analog circuit are combined together for simulation, so that the simulation is actually changed into the traditional digital verification, and the simulation running time can be greatly reduced.

However, when using virtuoso software to extract the verilog language model of the circuit, the virtuoso software only directly gives the verilog language model according to the device used by the circuit diagram and the input/output port of each device, and because the extracted verilog language model is instantiated according to the position mapping. When other submodules are called in the instantiation mode, pins of the submodules are easy to make mistakes, and calling ports are inconsistent, so that simulation data of the whole module are disordered, the verilog language model cannot be directly used, manual inspection and modification are needed, errors are easy to occur, and efficiency is affected.

Disclosure of Invention

Aiming at the defects existing in the prior art, the invention discloses a method for extracting a digital-analog hybrid integrated circuit netlist.

The invention relates to a method for extracting a digital-analog hybrid integrated circuit netlist, which comprises the following steps:

Step 1, finding a simulation library for calling a digital-analog hybrid integrated circuit, which needs to extract a netlist, in a CADENCE circuit aided design software environment;

step 2, finding out that the device is directly called in the simulation library, and describing each submodule of the function by using a simulation language, and defining a set as A;

Step 3, deleting the submodule netlists of all the submodules in the set A found in the step 2;

Step 4, extracting a digital-analog hybrid integrated circuit netlist;

step 5, finding pin descriptions used when all sub-modules in the set A are called in the digital-analog hybrid integrated circuit netlist;

Step 6, rewriting the internal netlist of each submodule in the set A, wherein the method specifically comprises the following steps:

step 61, writing the pin definition of each sub-module according to the pin description obtained in the step 5;

Step 62, describing the function of the submodule by using a simulation language according to the pin definition of step 61 to obtain a submodule netlist;

And 7, merging the digital-analog hybrid integrated circuit netlist obtained in the step 4 and the submodule netlist of all the submodules in the set A obtained in the step 6 to obtain a complete digital-analog hybrid integrated circuit netlist.

Preferably, in the step 4, virtuoso software is used to perform software extraction.

Preferably, the step 6 specifically includes deleting the connection line description after each pin name in the pin description obtained in the step 5, and obtaining the pin definition.

Preferably, the simulation language used in the step 62 is VERILOG.

Preferably, the device comprises a transistor, a resistor, and a capacitor.

The method for extracting the netlist of the digital-analog hybrid integrated circuit ensures that the pin definition of the bottom module is completely consistent with the pin definition of the whole netlist when using the bottom module by using the bottom module netlist in the name mapping form directly extracted by a computer, does not need to edit the pin definition and check and modify manually, and improves the efficiency and accuracy when the digital-analog hybrid integrated circuit carries out digital function simulation.

Drawings

FIG. 1 is a flow chart of a method for extracting a digital-analog hybrid integrated circuit netlist according to an embodiment of the invention.

Detailed Description

For a more intuitive and clear description of the technical solution of the present invention, the following detailed description will be given with reference to specific embodiments and example drawings.

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be clearly and completely explained below in connection with the detailed description of the present invention and the corresponding drawings, and it is obvious that the described embodiments are only some, but not all, embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Step 4, extracting a digital-analog hybrid integrated circuit netlist;

Based on adopting CADENCE circuit aided design software, each circuit module in the analog circuit is stored in a circuit library under a certain path in the aided design software environment, and a complete top-layer circuit can be finally built by calling the names of the circuit modules.

A complete version of the netlist for each circuit module stored in the circuit library is as follows:

Module xnor2(Y,A,B,DNW,VN,VP);

Output Y;

Input A,B,DNW,VN,VP;

Specify

Specparam CDS_LIBNAME=”GM605AA_TT”;

Endspecify;

nd2 I3 (net13,DNW,VN,VP,net2,net11);

nd2 I2 (net11,DNW,VN,VP,B,net9);

nd2 I1 (net12,DNW,VN,VP,A,net9);

nd2 I0 (net9,DNW,VN,VP,A,B);

inv1 I4(Y,DNW,VN,VP,net13);

endmodule

the first row of XOR2 represents the name of the current module, and pins which are connected externally and are related to the model are arranged in brackets behind the name of the current module;

Output and Input represent definitions of Output pins and Input pins of all pins of the current module in the first row, respectively;

specify represents defining a call library, a library-corresponding model name, and a netlist memory in the model;

nd2 is the module name of the sub-module called by the circuit module, the sub-module corresponding to the name exists in the library, then the name I3 given by the sub-module in the netlist of the current module is given, and then connecting wires of all pins of the sub-module in the netlist of the current module are placed in brackets.

For example, the I3 sub-module, called is the nd2 circuit module in the library, which has 6 pins, which are connected to net13, DNW, VN, VP, net2, net11 wires, respectively.

The sub-module may be a bottom module, which is a circuit module formed by only calling devices in the library, such as MOS transistors, resistors, capacitors, and the like, without calling other circuit modules in any library.

The sub-modules may also be non-underlying modules, so-called non-underlying modules, which invoke at least one circuit module in the library that is not a device.

For example, the nd2 module only calls two devices, namely an NMOS tube and a PMOS tube, in the library, and is a bottom layer module, while xnor calls a circuit module like nd2, and is a non-bottom layer module.

In the prior art, when extracting a digitized netlist, for a device model formed by extraction, digital simulation cannot be directly performed, for example, a specific example of extracting the netlist by using a bottom module nd2 circuit module is as follows:

Module nd2 (y,dnw,vn,vp,a,b)

pmos_5t M1 [dpw(vn),d(y),b(vp),g(b),s(vp)]

pmos_5t M0 [dpw(vn),s(vp),d(y),g(a),b(vp) ]

nmos_5t M2 [dnw(dnw),b(vn),d(y),g(b),s(net26) ]

nmos_5t M3 [dnw(dnw),d(net26),b(vn),g(a),s(vn) ]

In brackets in the first row are the names of the pins of the nd2 circuit module,

In the second to fifth behavior module, the device name is shown by pmos_5t, the device number is shown by M1, each port of the device is listed in brackets, and the connection name corresponding to the port is shown in brackets.

In the extracted netlist, the devices pmos_5t and nmos_5t cannot be called by the digital simulation tool, so that the whole nd2 model cannot be subjected to digital simulation.

Therefore, the existing processing mode is to directly carry out the simulation digital language function description on the nd2 module by manpower, and one specific description mode is as follows:

Module nd2 (y,dnw,vn,vp,a,b)

Assign y=a&b

The second row represents the digital logic implemented by the nd2 module in simulation language VERILOG, and the 3 pins are not used because the digital logic is irrelevant to the dnw, vn and vp pin connection relations listed in the first row, and in the digital logic simulation process, the power supply, the ground, the substrate and the like of all default devices and the pins irrelevant to the implementation of the digital logic are all correctly connected.

As the called bottom layer module is input manually according to the first row of pin arrangement sequence in the nd2 circuit module, the input is possibly wrong, and once the input is wrong, the corresponding connection relation of the called bottom layer module pins is wrong.

In the invention, netlists stored in each bottom layer module are all deleted, then virtuoso software is utilized for extraction after the netlists are deleted, and as the netlists in the bottom layer module are deleted, virtuoso software can only read pin information defined by the bottom layer module when calling the bottom layer module, pin names are used for defining each connection point of the bottom layer module, and when the generated netlists are called the bottom layer module, each pin and each connection line adopt a name mapping relation, for example, the concrete embodiment form of the bottom layer module nd2 in the extracted netlists is as follows:

nd2 I3 (y(net13), dnw (dnw), vn (vn), vp (vp),a(net2),b(net11));

For the pin connection of each bottom layer module, description is made in a unified name mapping relation of "pin names (connection lines)", for example, A, DNW, VN, VP, B, Y in the above embodiment represents the pin names of the bottom layer modules nd2, and net13, dnw, vn, vp, net2, and net11 represent connection lines of six pins A, DNW, VN, VP, B, Y, respectively.

Meanwhile, a verilog simulation language is adopted, on the premise of not changing pin definition, the function of the bottom layer model nd2 of which the internal netlist is deleted is described and defined in a simulation language form, a bottom layer module model in the simulation language form is obtained, and the extracted netlist and the rewritten bottom layer module models are combined to generate a new netlist, so that simulation can be carried out.

For example, when an engineer manually describes a computer language, such as verilog language, that can be identified by digital simulation of the nd2 module, the netlist of the bottom module extracted by the computer can be directly copied, and the pin definition of the bottom module can be obtained by deleting the connecting wire.

For example, the underlying module nd2 netlist extracted from a computer

nd2 I3 (y(net13), dnw (dnw), vn (vn), vp (vp),a(net2),b(net11));

The connection wire after deleting the pins can obtain the pin definition of the nd2 module

Module nd2 (y, dnw, vn, vp,a,b)

Then add the function description language, assign y=a & b

Obtaining a computer language model of the complete underlying module nd2

Module nd2 (y,dnw,vn,vp,a,b)

Assign y=a&b。

For all bottom layer modules and non-bottom layer modules containing devices, as the digital simulation tool cannot process the sub-modules of the bottom layer modules and the non-bottom layer modules containing devices, the sub-modules are processed by adopting the method, a netlist is extracted by adopting a computer to carry out pin description, and then a module function language is manually added, so that the digital simulation definition of the sub-modules is realized.

The netlist extraction method can avoid model pin connection errors caused by manual pin input errors, changes the original position mapping relation into name mapping, and the obtained model accords with a digital verification format without excessive modification. The accuracy is improved and the working time is shortened.

The foregoing description of the preferred embodiments of the present invention is not obvious contradiction or on the premise of a certain preferred embodiment, but all the preferred embodiments can be used in any overlapped combination, and the embodiments and specific parameters in the embodiments are only for clearly describing the invention verification process of the inventor and are not intended to limit the scope of the invention, and the scope of the invention is still subject to the claims, and all equivalent structural changes made by applying the specification and the content of the drawings of the present invention are included in the scope of the invention.

Claims

1. A method for extracting a netlist of a digital-analog hybrid integrated circuit, comprising the following steps:

Step 1. In the CADENCE circuit-aided design software environment, find the simulation library called by the mixed-signal integrated circuit whose netlist needs to be extracted;

Step 2. Find out the submodules in the simulation library that directly call the device and can describe the functions in the simulation language, and define the set as A;

Step 3. Delete the submodule netlists of all submodules in set A found in step 2;

Step 4. Extract the digital-analog hybrid integrated circuit netlist;

Step 5. Find the pin description used when calling all submodules in set A in the digital-analog hybrid integrated circuit netlist;

Step 6. Rewrite the internal netlist of each submodule in set A, specifically:

Step 61. Based on the pin description obtained in step 5, write the pin definition of each submodule;

Step 62. Based on the pin definition of step 61, describe the submodule function in simulation language to obtain the submodule netlist;

Step 7. Combine the netlist of the digital-analog hybrid integrated circuit obtained in step 4 and the sub-module netlists of all sub-modules in set A obtained in step 6 to obtain a complete netlist of the digital-analog hybrid integrated circuit.

2. The method for extracting a netlist of a digital-analog hybrid integrated circuit as described in claim 1, characterized in that in step 4, virtuoso software is used to perform software extraction.

3. The method for extracting a netlist of a hybrid integrated circuit as described in claim 1 is characterized in that the step 6 specifically comprises: deleting the connection line description after each pin name in the pin description obtained in step 5 to obtain the pin definition.

4. The method for extracting a netlist of a digital-analog hybrid integrated circuit as claimed in claim 1, wherein the simulation language used in step 62 is VERILOG.

5. The method for extracting a netlist of a hybrid integrated circuit as claimed in claim 1, wherein the devices include transistors, resistors, and capacitors.