CN120123141B - Coding and decoding method, device and electronic equipment - Google Patents
Coding and decoding method, device and electronic equipmentInfo
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- CN120123141B CN120123141B CN202510592635.3A CN202510592635A CN120123141B CN 120123141 B CN120123141 B CN 120123141B CN 202510592635 A CN202510592635 A CN 202510592635A CN 120123141 B CN120123141 B CN 120123141B
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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Abstract
本发明公开了一种编解码方法、装置及电子设备。该方法包括如下步骤：S1.编码步骤；S2.数据选择步骤；S3.解码步骤。将减重编解码与ECC编解码结合。方法一改变ECC的编码方式，通过对用户数据位和校验位分开取反，使ECC编解码具备减重功能。方法二同时改变ECC的输入数据和编码方式，首先通过第一层减重编码改变ECC的输入数据，使ECC可以生成汉明重量更小的校验位，然后通过对校验位取反使ECC编解码进一步具备减重功能。
The present invention discloses a coding and decoding method, device and electronic device. The method includes the following steps: S1. Coding step; S2. Data selection step; S3. Decoding step. Combining weight reduction coding and decoding with ECC coding and decoding. Method 1 changes the coding method of ECC, and enables the ECC coding and decoding to have a weight reduction function by separately inverting the user data bits and the check bits. Method 2 simultaneously changes the input data and coding method of ECC. First, the input data of ECC is changed through the first layer of weight reduction coding, so that ECC can generate a check bit with a smaller Hamming weight, and then the ECC coding and decoding is further enabled to have a weight reduction function by inverting the check bits.
Description
Technical Field
The present invention relates to coding and decoding methods, and in particular, to a coding and decoding method, a device, and an electronic apparatus.
Background
Spin transfer torque magnetic random access memory (SPIN TRANSFER Torque Magnetic Random Access Memory, STT-MRAM) is a future preferred solution in the field of embedded nonvolatile memory (embedded Nonvolatile Memories, eNVM) by virtue of its non-volatility, high endurance, high storage density, and full compatibility with CMOS processes. However, the reliability of STT-MRAM is affected by write failure, read disturb, and short hard errors, all of which have asymmetric behavior.
1) Write failure. The writing of stored data in STT-MRAM is an asymmetric process, and the "0- > 1" writing takes longer than the "1- > 0" writing, with the same write current amplitude. The write reliability of the STT-MRAM cell is therefore largely dependent on the failure rate of the "0- > 1" write.
2) Read disturb failure. To improve reliability, the direction of the STT-MRAM read current is typically designed to be the same as the current direction for a "1- > 0" write. Thus, a read disturb failure affects only the high resistance state cells storing a "1" and not the low resistance state cells storing a "0".
3) Short circuit hard errors. STT-MRAM continues to be used during the life cycle, causing oxide barrier breakdown or oxide thickness variation, resulting in a short-circuit hard error of the memory cell, manifested as a permanent failure Stuck at "0" (structure-at-0).
By reducing the hamming weight of the stored codeword, the asymmetry of the STT-MRAM failure can be utilized to effectively reduce the probability of "0- > 1" writing and reading "1", thereby reducing the write failure and the read disturbance failure. Meanwhile, the method can increase the probability of writing '0' into the short-circuit bit, so that correct data can be directly read out from the short-circuit bit, and the error correction pressure of short-circuit hard errors to ECC is relieved.
However, conventional ECC codecs do not have the ability to reduce hamming weight.
Disclosure of Invention
In order to solve the problems, the application provides a coding and decoding method, a coding and decoding device and electronic equipment.
The invention provides the following technical scheme:
A coding and decoding method comprising the steps of:
S1, collecting step
Collecting binary data to form source codes;
Binary data as described herein may be any set of discretized digital information of any bit width from any data source in any storage form. Any storage morphology includes, but is not limited to, electronic charge storage morphology, magnetic domain orientation storage morphology, photon modulation storage morphology, resistive effect storage morphology, and the like. Any data source includes, but is not limited to, a computing device generation source, a physical environment awareness source, a biological signal source, a human-machine interaction source, and the like.
S2, coding step
S2.1, generating ECC check bits through ECC coding according to the source codes, adding first flag bits for marking the data states of the ECC check bits, and splicing the source codes, the ECC check bits and the first flag bits to form a first group of data; inverting the ECC check bit to obtain an inverse code of the ECC check bit, and simultaneously inverting the first flag bit to obtain an inverse code of the first flag bit, and splicing the source code, the inverse code of the ECC check bit and the inverse code of the first flag bit to form a second group of data;
S2.2, adding a second flag bit for marking the data state of the source code after the first group of data to serve as first group of output data, inverting the first group of output data to obtain the inverse code of the first group of output data to serve as second group of output data, adding a second flag bit after the second group of data to serve as third group of output data, inverting the third group of output data to obtain the inverse code of the third group of output data to serve as fourth group of output data, wherein the data state of the source code is the original state or the inverted state;
s3, data selection step
Respectively calculating the Hamming weight of the first group of output data, the second group of output data, the third group of output data and the fourth group of output data, and selecting a group of data with the minimum Hamming weight as storage data;
S4, decoding step
S4.1, respectively restoring ECC check bits and source codes according to the first flag bits and the second flag bits of the stored data;
s4.2, performing ECC decoding according to the restored source codes and the ECC check bits.
The device for realizing the coding and decoding method at least comprises the following components:
The acquisition module is used for acquiring binary data to form source codes;
The encoding module generates ECC check bits according to the source codes through ECC encoding, adds first flag bits for marking the data states of the ECC check bits, splices the source codes, the ECC check bits and the first flag bits to form a first group of data, inverts the ECC check bits to obtain the inverted codes of the ECC check bits, simultaneously, inverts the first flag bits to obtain the inverted codes of the first flag bits, splices the inverted codes of the source codes, the ECC check bits and the inverted codes of the first flag bits to form a second group of data, wherein the data states of the ECC check bits are in an original state or an inverted state, adds the second flag bits for marking the data states of the source codes after the first group of data to serve as the first group of output data, inverts the first group of output data to obtain the inverted codes of the first group of output data to serve as the second group of output data, and adds the second flag bits after the second group of data to serve as the third group of output data;
The data selection module is used for respectively calculating the Hamming weight of the first group of output data, the second group of output data, the third group of output data and the fourth group of output data, and selecting a group of data with the minimum Hamming weight as storage data;
And the decoding module is used for respectively restoring the ECC check bit and the source code according to the first flag bit and the second flag bit of the stored data and carrying out ECC decoding according to the restored source code and the ECC check bit.
A coding and decoding method comprising the steps of:
S1, collecting step
Collecting binary data to form source codes;
s2, coding step
S2.1, forming at least one group of coded data according to a source code through at least one coding mode, adding a first flag bit for marking the source code and the coding mode of the coded data, and splicing the source code and the first flag bit to form a first group of data;
s2.2, generating ECC check bits respectively through ECC coding according to the first group of data and the coding flag data, adding second flag bits for marking the data states of the ECC check bits, splicing the first group of data and the corresponding ECC check bits with the corresponding second flag bits to serve as first group of output data, reversely obtaining the reverse codes of the ECC check bits for the ECC check bits, reversely obtaining the reverse codes of the second flag bits at the same time, splicing the reverse codes of the first group of data and the corresponding ECC check bits with the reverse codes of the corresponding second flag bits to serve as second group of output data, splicing the coding flag data and the corresponding ECC check bits with the second flag bits to serve as first coding flag data to output data, reversely obtaining the reverse codes of the ECC check bits for the coding flag data, reversely obtaining the reverse codes of the second flag bits, and reversely splicing the reverse codes of the coding flag data and the corresponding ECC check bits with the corresponding second flag bits to serve as second coding flag data;
s3, data selection step
If the Hamming weight of the data with the minimum Hamming weight is more than one group, the priority order is selected that the complexity of the decoding modes corresponding to the first group of output data, the second group of output data, the first coding mark data and the second coding mark data is arranged from low to high;
S4, decoding step
S4.1, restoring ECC check bits according to second flag bits of the stored data;
S4.2, performing ECC decoding according to the restored ECC check bits;
s4.3, restoring the source code according to the first flag bit of the ECC decoded data.
Further, the encoding mode at least comprises one of an inverse code, a gray code, a backward exclusive-or code and a cyclic shift code, and the complexity of the decoding mode is arranged into the inverse code, the gray code, the backward exclusive-or code and the cyclic shift code from low to high.
The device for realizing the coding and decoding method at least comprises the following components:
The acquisition module is used for acquiring binary data to form source codes;
The coding module is used for forming at least one group of coded data through at least one coding mode according to the source codes, adding first flag bits for marking the source codes and the coding modes of the coded data, and splicing the source codes and the first flag bits to form a first group of data; the method comprises the steps of forming coded mark data by splicing coded data and first mark bits, respectively generating ECC check bits according to the first group of data and the coded mark data through ECC coding, adding second mark bits for marking the data state of the ECC check bits, splicing the first group of data and corresponding ECC check bits with the corresponding second mark bits to be used as first group of output data, reversely obtaining the reverse code of the ECC check bits for the ECC check bits, reversely obtaining the reverse code of the second mark bits at the same time, splicing the reverse code of the first group of data and the corresponding ECC check bits with the reverse code of the corresponding second mark bits to be used as second group of output data, splicing the coded mark data and the corresponding ECC check bits with the second mark bits to be used as first coded mark data output data, reversely obtaining the reverse code of the ECC check bits for the coded mark data, reversely obtaining the reverse code of the second mark bits at the same time, and reversely splicing the reverse code of the first mark bits with the corresponding second mark bits to be used as second coded mark data or state of the second coded mark bits;
The data selection module is used for respectively calculating the Hamming weight of the first group of output data, the second group of output data, the first coding mark data output data and the second coding mark data output data, and selecting a group of data with the minimum Hamming weight as storage data;
The decoding module restores the ECC check bit according to the second flag bit of the stored data, performs ECC decoding according to the restored ECC check bit, and restores the source code according to the first flag bit of the ECC decoded data.
An electronic device, comprising:
One or more processors;
a memory for storing one or more programs;
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the methods as described above.
A computer readable storage medium having stored thereon computer instructions which when executed by a processor perform the steps of the method as described above.
The beneficial effects of the invention are as follows:
(1) The de-recoding is combined with the ECC encoding. The method changes the coding mode of the ECC, and the ECC coding and decoding have the weight reduction function by separating and inverting the user data bit and the check bit. The second method is to change the input data and the coding mode of the ECC at the same time, firstly, the input data of the ECC is changed through the first layer of de-encoding, so that the ECC can generate check bits with smaller hamming weight, and then the ECC coding and decoding further has the weight reduction function through inverting the check bits.
(2) A number of alternative codec schemes are provided. According to the characteristics of different input data sets, the optimal weight reduction effect of the weight reduction coding mode and the optimal weight reduction coding sequence can be flexibly selected in advance according to the software simulation result, so that the Hamming weight is maximally reduced.
(3) The redundancy cost is small, and the complexity is low. According to the invention, only two flag bits are added to represent the inversion mode or the weight-reduction decoding mode to be performed on the stored data, so that the area overhead is small. The first and second methods generate two parallel data through the first layer coding, and the second layer coding is performed in parallel, so that redundant delay cost is not generated. The negation operation can be directly realized through exclusive or operation in the digital circuit realization, and the complexity is low and the efficiency is high.
Drawings
FIG. 1 is a schematic diagram of an embodiment 1 of a codec method of the present invention;
fig. 2 is a schematic diagram of an embodiment 3 of a coding and decoding method of the present invention.
Detailed Description
In order to further describe the technical means and effects adopted by the present invention for achieving the intended purpose, the following detailed description will refer to the specific implementation, structure, characteristics and effects according to the present invention with reference to the accompanying drawings and preferred embodiments.
The invention combines the de-recoding and ECC encoding and decoding, and adds the first zone bit and the second zone bit, thereby providing reference for the restoration and decoding, and the data with the minimum hamming weight is selected for storage through calculation in the storage process, namely, the data with the minimum 0 to 1 in binary data, thereby reducing the write-in failure fault and the read-out interference fault.
The following examples are provided to further illustrate embodiments of the invention.
Example 1
When writing data, the source code input [ m:0] is input to the ECC encoder. In an ECC encoder, firstly, ECC encoding is carried out on source codes input to generate ECC check bits, then the parity is connected after the input and added with a first flag bit E 0 = "0" to be used as a first group of data input+parity+ "0" and marked as ecc0[ n+1:0], the parity is inverted and connected after the input and added with a first flag bit E 0 = "1" to be used as a second group of data input+ "1" and marked as ecc1[ n+1:0].
Input ecc0 and ecc1 to the de-encoder. In the de-recoder, a second flag bit E 1 = "0" is added after the ecc0 and is used as a first group of output data input+parity+ "0" + "0" and marked as the ecc_r0[ n+2:0], the ecc_r0 is inverted and is used as a second group of output data input+to parity+ "1" + "1" and marked as the ecc_r1[ n+2:0], a second flag bit E 1 = "0" is added after the ecc1 and is used as a third group of output data input+to parity+ "1" + "0" and marked as the ecc_r2[ n+2:0], and the ecc_r2 is inverted and is used as a fourth group of output data input+parity+ "0" + "1" and marked as the ecc_r3[ n+2:0].
And calculating the Hamming weight of four groups of data of the ech_r0-eccr, selecting a group of data with the minimum Hamming weight as storage data, and recording the storage data as the ech_rn+2:0, wherein if more than one group of data with the minimum Hamming weight are selected, the priority order is that the ech_r0 > ech_r2 > ech_r3 > ech_r1.
At the time of data reading, the stored data ecc_r is read to the weight-reduction decoder. In the weight-reducing decoder, the first flag bit E 0 and the ECC check bit are subjected to exclusive OR operation to restore the parity, the second flag bit E 1 and the ECC user data bit are subjected to exclusive OR operation to restore the input, and the output data input+parity of the weight-reducing decoder is obtained and is recorded as ECC [ n:0].
Input eccn 0 to the ECC decoder. In the ECC decoder, the restored input is ECC decoded according to the restored parity to obtain the read data output [ m:0].
The device for realizing the coding and decoding method at least comprises the following components:
The acquisition module is used for acquiring binary data to form source codes;
The encoding module generates ECC check bits according to the source codes through ECC encoding, adds first flag bits for marking the data states of the ECC check bits, splices the source codes, the ECC check bits and the first flag bits to form a first group of data, inverts the ECC check bits to obtain the inverted codes of the ECC check bits, simultaneously, inverts the first flag bits to obtain the inverted codes of the first flag bits, splices the inverted codes of the source codes, the ECC check bits and the inverted codes of the first flag bits to form a second group of data, wherein the data states of the ECC check bits are in an original state or an inverted state, adds the second flag bits for marking the data states of the source codes after the first group of data to serve as the first group of output data, inverts the first group of output data to obtain the inverted codes of the first group of output data to serve as the second group of output data, and adds the second flag bits after the second group of data to serve as the third group of output data;
The data selection module is used for respectively calculating the Hamming weight of the first group of output data, the second group of output data, the third group of output data and the fourth group of output data, and selecting a group of data with the minimum Hamming weight as storage data;
And the decoding module is used for respectively restoring the ECC check bit and the source code according to the first flag bit and the second flag bit of the stored data and carrying out ECC decoding according to the restored source code and the ECC check bit.
An electronic device, comprising:
One or more processors;
a memory for storing one or more programs;
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the methods as described above.
In the embodiments provided in the present application, it should be understood that the disclosed method and system may be implemented in other manners. The above-described method and system embodiments are merely illustrative, for example, flow charts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods and systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
In addition, functional modules in the embodiments of the present application may be integrated together to form a single part, or each module may exist alone, or two or more modules may be integrated to form a single part.
In another aspect, a computer readable storage medium has stored thereon computer instructions which when executed by a processor perform the steps of the method as described above. The computer program implementing the method according to any of the above first aspects when executed by a processor. The functions, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. The storage medium includes a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, an optical disk, or other various media capable of storing program codes.
Example 2
Taking numerical values as examples, the following are concrete:
In this embodiment, the input codeword set is 16bit full data, and the ECC encoding and decoding mode selects BCH codes with correction of 2 and detection of 3. One of the memory addresses has 16 data memory bits, 11 ECC check bits, and 2 flag bits.
The method comprises the steps of writing source codes in 15:0 into the data storage medium, generating ECC check bits in 11'd10111101100 by ECC coding, connecting the parity to the input and adding a first flag bit E 0 = "0", taking the first group of data ecc0[27:0] as 28'd 1101011011011_10111101100_0, connecting the parity inverse to the input and adding a first flag bit E 0 = "1", and taking the second group of data ecc1[27:0] as 28'd1101011101011011_01000010011_1.
Input ecc0 and ecc1 to the de-encoder. In the de-recoder, a second flag bit E 1 = "0" is added after the ecc0, the first group of output data ecc_r0[28:0] is 29'd1101011101011011_10111101100_0_0, the ecc_r0 is inverted to obtain a second group of output data ecc_r1[28:0] which is 29'd 0010100010100100_01010011_1_1, the second flag bit E 1 = "0" is added after the ecc1, the third group of output data ecc_r2[28:0] is 29'd 1101011011011_01000010011_1_0, the second group of output data ecc_r2[28:0] is inverted to obtain a fourth group of output data ecc_r3[28:0] which is 29'd 0010100010100100100_11101100_0_1.
The hamming weight of the four sets of data after two layers of encoding is calculated and compared, the hamming weight of the codeword is denoted by H (), H (ecc_r0) =18, H (ecc_r1) =11, H (ecc_r2) =16, H (ecc_r3) =13, and ecc_r1 is selected as the stored data and denoted as ecc_r.
Suppose that the data ecc_r has a two-bit soft error during storage, becoming 29'd0011100010100100_11000010011_1_1. When data is read, ecc_r is read to the weight-reduction decoder. In the weight-reducing decoder, the first flag bit ' 1' and the ECC check bit ' 11000010011 ' are subjected to exclusive OR operation to restore the parity to be ' 00111101100 ', the second flag bit ' 1' and the ECC user data bit ' 0011100010100100 ' are subjected to exclusive OR operation to restore the input to be ' 1100011101011011 ', and the output data ECC [26:0] of the weight-reducing decoder is obtained to be 27'd1100011101011011_00111101100.
Input ECC [26:0] to the ECC decoder. In the ECC decoder, the BCH decoding operation of correcting 2 and 3 is carried out on the restored input according to the restored parity, so that the correct read data output [15:0] is 16'd1101011101011011.
The coding mode of the ECC is changed, and the data bit and the check bit are separated and inverted, so that the ECC coding and decoding has the weight reduction function. The number of times of writing from 0 to 1 is reduced from 18 times to 11 times, the failure rate of writing failure is reduced, and the number of times of reading from 1 to 18 times is reduced, and the failure rate of reading interference is reduced.
Only two bit flag bits are added to represent the inversion mode to be performed for storing data, and the area cost is small. Two groups of parallel data are generated through the first layer of coding, and the second layer of coding is performed in parallel, so that redundant delay cost is not generated. The negation operation is directly realized through exclusive or operation in the digital circuit realization, and the complexity is low and the efficiency is high.
Example 3
When writing data, the source code input [ m:0] is input to the de-recoder. In the de-recoder, a first flag bit E 0 = "000" is added to the source code input as a first group of data input+000, denoted as input0[ m+3:0], the source code input is de-recoded and a first flag bit E 0 is added as encoded flag data input_rx+E 0, denoted as inputx [ m+3:0]. The de-encoding mode is inverse code, gray code, backward exclusive-or code, cyclic shift code, corresponding to x is 1,2, 3 and 4 respectively, and corresponding to the first flag bit E 0 is 001, 010, 011 and 100 respectively. According to the number of coding modes required to be marked, the first flag bit can be 1 bit (two coding modes can be marked), 2 bits (four coding modes can be marked), 3 bits (8 coding modes can be marked), more bits can be adopted, and the setting can be carried out according to actual needs. In this embodiment, the first flag bit uses 3 bits, and 5 different coding modes (including source codes) are marked.
Input0, input1, input2, input3, and input4 are input to the ECC encoder. In an ECC encoder, firstly, ECC encoding is performed on input0 to generate an ECC check bit parity, the parity is connected to the input0 and added with a second flag bit E 1 = "0" to be used as a first group of output data input+ "000" +parity+ "0" and marked as ecc_r0[ n+4:0], the parity is inverted and connected to the input0 and added with a second flag bit E 1 = "1" to be used as a second group of output data input+ "000" + "to parity+"1 "and marked as ecc_r1[ n+4:0]. And then ECC encoding is carried out on the input1 to generate an ECC check bit parity_r1, the parity_r1 is connected to the input1, a second flag bit E 1 = "0" is added, the data input_r1+ "001" +parity_r1+ "0" is marked as ecc_r11[ n+4:0] as a first group of first encoding flag data, the parity_r1 is inverted, the data input_r1+ "001" + "to parity_r1+"1 "is marked as ecc_r12[ n+4:0] as a first group of second encoding flag data output data, and the second flag bit E 1 =" 1 "is added after the input1 is connected. And then ECC encoding is carried out on the input2 to generate an ECC check bit parity_r2, the parity_r2 is connected to the input2 and added with a second flag bit E 1 = "0", the data input_r2+ "010" +parity_r2+ "0" is output as second group of first encoding flag data, and is marked as ecc_r21[ n+4:0], the parity_r2 is inverted and connected to the input2 and added with a second flag bit E 1 = "1", and the data input_r2+ "010" + "to parity_r2+"1 "is output as second group of second encoding flag data, and the data input_r22 [ n+4:0]. And then ECC encoding is carried out on the input3 to generate an ECC check bit parity_r3, the parity_r3 is connected to the input3 and added with a second flag bit E 1 = "0", the data input_r3+ "011" +parity_r3+ "0" is output as a third group of first encoded flag data, and the data input_r31 [ n+4:0] is marked, the parity_r3 is inverted and connected to the input3 and added with a second flag bit E 1 = "1", and the data input_r3+ "011" + "to parity_r3+"1 "is output as a third group of second encoded flag data, and the data input_r32 [ n+4:0] is marked. And then ECC encoding is carried out on the input4 to generate an ECC check bit parity_r4, the parity_r4 is connected to the input4 and added with a second flag bit E 1 = "0", the data input_r4+ "100" +parity_r4+ "0" is marked as ecc_r41[ n+4:0] as the fourth group of first encoding flag data, the parity_r4 is inverted and connected to the input4 and added with a second flag bit E 1 = "1", and the data input_r4+ "100" + -parity_r4+ "1" is marked as ecc_r42[ n+4:0] as the fourth group of second encoding flag data output data.
Calculating the Hamming weight of 10 groups of data, including ech_r0, eccr1, ech_r11, ech_r12, ech_r21, ech_r22, ech_r31, ech_r32, ech_r41 and ech_r42, selecting a group of data with the minimum Hamming weight as storage data, and recording the storage data as ech_rn+4:0, wherein if more than one group of data with the minimum Hamming weight is selected, the priority order is selected that the first group of output data > the second group of output data > the first encoding mark data output data and the decoding mode complexity corresponding to the second encoding mark data output data are arranged from low to high.
At the time of data reading, the stored data ecc_r is read to the ECC decoder. In the ECC decoder, first, the second flag bit E 1 and the ECC check bit are subjected to exclusive OR operation to restore the parity or the parity_r1 or the parity_r2 or the parity_r3 or the parity_r4, and the first group of data or the encoded flag data is subjected to ECC decoding according to the restored ECC check bit to obtain output data of the ECC decoder, namely output + '000' or output_r1+ '001' or output_r2+ '010' or output_r3+ '011' or output_r4+ '100', which is denoted as output_r [ m+3:0].
Input output_r to the weight-reduction decoder. In the weight-reducing decoder, a corresponding weight-reducing decoding mode is selected according to the first flag bit E 0, and read data output [ m:0] is obtained through weight-reducing decoding operation.
The device for realizing the coding and decoding method at least comprises the following components:
The acquisition module is used for acquiring binary data to form source codes;
The coding module is used for forming at least one group of coded data through at least one coding mode according to the source codes, adding first flag bits for marking the source codes and the coding modes of the coded data, and splicing the source codes and the first flag bits to form a first group of data; the method comprises the steps of forming coded mark data by splicing coded data and first mark bits, respectively generating ECC check bits according to the first group of data and the coded mark data through ECC coding, adding second mark bits for marking the data state of the ECC check bits, splicing the first group of data and corresponding ECC check bits with the corresponding second mark bits to be used as first group of output data, reversely obtaining the reverse code of the ECC check bits for the ECC check bits, reversely obtaining the reverse code of the second mark bits at the same time, splicing the reverse code of the first group of data and the corresponding ECC check bits with the reverse code of the corresponding second mark bits to be used as second group of output data, splicing the coded mark data and the corresponding ECC check bits with the second mark bits to be used as first coded mark data output data, reversely obtaining the reverse code of the ECC check bits for the coded mark data, reversely obtaining the reverse code of the second mark bits at the same time, and reversely splicing the reverse code of the first mark bits with the corresponding second mark bits to be used as second coded mark data or state of the second coded mark bits;
The data selection module is used for respectively calculating the Hamming weight of the first group of output data, the second group of output data, the first coding mark data output data and the second coding mark data output data, and selecting a group of data with the minimum Hamming weight as storage data;
The decoding module restores the ECC check bit according to the second flag bit of the stored data, performs ECC decoding according to the restored ECC check bit, and restores the source code according to the first flag bit of the ECC decoded data.
Example 4
Taking numerical values as examples, the following are concrete:
In this embodiment, the input codeword set is 8bit full data, the de-multiplexing decoding mode selects the inverse code, gray code, backward exclusive-or code and cyclic shift code, and the ECC encoding and decoding mode selects the hamming code of 1. One of the memory addresses has 8 data memory bits, 4 ECC check bits, and 4 flag bits.
The write source code input [7:0] is 8' b11100111. In the de-recoder, a first flag bit E 0 = "000" is added to the source code input as a first group of data input0[10:0] is 11' b11100111_000, the source code input is subjected to inverse coding and added with a first flag bit E 0 = "001", as a first group of coded flag data input1[10:0] is 11' b00011000001, the source code input is subjected to gray coding and added with a first flag bit E 0 = "010", as a second group of coded flag data input2[10:0] is 11' b10010100010, the source code input is subjected to backward exclusive or coding and added with a first flag bit E 0 = "011", as a third group of coded flag data input3[10:0] is 11' b 00101_011, the source code input is subjected to cyclic shift coding and added with a first flag bit E 0 = "100", and as a fourth group of coded flag data input2[10:0] is 11' b10010100010 ".
Input0, input1, input2, input3, and input4 are input to the ECC encoder. In an ECC encoder, firstly, ECC encoding is performed on input0 to generate an ECC check bit parity [3:0] as 4' b1000, the parity is connected after the input0 and added with a second flag bit E 1 = "0", the output data eccr 0[15:0] as a first group is 16'11100111_0001000_0, the parity is inverted, the input0 is connected and added with a second flag bit E 1 = "1", and the output data eccr 1[15:0] as a second group is 16'11100111_0000111_1. Then, ECC encoding is performed on input1 to generate an ECC check bit parity_r1[3:0] as 0100, the parity_r1 is connected after input1 and added with a second flag bit E 1 = "0", the output data ecc_r11[15:0] as a first group of first encoded flag data is 16 '00011000_001_0100_0, and the parity_r1 is inverted, connected after input1 and added with a second flag bit E 1 = "1", and the output data ecc_r12[15:0] as a first group of second encoded flag data is 16' 00011000_001_1011_1. Then, ECC encoding is performed on input 2to generate an ECC check bit parity_r2[3:0] as 1100, the parity_r2 is connected after input2 and added with a second flag bit E 1 = "0", the output data ecc_r21[15:0] as the second group of first encoded flag data is 16 '10010100_0101100_0, the parity_r2 is inverted, the input2 is connected and added with a second flag bit E 1 = "1", and the output data ecc_r22[15:0] as the second group of second encoded flag data is 16' 10010100_0100011_1. And then ECC encoding is carried out on the input3 to generate ECC check bit parity_r3[3:0] as 0111, the parity_r3 is connected after the input3 and added with a second flag bit E 1 = "0", the output data ecc_r31[15:0] of the first encoded flag data is 16 '00101001_0111_0, the parity_r3 is inverted and connected after the input3 and added with a second flag bit E 1 = "1", and the output data ecc_r32[15:0] of the second encoded flag data of the third group is 16'00101001 _011000_1. Then, ECC encoding is performed on input4 to generate ECC check bit parity_r4[3:0] as 0001, parity_r4 is connected after input4 and added with a second flag bit E 1 = "0", the output data of the fourth group of first encoded flag data ecc_r41[15:0] as 16 '01111110_1000001_0, and parity_r4 is inverted, connected after input4 and added with a second flag bit E 1 = "1", and the output data of the fourth group of second encoded flag data ecc_r42[15:0] as 16' 01111110_1001110_1.
The hamming weights ,H(ecc_r0)=7,H(ecc_r1)=10,H(ecc_r11)=4,H(ecc_r12)=7,H(ecc_r21)=6,H(ecc_r22)=7,H(ecc_r31)=8,H(ecc_r32)=7,H(ecc_r41)=8,H(ecc_r41)=11, of the two-layer encoded 10-set codewords are calculated and compared, and then ecc_r11 is selected as the stored codeword, denoted ecc_r.
Suppose that the data ecc_r has a three-bit short hard error during storage, becoming 16' b00001000_0010100_0. At the time of data reading, ecc_r is read to the ECC decoder. In the ECC decoder, firstly, the second flag bit '0' and the ECC check bit '0100' are subjected to exclusive OR operation to restore the parity_r1 to be '0100', and then the Hamming code of the data 15'b00001000_0010100 is subjected to error correction 1 decoding to obtain output data output_r [10:0] of the ECC decoder to be 11' b00011000_001.
Input output_r [10:0] to the de-emphasis decoder. In the weight-reducing decoder, the first flag bit ' 001 ' is selected to be the inverse of the first flag bit, and the correct read data output [7:0] is obtained as 8' b11100111 through the weight-reducing decoding operation.
Meanwhile, the input data and the coding mode of the ECC are changed, the input data of the ECC is changed through the first layer of reduction and recoding, so that the ECC generates check bits with smaller hamming weight, and then the ECC coding and decoding further has the weight reduction function through inverting the check bits. The number of times of writing from 0 to 1 is reduced from 8 times to 4 times, the failure rate of writing failure is reduced, the number of times of reading from 1 to 6 times is reduced, and the failure rate of reading interference is reduced. Only two flag bits are added to represent the inversion mode and the weight-reduction decoding mode to be performed for the stored data, so that the area overhead is small. Two groups of parallel data are generated through the first layer of coding, and the second layer of coding is performed in parallel, so that redundant delay cost is not generated. The negation operation is directly realized through exclusive or operation in the digital circuit realization, and the complexity is low and the efficiency is high.
In addition, since DATA4 is stored in the shorted bit, an error occurs in the bit. Although DATA5 and DATA0 are also stored in the shorted bit, since the write DATA is "0", they are consistent with the DATA after the shorted error, and thus the two bits of DATA do not appear as errors. The final ECC decoder detects the 1-bit error and corrects it. If no codec is performed, the DATA of DATA4 is correct, the DATA of DATA5 and DATA0 are wrong, and 2 errors occur together, and cannot be corrected correctly through the hamming code ECC of correction 1.
The present invention is not limited in any way by the above-described preferred embodiments, but is not limited to the above-described preferred embodiments, and any person skilled in the art will appreciate that the present invention can be embodied in the form of a program for carrying out the method of the present invention, while the above disclosure is directed to equivalent embodiments capable of being modified or altered in some ways, it is apparent that any modifications, equivalent variations and alterations made to the above embodiments according to the technical principles of the present invention fall within the scope of the present invention.
Claims (7)
1. A method of encoding and decoding comprising the steps of:
S1, collecting step
Collecting binary data to form source codes;
s2, coding step
S2.1, generating ECC check bits through ECC coding according to the source codes, adding first flag bits for marking the data states of the ECC check bits, and splicing the source codes, the ECC check bits and the first flag bits to form a first group of data; inverting the ECC check bit to obtain an inverse code of the ECC check bit, and simultaneously inverting the first flag bit to obtain an inverse code of the first flag bit, and splicing the source code, the inverse code of the ECC check bit and the inverse code of the first flag bit to form a second group of data;
S2.2, adding a second flag bit for marking the data state of the source code after the first group of data to serve as first group of output data, inverting the first group of output data to obtain the inverse code of the first group of output data to serve as second group of output data, adding a second flag bit after the second group of data to serve as third group of output data, inverting the third group of output data to obtain the inverse code of the third group of output data to serve as fourth group of output data, wherein the data state of the source code is the original state or the inverted state;
s3, data selection step
Respectively calculating the Hamming weight of the first group of output data, the second group of output data, the third group of output data and the fourth group of output data, and selecting a group of data with the minimum Hamming weight as storage data;
S4, decoding step
S4.1, respectively restoring ECC check bits and source codes according to the first flag bits and the second flag bits of the stored data;
s4.2, performing ECC decoding according to the restored source codes and the ECC check bits.
2. An apparatus for implementing a coding and decoding method according to claim 1, comprising at least:
The acquisition module is used for acquiring binary data to form source codes;
The encoding module generates ECC check bits according to the source codes through ECC encoding, adds first flag bits for marking the data states of the ECC check bits, splices the source codes, the ECC check bits and the first flag bits to form a first group of data, inverts the ECC check bits to obtain the inverted codes of the ECC check bits, simultaneously, inverts the first flag bits to obtain the inverted codes of the first flag bits, splices the inverted codes of the source codes, the ECC check bits and the inverted codes of the first flag bits to form a second group of data, wherein the data states of the ECC check bits are in an original state or an inverted state, adds the second flag bits for marking the data states of the source codes after the first group of data to serve as the first group of output data, inverts the first group of output data to obtain the inverted codes of the first group of output data to serve as the second group of output data, and adds the second flag bits after the second group of data to serve as the third group of output data;
The data selection module is used for respectively calculating the Hamming weight of the first group of output data, the second group of output data, the third group of output data and the fourth group of output data, and selecting a group of data with the minimum Hamming weight as storage data;
And the decoding module is used for respectively restoring the ECC check bit and the source code according to the first flag bit and the second flag bit of the stored data and carrying out ECC decoding according to the restored source code and the ECC check bit.
3. A method of encoding and decoding comprising the steps of:
S1, collecting step
Collecting binary data to form source codes;
s2, coding step
S2.1, forming at least one group of coded data according to a source code through at least one coding mode, adding a first flag bit for marking the source code and the coding mode of the coded data, and splicing the source code and the first flag bit to form a first group of data;
s2.2, generating ECC check bits respectively through ECC coding according to the first group of data and the coding flag data, adding second flag bits for marking the data states of the ECC check bits, splicing the first group of data and the corresponding ECC check bits with the corresponding second flag bits to serve as first group of output data, reversely obtaining the reverse codes of the ECC check bits for the ECC check bits, reversely obtaining the reverse codes of the second flag bits at the same time, splicing the reverse codes of the first group of data and the corresponding ECC check bits with the reverse codes of the corresponding second flag bits to serve as second group of output data, splicing the coding flag data and the corresponding ECC check bits with the second flag bits to serve as first coding flag data to output data, reversely obtaining the reverse codes of the ECC check bits for the coding flag data, reversely obtaining the reverse codes of the second flag bits, and reversely splicing the reverse codes of the coding flag data and the corresponding ECC check bits with the corresponding second flag bits to serve as second coding flag data;
s3, data selection step
If the Hamming weight of the data with the minimum Hamming weight is more than one group, the priority order is selected that the complexity of the decoding modes corresponding to the first group of output data, the second group of output data, the first coding mark data and the second coding mark data is arranged from low to high;
S4, decoding step
S4.1, restoring ECC check bits according to second flag bits of the stored data;
S4.2, performing ECC decoding according to the restored ECC check bits;
s4.3, restoring the source code according to the first flag bit of the ECC decoded data.
4. A method according to claim 3, wherein the coding scheme comprises at least one of an inverse code, a gray code, a backward exclusive-or code, and a cyclic shift code.
5. Apparatus for implementing a coding method according to claim 3 or 4, comprising at least:
The acquisition module is used for acquiring binary data to form source codes;
The coding module is used for forming at least one group of coded data through at least one coding mode according to the source codes, adding first flag bits for marking the source codes and the coding modes of the coded data, and splicing the source codes and the first flag bits to form a first group of data; the method comprises the steps of forming coded mark data by splicing coded data and first mark bits, respectively generating ECC check bits according to the first group of data and the coded mark data through ECC coding, adding second mark bits for marking the data state of the ECC check bits, splicing the first group of data and corresponding ECC check bits with the corresponding second mark bits to be used as first group of output data, reversely obtaining the reverse code of the ECC check bits for the ECC check bits, reversely obtaining the reverse code of the second mark bits at the same time, splicing the reverse code of the first group of data and the corresponding ECC check bits with the reverse code of the corresponding second mark bits to be used as second group of output data, splicing the coded mark data and the corresponding ECC check bits with the second mark bits to be used as first coded mark data output data, reversely obtaining the reverse code of the ECC check bits for the coded mark data, reversely obtaining the reverse code of the second mark bits at the same time, and reversely splicing the reverse code of the first mark bits with the corresponding second mark bits to be used as second coded mark data or state of the second coded mark bits;
The data selection module is used for respectively calculating the Hamming weight of the first group of output data, the second group of output data, the first coding mark data output data and the second coding mark data output data, and selecting a group of data with the minimum Hamming weight as storage data;
The decoding module restores the ECC check bit according to the second flag bit of the stored data, performs ECC decoding according to the restored ECC check bit, and restores the source code according to the first flag bit of the ECC decoded data.
6. An electronic device, comprising:
One or more processors;
a memory for storing one or more programs;
When executed by the one or more processors, causes the one or more processors to implement the method of any of claims 1 or 3 or 4.
7. A computer readable storage medium having stored thereon computer instructions which, when executed by a processor, implement the steps of the method of any of claims 1 or 3 or 4.
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