CN120163098B

CN120163098B - On-chip network interface automatic matching method and system based on hierarchical tag driving

Info

Publication number: CN120163098B
Application number: CN202510647029.7A
Authority: CN
Inventors: 高齐; 阮航; 熊梓静; 熊庭刚
Original assignee: Wuhan Lingjiu Microelectronics Co ltd
Current assignee: Wuhan Lingjiu Microelectronics Co ltd
Priority date: 2025-05-20
Filing date: 2025-05-20
Publication date: 2025-09-05
Anticipated expiration: 2045-05-20
Also published as: CN120163098A

Abstract

The invention is suitable for the technical field of chips and provides an automatic matching method and system of a network-on-chip interface based on hierarchical mark driving, wherein the method comprises the steps of extracting module definition, a port list and interface signal information from a module Verilog file; the method comprises the steps of layering and marking interface signals based on naming rules, customizing connection rules, executing an automatic matching algorithm according to marking information to determine connection relations among the signals, generating a complete top-level Verilog code according to matching results, providing a visual interaction interface, providing a layered tree view to display interface states, and supporting screening, grouping and highlighting. The invention is specially designed for large complex chips centering on NoC, realizes high-efficiency and accurate automatic signal connection by systematically analyzing the structural information contained in the signal naming rule, provides a layered visual interface, and helps users to quickly locate and solve the connection problem.

Description

Automatic matching method and system for network-on-chip interfaces based on hierarchical label driving

Technical Field

The invention belongs to the technical field of chips, and particularly relates to an automatic matching method and system for an on-chip network interface based on hierarchical label driving.

Background

With the exponential growth of integrated circuit design scale and complexity, the number of functional blocks and interface signals included in modern chip designs has reached an unprecedented scale. In large system on chip (SoC) design, noC (network on chip) is widely adopted to construct the top layer topology of the chip, all Agent modules communicate through NoC, so that the top layer often contains a large number of module instantiations, the interface is large in scale and complex in structure, but has obvious layering characteristics, the occupation ratio of standard bus interfaces is usually more than 95%, and the existing tools lack special optimization mechanisms for such architecture.

At present, in the design process, the number of interconnection signal lines required to be written manually by a design engineer is often thousands, the top-layer topological structure may need to undergo hundreds of iterative modifications, and the connection work is carried out manually, so that a great amount of engineering time is consumed, errors are easily introduced, and the design reliability is affected.

Although, existing auto-wiring techniques attempt to achieve automated generation of top-level files by manually writing configuration files or template definition module hierarchies and interface information to reduce human intervention. However, when the number of modules exceeds hundred or the complexity of the interface is increased, the maintenance cost of the configuration file increases exponentially, the module name, the port name and the parameters need to be updated manually and synchronously, the operation is time-consuming, spelling errors or parameter omission is easy to introduce, and the design iteration efficiency is low.

In addition, the matching mechanism based on the universal interface name or the keyword cannot process the signal level matching requirement of AXI（Advanced eXtensible Interface）/AHB（Advanced High - performance Bus）/APB（Advanced Peripheral Bus） and other complex bus protocols, and the signals with the same name in multiple modules may cause error connection due to bit width or protocol type difference, but the prior art lacks protocol perception capability, so that signal timing errors need to be debugged manually for the second time. Although some tools allow users to define connection relations, the lack of an intelligent conflict detection mechanism may destroy implicit dependency relations among modules after manual modification, and bit width matching or direction consistency cannot be automatically verified, so that function abnormality after synthesis is caused.

The visual interface design also has the defect that when the module interface exceeds hundred levels, signal groups are not effectively folded or marked in state, a user needs to manually spread a large number of signals, key connection states are difficult to quickly identify, and the debugging efficiency is suddenly reduced.

The protocol version adaptation limitation of naming rules further aggravates maintenance difficulty, and naming conflicts need to modify all relevant modules when the modules need to support multiple protocols or protocol upgrades, and compatibility problems are frequent. The systematic lack of the verification mechanism further enables potential problems such as bit width mismatch, clock domain asynchronism and the like to be discovered in the comprehensive or simulation stage, so that manual row-by-row investigation is time-consuming and labor-consuming. The fundamental contradiction is that the prior art excessively depends on manual input and general matching rules, fails to solve unbalance of automation degree and design complexity in large-scale chip design, and lacks intelligent matching, dynamic priority management and depth verification capability of protocol perception.

Therefore, in general, the existing network-on-chip interface matching method has the problems of low interface matching efficiency, high network-on-chip architecture connection complexity, incapability of uniformly processing diversified standard interfaces, insufficient interface connection state visualization, difficult cooperation between user-defined rules and automatic matching and the like.

Disclosure of Invention

In view of the above problems, the present invention aims to provide a method and a system for automatically matching network interfaces on chip based on hierarchical label driving, which aims to solve the above technical problems.

The invention adopts the following technical scheme:

In one aspect, the hierarchical label driving-based automatic network-on-chip interface matching method includes the following steps:

S1, respectively reading a NoC module file and an Agent module file, and extracting definitions of the NoC module and the Agent module file and all interface signals through grammar analysis;

S2, layering and marking NoC module interface signals and Agent module interface signals according to naming rules, and organizing all marking information into a layering structure;

Step S3, if the user provides a custom configuration file, acquiring a custom connection relation between interfaces according to the configuration file;

Step S4, adopting a multidimensional interface matching algorithm to automatically match according to the marking information to obtain an automatic matching connection relation between interfaces, wherein the priority of the self-defined connection relation is higher than that of the automatic matching connection relation;

And S5, generating a complete top-level Verilog code according to the connection relation table.

Further, the method comprises the following steps:

and S6, displaying the interface state in a layering folding visual tree view mode, and screening, grouping or highlighting according to the operation instruction.

In another aspect, the hierarchical label driving-based automatic network-on-chip interface matching system includes:

The analysis unit is used for respectively reading the NoC module file and the Agent module file, and extracting definitions of the NoC module and the Agent module file and all interface signals through grammar analysis;

The layering marking unit is used for layering marking the NoC module interface signal and the Agent module interface signal according to naming rules and organizing all marking information into a layering structure;

the user-defined processing unit is used for acquiring the user-defined connection relation between the interfaces according to the configuration file if the user provides the user-defined configuration file;

The automatic matching unit is used for automatically matching by adopting a multidimensional interface matching algorithm according to the marking information to obtain an automatic matching connection relation among interfaces, wherein the priority of the self-defined connection relation is higher than that of the automatic matching connection relation;

And the integrated generation unit is used for generating a complete top-level Verilog code according to the connection relation table.

Further, the system further comprises:

GUI unit for displaying interface state in hierarchical folding visualized tree view mode and screening, grouping or highlighting according to operation instruction

The invention has the beneficial effects that the invention provides the automatic matching method and the system of the network-on-chip interface based on the hierarchical mark driving, the technical scheme is specially designed for the large complex chip taking the NoC as the center, the efficient and accurate automatic signal connection is realized by systematically analyzing the structural information contained in the signal naming rule, and the hierarchical visual interface is provided, so that the rapid positioning of a user is helped and the connection problem is solved.

The invention provides a multi-dimensional interface matching algorithm based on NoC architecture characteristics, which is characterized in that connection accuracy is remarkably improved through a standardized naming rule and a hierarchical marking structure, a flexible user-defined connection rule is designed, a clear priority mechanism is established to ensure the cooperative work of automatic matching and user-defined specified connection, a hierarchical visual expression is constructed, the connection state from a module to a signal is intuitively displayed in a multi-level folding mode, success/partial success/failure states are distinguished through color marking, a multi-mode operation engine supporting command lines and a graphical interface is developed, and different development environment requirements are met through unified back-end processing logic.

The technology breaks through the limitation of the universality of the traditional automatic connecting tool, provides a specialized solution for the characteristics of the NoC architecture, and effectively solves the core problems of low interface matching efficiency, high error rate, difficult debugging and the like in the complex chip design.

Drawings

FIG. 1 is a flow chart of a hierarchical label driven based automatic network-on-chip interface matching method provided by a first embodiment of the present invention;

FIG. 2 is a specific flowchart of step S2;

FIG. 3 is a specific flowchart of step S3;

fig. 4 is a specific flowchart of step S4;

fig. 5 is a specific flowchart of step S5;

FIG. 6 is a diagram showing an example interface;

Fig. 7 is a schematic block diagram of an automatic matching system for network interfaces on chip based on hierarchical label driving according to a second embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The invention provides an automatic matching method and system for network interfaces on chip based on hierarchical label driving, which fully utilizes the characteristic that modern chips are interconnected by taking NoC as a center, extracts hierarchical labels based on automatic analysis of NoC module interfaces, identifies the standard interface connection relation between the NoC and all Agent modules, and automatically establishes matching connection. Conventional interface matching methods typically rely on user-predefined connection file inputs without taking into account the specific requirements of modern chip designs. In contrast, the invention utilizes the characteristics of NoC, and can automatically complete the connection of all standard interfaces by only inputting code files without predefining by a user. And the user can obtain the connected top-level files without any intervention. Through a graphical interface optimized for NoC characteristics, a user can quickly find unconnected non-standard interface signals among thousands of connections. The invention also designs a user-defined connection function, and when unconnected non-standard interface signals exist, the user-defined connection configuration is supported to be imported so as to complete the automatic connection of the residual non-standard signals. In order to illustrate the technical scheme of the invention, the following description is made by specific examples.

Embodiment one:

As shown in fig. 1, the present embodiment provides a hierarchical label driving-based automatic matching method for network interfaces on chip, which includes the following steps:

And S1, respectively reading the NoC module file and the Agent module file, and extracting definitions of the NoC module and the Agent module file and all interface signals through grammar analysis.

First, all module Verilog files to be connected are input, including NoC module files and Agent module files, or a directory containing these files is specified. The user may specify the input file or directory through a command line parameter or graphical interface. All input files are then read and parsed using a Verilog parser, extracting key information.

The Verilog file of the NoC module is read first, and the definition of the NoC module and all port signals including information such as signal names, directions (input/output) and bit widths are extracted through grammar analysis. And meanwhile, similar to the processing of the NoC module, the Verilog file of each Agent module is read, and all interface signals are extracted.

And S2, layering and marking the NoC module interface signals and the Agent module interface signals according to naming rules, and organizing all marking information into a layering structure.

In this step, hierarchical marking is applied to the extracted interface signals, standard interfaces are identified and marked, and all interface signals are marked and classified. As shown in fig. 2, the specific procedure of hierarchical marking is as follows:

S21, identifying the standard interface type of each interface signal of the NoC module through the keywords and the structural features in the analyzed signal names.

For the NoC module, this step identifies each interface signal by naming, identifying the standard interface type to which it belongs. The interface signal is named with its naming rule, and in this embodiment, the standard interface type, such as ACE（AXI Coherency Extensions）、AXI（Advanced eXtensible Interface）、AHB（Advanced High-performance Bus）、APB（Advanced Peripheral Bus）, to which the signal belongs is determined by analyzing the keywords and structural features in the signal name. ACE, AXI, AHB, APB is an on-chip bus protocol proposed by the ARM company, and is used for realizing high-speed data transmission and communication between different modules inside a chip.

S22, extracting a target module name and an interface serial number of a target Agent module contained in the signal name, and extracting a channel and a specific signal type to which the interface signal belongs.

For example, "ddrc" is extracted from "ddrc _0_aw_ready" as the target module name, indicating that the signal needs to be connected to the DDR controller module. "0" is extracted from "ddrc _0_aw_ready" as the interface number, indicating that this is the first set of interfaces.

For example, for an AXI interface, channel information (for example, the AXI interface has five independent channels, namely, a read address channel, a read DATA channel, a write address channel, a write DATA channel and a write response channel) and signal types (for example, an effective signal VALID, a READY signal READY, a DATA signal DATA and the like, the VALID and READY signals together form a handshake signal, which is used for synchronization and coordination between master and slave devices, so as to ensure accuracy and stability of DATA transmission).

For the interfaces of AHB, APB and the like, corresponding signal types are extracted as well.

S23, creating a multi-level mark for each interface signal, wherein the multi-level mark comprises an interface type, a target module name, an interface serial number, a channel and a signal type.

Here, a tag containing multiple dimensions of a target module name, an interface type, an interface serial number, a channel, a signal type, and the like is created for each signal based on the information extracted in the foregoing steps.

S24, identifying the standard interface type of the interface signal according to each interface signal of the Agent module, extracting the interface serial number contained in the signal name, and creating a corresponding multi-level mark comprising the interface type and the interface serial number.

Similarly, the interface signals of the Agent module are identified according to similar naming rules. Unlike NoC modules, the Agent module's signal naming typically does not contain the target module name, but instead focuses on interface number and interface type. And then creating a corresponding multi-level mark for each interface signal of the Agent module.

S25, integrating and organizing all the marking information of the NoC module and the Agent module into a tree-shaped hierarchical structure.

In the step, all the marking information of the NoC module and the Agent module are integrated and organized into a tree-shaped hierarchical structure, so that the subsequent matching operation is facilitated.

And S3, if the user provides the custom configuration file, acquiring the custom connection relation between the interfaces according to the configuration file.

The step is custom matching, mainly for the purpose of needing intervention and incapable of automatically matching the nonstandard signal connection relation. If the user provides custom configuration files for custom connections, these configuration file rules are applied to preferentially process connection rules specified by the user through the configuration files. Custom matching has a higher priority than automatic matching.

As shown in fig. 3, the specific procedure of step S3 is as follows:

S31, analyzing a user-defined configuration file provided by a user, and extracting each connection rule from the user-defined configuration file, wherein each connection rule comprises a source module, a source signal, a target module and a target signal.

For example, an Excel table or a configuration file in other formats provided by a user can be read, a connection relationship defined by the user is obtained, and then each connection rule including information such as a source module, a source signal, a target module, a target signal and the like is extracted from the configuration file.

S32, converting the extracted connection rule into a custom connection relationship compatible with the automatic matching connection relationship.

This step converts the extracted connection rules into an internal representation compatible with auto-matching. Before the automatic matching algorithm is performed, the custom connections are first applied, and the custom connection rules of the user are preferably processed, so that the connection is ensured to be established according to the intention of the user. And the interface signals which are connected through the custom rules are marked, so that the influence of the subsequent automatic matching process on the interface signals is avoided. When an automatic match is made, it is checked whether the interface signal has been connected by a custom rule, and if so, the signal is skipped.

And S4, automatically matching by adopting a multidimensional interface matching algorithm according to the marking information to obtain an automatic matching connection relation among interfaces, wherein the priority of the self-defined connection relation is higher than that of the automatic matching connection relation, and finally merging the self-defined connection relation and the automatic matching connection relation to form a complete connection relation table.

Based on the above layered marking, the step adopts a multi-dimensional interface matching algorithm to automatically match, comprehensively considers information of multiple dimensions such as module name, interface type, interface serial number and the like, and realizes high-precision interface matching, as shown in fig. 4, the specific process is as follows:

s41, grouping all the marking information of the NoC modules according to the names of the target modules to obtain each target module group.

S42, for each target module group, grouping is further carried out according to the interface type and the interface serial number.

S43, searching the modules with the same names as the target module names in the parsed Agent modules according to each target module group, and selecting the corresponding interface types and interface serial numbers.

For the above-mentioned automatic matching process, all the tag information of the NoC modules are first grouped according to the target module names, so that the subsequent matching for the specific modules is facilitated. Within each group of target modules, the signals are subdivided by interface type and interface sequence number to form finer groupings. And searching the same name module in the Agent module, and selecting the matched interface type and interface serial number.

S44, performing bidirectional signal preliminary matching between the NoC module interface signal and the Agent module signal, then performing accurate matching according to the function of the signals in the interface, finally verifying whether the bit widths of the signals of the two matched parts are consistent, and marking that the bit widths are inconsistent is a potential problem.

And finally, matching the interface signals in the selected NoC interface group and the Agent interface group. Firstly, performing preliminary matching according to the signal direction (the input of the NoC module corresponds to the output of the Agent module and vice versa), then performing accurate matching according to the function of the interface signal in the interface, and finally verifying whether the bit widths of the matching signals are consistent, and marking that the bit widths are inconsistent is a potential problem.

S45, establishing a connection relation for the successfully matched interface signal pair and updating the connection state, namely automatically matching the connection relation, and recording the unsuccessfully matched signal for subsequent processing or reminding.

Each pair of successfully matched signals is recorded and their connection status is updated in preparation for subsequent code generation. For signals for which no match can be found, it is recorded and displayed in a graphical interface for further processing by the user.

It should be noted that, the priority of the custom connection relationship is higher than the priority of the automatic matching connection relationship, the custom connection relationship of the custom connection rule is processed preferentially, the signal of the custom connection relationship is marked, and the signal marked with the custom connection relationship is skipped when the automatic matching is performed.

Therefore, the automatic matching mode combines multiple dimensions (module name, interface type, interface serial number, signal function and the like) to carry out comprehensive judgment, but not simple character string matching, and the matching accuracy is improved to a great extent.

S46, merging the self-defined connection relation and the automatic matching connection relation to generate a final complete connection relation table.

And finally, combining the self-defined connection relation and the automatic matching connection relation to form a complete connection relation table, and preparing for subsequent code generation. Thus, by this mechanism, the designer is allowed flexibility in handling special situations, such as non-standard named signals, interfaces requiring special handling, or different ways of connection than automatic matching.

Based on the determined connection relation, the step can automatically generate a complete top-level Verilog code, including modular instantiation, signal declaration and connection statement. As shown in fig. 5, the specific process of step S5 is as follows:

s51, generating a top-level module statement, namely creating a Verilog code framework of the top-level module, wherein the Verilog code framework comprises a module name and all required input and output interfaces.

S52, generating an internal wire claim, namely generating a wire claim with a corresponding width for each matched signal pair, and processing unconnected signals according to a preset, such as suspending or connecting a default value. In Verilog, wire types are commonly used to connect signals in combinational logic circuits, such as inter-module connections, gate level circuit inputs and outputs, and the like.

And S53, generating instantiation codes of the NoC module, namely creating instantiation sentences of the NoC module, wherein the instantiation sentences comprise module names, instance names and mapping relations from all interfaces to wire.

S54, generating instantiation codes of the Agent modules, namely creating instantiation sentences for each Agent module, wherein the instantiation sentences also comprise module names, instance names and mapping relations from all interfaces to wires.

S55, writing the generated complete top-level Verilog code into a specified output file.

The code generated by the method has good readability and structure, and is convenient for subsequent manual adjustment or modification. For signals that are not successfully connected, clear comments and default handling are provided, avoiding leaving potential design issues. And the connection result is displayed through the graphical interface, so that the user can verify and debug conveniently. And supports the user to adjust the configuration or manually modify the connection relationship according to the verification result. And outputting the finally determined top-level code to a designated file to complete the whole automatic wire connection process.

In order to help the designer visually view and verify the connection results, the present embodiment provides a hierarchical folding visualization interface.

An interface example is shown in fig. 6, where the interface tree of NoC modules is displayed on the left side of the interface, hierarchically organized by target module name, interface type and interface sequence number, so that the user can quickly locate a specific interface. And displaying an interface tree of the Agent modules on the right side of the interface, wherein a user can select and display a single Agent module or a plurality of Agent modules, so that comparison and analysis are facilitated. Each node displays the statistical information of the connection state, and the statistical information of the connection state, such as the connected 10/12 signal, is displayed on each node, so that the user can know the connection completion degree at a glance.

The method is characterized in that the connection state is displayed by using color codes, for example, green color indicates that all connection is successful, yellow color indicates that part of connection is successful, red color indicates that all connection is failed, the connection state is visually reflected through colors, and the support node is unfolded/folded, so that a user is allowed to unfold or fold any node, and the method is convenient to quickly navigate among different layers and is particularly suitable for processing a large number of signals in large-scale design. In addition, a global screening function is provided, so that a user is allowed to display only unconnected signals and quickly locate a problem area. A filtering function by module name, interface type, etc. is also provided to help the user focus on a particular module or interface.

The visual design greatly simplifies the connection verification process, so that a designer can quickly locate the connection problem, and the debugging efficiency is improved. The whole flow supports a command line mode and a graphical interface mode, and is suitable for different use scenes and user preferences. The command line mode is suitable for integration into an automation script, while the graphical interface mode provides more intuitive operation and feedback, and is particularly suitable for interactive design and debugging.

The method of the embodiment of the invention realizes the complete flow from the input of the Verilog file to the generation of the top-level connecting code and solves the top-level connecting problem in the design of the large-scale system chip.

Embodiment two:

the embodiment provides an automatic matching system of network interfaces on chip based on hierarchical label driving, as shown in fig. 7, the system comprises:

The parsing unit 100 is configured to read the NoC module file and the Agent module file, and parse and extract definitions and all interface signals of the NoC module and the Agent module file;

the layering marking unit 200 is used for layering marking the NoC module interface signal and the Agent module interface signal according to naming rules, and organizing all marking information into a layering structure;

The user-defined processing unit 300 is configured to obtain a user-defined connection relationship between the interfaces according to the configuration file if the user provides the user-defined configuration file;

the automatic matching unit 400 is used for automatically matching by adopting a multidimensional interface matching algorithm according to the marking information to obtain an automatic matching connection relation among interfaces, wherein the priority of the self-defined connection relation is higher than that of the automatic matching connection relation;

and the integrated generation unit 500 is used for generating a complete top-level Verilog code according to the connection relation table.

Further, the system further comprises:

the GUI element 600 is configured to display the interface states in a tree view manner of hierarchical fold visualization, and perform filtering, grouping, or highlighting according to the operation instruction.

The respective functional units of the present embodiment correspondingly implement steps S1-S6 in the implementation. The function units have clear responsibilities and clear interaction relationship. The analysis unit is responsible for extracting module definition, port list and interface signal information from the Verilog file, the layering marking unit block realizes layering marking of interface signals based on naming rules, the user self-defined processing unit manages self-defined connection rules, the automatic matching unit executes an automatic matching algorithm according to marking information to determine connection relations between signals, the integrated generation unit generates a complete top-layer Verilog code according to a matching result, the GUI unit provides a visual interaction interface, provides a layering tree view to display interface states, and supports screening, grouping and highlighting. These functional units work cooperatively to achieve a complete flow from entering Verilog files to generating top level wiring code.

The functional units of the embodiment adopt a modularized design, and have good expansibility and maintainability while maintaining the core function. The units interact through clearly defined interfaces, so that the system can easily add new functions or support new interface types. For example, the system may be extended to support a wider variety of standard bus protocols, or to add more complex matching algorithms to handle special cases.

On one hand, the invention does not need a user to provide extra input, utilizes a NoC structured naming rule system, identifies the target Agent module, the interface type and the interface serial number to be connected by extracting and matching the multi-dimensional hierarchical label of 'module name + interface type + interface serial number', and pertinently realizes the efficient matching of all system interfaces based on the NoC architecture.

On the other hand, the invention designs an efficient automatic matching algorithm for automatic connection of standard interface types according to practical application, and introduces a user-defined rule priority mechanism. By constructing a complete user-defined rule system, a user is allowed to define a specific connection relation through an external configuration file, and a rule application strategy based on priority is implemented in an automatic matching process, so that the special connection requirement and exception handling problem are effectively solved.

In conclusion, the technical scheme of the invention is suitable for all chip designs which are interconnected based on the NoC, and can automatically match and connect standard interface signals under the condition of no need of user intervention, thereby completing signal connection of more than 95% of the top layer. The user only needs to intervene in the residual 5% of nonstandard signal connection relation to finish the complete top-level file, so that the workload of the user is greatly reduced, and the efficiency of chip design iteration is improved.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.

Claims

1. An automatic matching method of network interfaces on a chip based on hierarchical label driving is characterized in that the method comprises the following steps:

s5, generating a complete top-level Verilog code according to the connection relation table;

the specific process in the step S2 is as follows:

S21, identifying the standard interface type of each interface signal of the NoC module through the keywords and the structural features in the analyzed signal names;

s22, extracting a target module name and an interface serial number of a target Agent module contained in the signal name, and extracting a channel and a specific signal type of the interface signal;

S23, establishing a multi-level mark for each interface signal, wherein the multi-level mark comprises an interface type, a target module name, an interface serial number, a channel and a signal type;

s24, identifying the standard interface type of each interface signal of the Agent module, extracting the interface serial number contained in the signal name, and creating a corresponding multi-level mark comprising the interface type and the interface serial number;

2. The hierarchical label driven based network on chip interface automatic matching method of claim 1, further comprising the steps of:

3. The automatic matching method of network-on-chip interfaces based on hierarchical label driving according to claim 2, wherein the specific procedure of step S3 is as follows:

s31, analyzing a user-defined configuration file provided by a user, and extracting each connection rule from the user-defined configuration file, wherein each connection rule comprises a source module, a source signal, a target module and a target signal;

4. The automatic matching method for network interfaces on chip based on hierarchical label driving as set forth in claim 3, wherein the specific procedure in step S4 is as follows:

s41, grouping all marking information of the NoC modules according to the names of the target modules to obtain each target module group;

s42, for each target module group, grouping is further carried out according to the interface type and the interface serial number;

S43, searching the names of the target modules in the parsed Agent modules for each target module group

The modules with the same name are used for selecting the corresponding interface type and interface serial number;

S44, performing bidirectional signal preliminary matching between the NoC module interface signal and the Agent module signal, then performing accurate matching according to the function of the signals in the interface, and finally verifying whether the bit widths of the signals of the two matched parties are consistent, and marking that the bit widths are inconsistent is a potential problem;

S45, establishing a connection relation for the successfully matched interface signal pair and updating a connection state, namely automatically matching the connection relation, and recording an unsuccessfully matched signal for subsequent processing or reminding, wherein the priority of the custom connection relation is higher than that of the automatically matched connection relation, the custom connection relation of the custom connection rule is preferentially processed, the signals of the custom connection relation are marked, and the signals marked with the custom connection relation are skipped when the signals are automatically matched;

5. The automatic matching method of network-on-chip interface based on hierarchical label driving as set forth in claim 4, wherein the specific procedure of step S5 is as follows:

s51, generating a top module statement, namely creating a Verilog code frame of the top module;

S52, generating an internal wire claim, namely generating a wire claim with a corresponding width for each matched signal pair, and processing unconnected signals according to a preset;

S53, generating instantiation codes of the NoC module;

s54, generating instantiation codes of the Agent modules;

6. A hierarchical label driven network-on-chip interface automatic matching system, the system comprising:

the integrated generation unit is used for generating a complete top-level Verilog code according to the connection relation table;

The execution flow of the layering marking unit is as follows:

7. The hierarchical label driven based network on chip interface automatic matching system of claim 6, further comprising:

And the GUI unit is used for displaying the interface state in a layering folding visual tree view mode and carrying out screening, grouping or highlighting according to the operation instruction.